Failure when using both GateMP and Intc

I am developing code for C6678 involving multicore communications/synchronization. Now I encoutered a problem, i.e., using GateMP will fail if Intc is intialized. The tool chain I am using is listed below:

MCSDK: 2.0.1.12

C6678 PDK: 1.0.0.12

IPC: 1.23.0.26

Sys/BIOS: 6.32.01.38

XDC: 3.22.01.21

TI Compiler: 7.3.0

CCS: 5.0.3.00028

The two files at the end of this posting should reproduce the problem. The problem is that calling  CSL_intcInit before calling GateMP_open() by cores 1 to 7 will cause failure in finding the named GateMP created by core 0. If I comment out the line calling  InitIntc() in tsk0_func, calling GateMP_open(0 will succeed after a few loop iterations. Another (related) problem is if I do Intc initialzation after all cores have the GateMP opened, then using the GateMP will causes an assertion failure for cores 1 to 7 with the error message:

ti.sdo.ipc.GateMP: line 208: assertion failure: A_nullArgument: Required argument is null

I would be very grateful for reasons of and solutions to the problem.

Dongning

--------------------------------- main.cpp -------------------------------

#include <xdc/std.h>
#include <string.h>

#include <xdc/runtime/System.h>

#include <ti/ipc/Ipc.h>
#include <ti/ipc/MultiProc.h>

#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>

#include <xdc/cfg/global.h>

#include <ti/ipc/GateMP.h>
#include <ti/csl/src/intc/csl_intc.h>

static Char gateMpName[] = "myGateMpName";
static int regionId = 0;
CSL_IntcContext   intcContext;

enum{
  NUM_INTCS = 2, // Only INTC0 and INTC1 can generate interrupt to core
  NUM_HANDLERS = 10
};

CSL_IntcEventHandlerRecord  EventHandler[NUM_HANDLERS];

void InitIntc(Int32 intcNum)
{
  if(intcNum < 0 || intcNum >= NUM_INTCS)
  {
    System_printf("There are only 4 INTCs!");
    return;
  }

  intcContext.eventhandlerRecord = EventHandler;
  intcContext.numEvtEntries      = NUM_HANDLERS;
  if (CSL_intcInit(&intcContext) != CSL_SOK)
  {
    System_printf("Error: GEM-INTC initialization failed\n");
    return;
  }   

}

extern "C" Void tsk0_func(UArg arg0, UArg arg1)
{
  int coreId = MultiProc_self();
  System_printf("tsk0_func%d\n", coreId);

  InitIntc(coreId >> 2);

  Int              status;
  GateMP_Handle m_handle = NULL;

  if (MultiProc_self() == 0) {

    GateMP_Params params;
    GateMP_Params_init(&params);
    params.localProtect = GateMP_LocalProtect_THREAD;
    params.remoteProtect = GateMP_RemoteProtect_SYSTEM;
    params.name = gateMpName;
    params.regionId = regionId;
    m_handle = GateMP_create(&params);

    System_printf("GateMP_create(%08x)\n", m_handle);

  }
  else {

    do {
      status = GateMP_open(gateMpName, &m_handle);
      if (status < 0) {
        Task_sleep(1);
      }
    } while (status < 0);

    System_printf("GateMP_open(%08x)\n", m_handle);

  }

  System_printf("The test is complete\n");
}

Int main(Int argc, Char* argv[])
{
  Int status = Ipc_start();
  if (status < 0) {
    System_abort("Ipc_start failed\n");
  }

  BIOS_start();

  return (0);
}

------------------------ cfg file ----------------------------------

switch (Program.platformName) {
    case "ti.sdo.ipc.examples.platforms.evm6670.core0":
        var nameList = ["CORE0", "CORE1", "CORE2", "CORE3"];
        break;
    case "ti.sdo.ipc.examples.platforms.evm6678.core0":
        var nameList = ["CORE0", "CORE1", "CORE2", "CORE3",
                        "CORE4", "CORE5", "CORE6", "CORE7"];
        break;
    case "ti.platforms.evm6678":
        var nameList = ["CORE0", "CORE1", "CORE2", "CORE3",
                        "CORE4", "CORE5", "CORE6", "CORE7"];
        break;
    default:
        throw("Platform " + Program.platformName + " not supported by this example");
        break;
}

var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
var Settings = xdc.useModule('ti.csl.Settings');
Settings.useCSLIntcLib = true;

var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
MultiProc.setConfig(null, nameList);
                          
/*
 *  The SysStd System provider is a good one to use for debugging
 *  but does not have the best performance. Use xdc.runtime.SysMin
 *  for better performance.
 */
var System   = xdc.useModule('xdc.runtime.System');
var SysStd   = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;

var Ipc         = xdc.useModule('ti.sdo.ipc.Ipc');
var MultiProc   = xdc.useModule('ti.sdo.utils.MultiProc');

/* BIOS/XDC modules */
var BIOS        = xdc.useModule('ti.sysbios.BIOS');
BIOS.heapSize   = 0x8000;
var Task        = xdc.useModule('ti.sysbios.knl.Task');

var tsk0 = Task.create('&tsk0_func');
tsk0.instance.name = "tsk0";

/* Synchronize all processors (this will be done in Ipc_start) */
Ipc.procSync = Ipc.ProcSync_ALL;

/* Shared Memory base address and length */
var SHAREDMEM           = 0x0C000000;
var SHAREDMEMSIZE       = 0x00200000;

/*
 *  Need to define the shared region. The IPC modules use this
 *  to make portable pointers. All processors need to add this
 *  call with their base address of the shared memory region.
 *  If the processor cannot access the memory, do not add it.
 */
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
      len:  SHAREDMEMSIZE,
      ownerProcId: 0,
      isValid: true,
      name: "DDR2 RAM",
    });
/*
 *  @(#) ti.sdo.ipc.examples.multicore.evm667x; 1, 0, 0, 0,86; 6-18-2011 17:34:50; /db/vtree/library/trees/ipc/ipc.git/src/ ipc-g26
 */