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DRA829V: STREXH instruction sometimes fail to write

Kenley
Intellectual 1775 points
Part Number: DRA829V

Hi team,

The STREXH instruction sometimes fail to write even though there is no memory access from other cores.
If you repeat reading with the LDREXH instruction and writing with the STREXH instruction several times, it succeeds.

Could you tell us about the factors that cause the writing with the STREXH instruction to fail in addition to memory access from other cores?

The core executing the instruction is the main_A72SS0_0 core.

As other cores, we have confirmed that there is no access to the memory read by LDREXH instruction from R5F core in main domain, and the C66C71 core has not started.

Thank you in advance.

Best regards,

Kenley

  • 0
    TI__Mastermind 23795 points

    Hello,

    Exclusives are one class of instruction which can have undefined properties if not executed against MMU-normal memory types.  You need to decode what MMU attributes are in place for the address you are trying to use this against.  If the MMU is OFF, the execution will also be undefined.   Further normal usage requires a check to see if the write was successful, if your core doesn't have the exclusive it won't write.  Some other code might be holding a lock and it needs to release it.

    The ARM exclusives do not work outside of the ARM cluster, the state of a C66 or other core will not effect its state.   The operation is used for light weight coordination inside an SMP cluster.  Usually the operating system will use it to build primitives and typical users do not use these instructions directly, they use the OS primitives which are well tested.

    Sometimes I see people trying to port code which uses these instructions into a boot loader which is running before the MMU us up.  Its common to see that code fail here as its not using it properly.

    Regards,
    Richard W.