TDA4AL-Q1: camera app got stuck while opening I2C0

Hi  TI,

    The patch for SBL startup modification is as follows：

sbl_patch.rar

Before adding SBL modification, the camera work normally, but after adding SBL modification, I2C0 cannot be opened

Hi Ti，

     Please help me check, Thanks.

Hi Qin,

I2C0 is typically allocated to A72 in the dts file, can you please check and confirm that it is removed from the A72? 

Regards,

Brijesh

Hi,  Brijesh,

 Do you mean to add the following code?

&main_i2c0 {
 status = "disabled";
};

Hi qin,

Yes, if you are using i2c0 from R5F, it must be disabled from A72. Otherwise there could be conflicts. 

If it is already disabled, can you please tell me where exactly it is hanging? 

Regards,

Brijesh

Hi  Brijesh，

  our camera use  i2c hardware:

and must disable main_i2c0 ?

&main_i2c0 {
 status = "disabled";
};

Yes, if you are using i2c0 from R5F, then it must be disabled from A72.

&main_i2c0 {
 status = "disabled";
};

Regards,

Brijesh

Dear Brijesh,

      it is already disabled, but  it is hanging in  I2C_open

ok, then is it powered on? Maybe since it is disabled on Linux, noone is powering it on and so it is causing crash in i2c_open, which might be trying to access this register. 

Can you please try powering it on, using below, before calling i2c_open?

SET_DEVICE_STATE_ON(TISCI_DEV_I2C0);

Regards,

Brijesh

Hi Brijesh,

Can the following code be added to the device tree of the A72 ?

+&ti_csi2rx0 {
+ status = "disabled";
+};
+
+&ti_csi2rx1 {
+ status = "disabled";
+};

Hi Qin,

Yes, it should also be added, but i think you are using vision apps, so vision apps dtb file should have taken care, because vision apps uses CSIRX from R5F. 

Rgds,

Brijesh

Hi Brijesh

  i2c0 work ok in MCU2_0 when  disable i2c0 in A72.  But  TDA4 can not recevie any image when sensor stream on:

log:

0.000000 s: ISS: Startling sensor [SENSOR_OX08B40_MAX96717] channel_mask = 0x10 ... !!!
[MCU2_0] 74.255772 s: ImageSensor_RemoteServiceHandler: IM_SENSOR_CMD_STREAM_ON
[MCU2_0] 74.255834 s: IM_SENSOR_CMD_STREAM_ON: channel_mask = 0x10
[MCU2_0] 74.255866 s: IM_SENSOR_CMD_STREAM_ON: 2 channel_mask = 0x10 chId 0
[MCU2_0] 74.255927 s: IssSensor_Start chId = 4
[MCU2_0] 74.255965 s: OX08B40_StreamOn chId: 0x4
[MCU2_0] 74.260896 s: max96716 config start2
[MCU2_0] 74.260925 s: write 96716DES 313 TEST start!!!
[MCU2_0] 74.261372 s: write 96716DES 313 TEST successful!!!
0.000000 s: ISS: Starting sensor [SENSOR_OX08B40_MAX96717] ... !!!

==========================
Demo : Single Camera w/ 2A
==========================

p: Print performance statistics

s: Save Sensor RAW, VISS Output and H3A output images to File System

e: Export performance statistics

u: Update DCC from File System

x: Exit

Enter Choice:
Unsupported command

==========================
Demo : Single Camera w/ 2A
==========================

p: Print performance statistics

s: Save Sensor RAW, VISS Output and H3A output images to File System

e: Export performance statistics

u: Update DCC from File System

x: Exit

Enter Choice: get_dcc_dir_size : Could not open directory or directory is empty /opt/vision_apps/dcc/SENSOR_OX08B40_MAX96717/wdr
[MCU2_0] 74.292893 s: End of max96716 config2
[MCU2_0] 74.292936 s: OX08B40_StreamOn chId: 0x4, status = 0
[MCU2_0] 74.370416 s: OX08B40_GetWBPrgFxn: sensor_pre_gain = 1
[MCU2_0] 74.370640 s: OX08B40_GetExpPrgFxn chId = 4
p

Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD = 0.17 % ( HWI = 0. 1 %, SWI = 0. 1 % )
CPU: mcu2_0: TOTAL LOAD = 34. 0 % ( HWI = 0. 0 %, SWI = 0. 0 % )
CPU: mcu2_1: TOTAL LOAD = 32. 0 % ( HWI = 0. 0 %, SWI = 0. 0 % )
CPU: c7x_1: TOTAL LOAD = 0. 0 % ( HWI = 0. 0 %, SWI = 0. 0 % )
CPU: c7x_2: TOTAL LOAD = 0. 0 % ( HWI = 0. 0 %, SWI = 0. 0 % )

HWA performance statistics,
===========================

HWA: VISS: LOAD = 20.37 % ( 137 MP/s )
HWA: MSC0: LOAD = 26.64 % ( 187 MP/s )

DDR performance statistics,
===========================

DDR: READ BW: AVG = 29 MB/s, PEAK = 3417 MB/s
DDR: WRITE BW: AVG = 508 MB/s, PEAK = 2313 MB/s
DDR: TOTAL BW: AVG = 537 MB/s, PEAK = 5730 MB/s

Detailed CPU performance/memory statistics,
===========================================

DDR_SHARED_MEM: Alloc's: 19 alloc's of 135944945 bytes
DDR_SHARED_MEM: Free's : 0 free's of 0 bytes
DDR_SHARED_MEM: Open's : 19 allocs of 135944945 bytes
DDR_SHARED_MEM: Total size: 536870912 bytes

CPU: mcu2_0: TASK: IPC_RX: 0. 0 %
CPU: mcu2_0: TASK: REMOTE_SRV: 0.80 %
CPU: mcu2_0: TASK: LOAD_TEST: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CPU_0: 0.10 %
CPU: mcu2_0: TASK: TIVX_V1NF: 0. 0 %
CPU: mcu2_0: TASK: TIVX_V1LDC1: 0. 0 %
CPU: mcu2_0: TASK: TIVX_V1SC1: 0. 0 %
CPU: mcu2_0: TASK: TIVX_V1MSC2: 0. 0 %
CPU: mcu2_0: TASK: TIVXVVISS1: 0. 1 %
CPU: mcu2_0: TASK: TIVX_CAPT1: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT2: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DISP1: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DISP2: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CSITX: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT3: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT4: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT5: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT6: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT7: 0. 0 %
CPU: mcu2_0: TASK: TIVX_CAPT8: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DPM2M1: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DPM2M2: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DPM2M3: 0. 0 %
CPU: mcu2_0: TASK: TIVX_DPM2M4: 0. 0 %

CPU: mcu2_0: HEAP: DDR_LOCAL_MEM: size = 16777216 B, free = 16052736 B ( 95 % unused)
CPU: mcu2_0: HEAP: L3_MEM: size = 524288 B, free = 524032 B ( 99 % unused)

CPU: mcu2_1: TASK: IPC_RX: 0. 0 %
CPU: mcu2_1: TASK: REMOTE_SRV: 0. 0 %
CPU: mcu2_1: TASK: LOAD_TEST: 0. 0 %
CPU: mcu2_1: TASK: TIVX_CPU_1: 0. 0 %
CPU: mcu2_1: TASK: TIVX_SDE: 0. 0 %
CPU: mcu2_1: TASK: TIVX_DOF: 0. 0 %
CPU: mcu2_1: TASK: IPC_TEST_RX: 0. 0 %
CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: mcu2_1: TASK: IPC_TEST_TX: 0. 0 %

CPU: mcu2_1: HEAP: DDR_LOCAL_MEM: size = 16777216 B, free = 16773120 B ( 99 % unused)
CPU: mcu2_1: HEAP: L3_MEM: size = 524288 B, free = 524288 B (100 % unused)

CPU: c7x_1: TASK: IPC_RX: 0. 0 %
CPU: c7x_1: TASK: REMOTE_SRV: 0. 0 %
CPU: c7x_1: TASK: LOAD_TEST: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P1: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P2: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P3: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P4: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P5: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P6: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P7: 0. 0 %
CPU: c7x_1: TASK: TIVX_C71_P8: 0. 0 %
CPU: c7x_1: TASK: IPC_TEST_RX: 0. 0 %
CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_1: TASK: IPC_TEST_TX: 0. 0 %

CPU: c7x_1: HEAP: DDR_LOCAL_MEM: size = 268435456 B, free = 268435200 B ( 99 % unused)
CPU: c7x_1: HEAP: L3_MEM: size = 3964928 B, free = 3964928 B (100 % unused)
CPU: c7x_1: HEAP: L2_MEM: size = 458752 B, free = 458752 B (100 % unused)
CPU: c7x_1: HEAP: L1_MEM: size = 16384 B, free = 16384 B (100 % unused)
CPU: c7x_1: HEAP: DDR_SCRATCH_MEM: size = 385875968 B, free = 385875968 B (100 % unused)

CPU: c7x_2: TASK: IPC_RX: 0. 0 %
CPU: c7x_2: TASK: REMOTE_SRV: 0. 0 %
CPU: c7x_2: TASK: LOAD_TEST: 0. 0 %
CPU: c7x_2: TASK: TIVX_CPU: 0. 0 %
CPU: c7x_2: TASK: IPC_TEST_RX: 0. 0 %
CPU: c7x_2: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_2: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_2: TASK: IPC_TEST_TX: 0. 0 %
CPU: c7x_2: TASK: IPC_TEST_TX: 0. 0 %

CPU: c7x_2: HEAP: DDR_LOCAL_MEM: size = 16777216 B, free = 16772608 B ( 99 % unused)
CPU: c7x_2: HEAP: L2_MEM: size = 458752 B, free = 458752 B (100 % unused)
CPU: c7x_2: HEAP: L1_MEM: size = 16384 B, free = 16384 B (100 % unused)
CPU: c7x_2: HEAP: DDR_SCRATCH_MEM: size = 67108864 B, free = 67108864 B (100 % unused)

GRAPH: graph_85 (#nodes = 4, #executions = 3)
NODE: CAPTURE2: node_96: avg = 41718 usecs, min/max = 33274 / 58585 usecs, #executions = 3
NODE: VPAC_VISS1: VISS_Processing: avg = 12626 usecs, min/max = 12415 / 12850 usecs, #executions = 3
NODE: MCU2-0: 2A_AlgNode: avg = 23931 usecs, min/max = 23492 / 24296 usecs, #executions = 3
NODE: VPAC_MSC1: node_107: avg = 17678 usecs, min/max = 17623 / 17778 usecs, #executions = 3

PERF: TOTAL: avg = 0 usecs, min/max = 4294967295 / 0 usecs, #executions = 0

PERF: TOTAL: 0. 0 FPS

 The content of the file k3-j721s2-vision apps. dts is as follows:

k3-j721s2-vision-apps.dts 
#include "k3-j721s2-rtos-memory-map.dtsi"

&main_i2c1 {
status = "disabled";
};

&main_i2c4 {
status = "disabled";
};

&main_i2c5 {
status = "disabled";
};

&serdes_wiz0 {
status = "disabled";
};

&dss {
status = "disabled";
};

&ti_csi2rx0 {
status = "disabled";
};

&ti_csi2rx1 {
status = "disabled";
};
~

daohong qin said:

i2c0 work ok in MCU2_0 when  disable i2c0 in A72.  But  TDA4 can not recevie any image when sensor stream on:

ok, that's difference issue. Is this new camera that you are trying to bringup? Is the camera configured correctly? 

Regards,

Brijesh

Hi Brijesh,

Before adding SBL modification, the camera work normally, but after adding SBL modification, camera can not work.

     The patch for SBL startup modification is as follows：

sbl_patch.rar

Hi Brijesh,

    Is this new camera that you are trying to bringup?

    --> No, is old camera 

Is the camera configured correctly?

   --> yes, Because  camera work ok  before add SBL patch 

Hi  Brijesh,

     please help me check,  Thank you very much. 

Hi Qin,

daohong qin said:

es, Because  camera work ok  before add SBL patch 

I did not get it. What is SBL patch? and before applying SBL patch, do you confirm that it was working fine? 

If it was working fine, what's the dependency on I2C0? 

If possible, please share these SBL changes.. 

Regards,

Brijesh

Hi  Brijesh,

  1. SPL boot,   camera  was working fine 

  2. Add SBL patch,  camera  stuck in i2c open,  and disable i2c0 dtsi in A72, then I2C working fine, but TDA4  capture node does not receive image.   

     SBL patch：6607.sbl_patch.rar

Hi Brijesh,

     Previously, the SDK was SPL boot, and the camera worked normally.Now, it has been switched to SBL boot, and the SBL patch has been added, but the camera does not work properly. Then disable i2c0 dtsi in A72,  I2C working fine, but TDA4  capture node does not receive any image.

Hi Brijesh,

          Are there any new analytical progresses?  please help me check,  Thank you very much.  

Hi Brijesh， 

 Linux sdk patch：

commit e624a3a5d24c274e563e128308e936a7ddb46cf9
Author: niujx <niujx@aicview.com>
Date:   Mon Nov 6 16:41:26 2023 +0800

    [Linux] Config SBL
    
    Configure SBL related data

diff --git a/Makefile b/Makefile
index 615e92a86..975ba9ffc 100755
--- a/Makefile
+++ b/Makefile
@@ -255,7 +255,8 @@ ifeq ($(SBL_PATH),"")
 else
 	cp $(TI_SDK_PATH)/board-support/built-images/tiboot3.bin $(BOOTFS)
 endif
-	
+	cp $(TI_SDK_PATH)/board-support/linux/arch/arm64/boot/Image $(TI_SDK_PATH)/board-support/prebuilt-images/
+
 # Kernel build targets
 linux-jacinto: linux
 linux-jacinto_clean: linux_clean
@@ -315,20 +316,23 @@ linux-dtbs:
 	@echo     Building the Linux Kernel DTBs
 	@echo =====================================
 	$(MAKE) -C $(LINUXKERNEL_INSTALL_DIR) ARCH=arm64 CROSS_COMPILE=$(CROSS_COMPILE) $(DEFCONFIG)
-	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
+	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb     ti/k3-j721s2-common-proc-board_sbl_sd.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
 		$(MAKE) -j $(MAKE_JOBS) -C $(LINUXKERNEL_INSTALL_DIR) DTC_FLAGS=-@ ARCH=arm64 CROSS_COMPILE=$(CROSS_COMPILE) $$DTB; \
 	done
 
 linux-dtbs_stage:
 	mkdir -p $(TI_SDK_PATH)/board-support/built-images
 ifneq ($(SOC_TYPE),gp)
-	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
+	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb    ti/k3-j721s2-common-proc-board_sbl_sd.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
 		$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh $(LINUXKERNEL_INSTALL_DIR)/arch/arm64/boot/dts/$$DTB $(TI_SDK_PATH)/board-support/built-images/$$(basename $$DTB).sec; \
 	done
 else
-	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
+	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb     ti/k3-j721s2-common-proc-board_sbl_sd.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
 		cp $(LINUXKERNEL_INSTALL_DIR)/arch/arm64/boot/dts/$$DTB $(TI_SDK_PATH)/board-support/built-images; \
 	done
+	cp $(LINUXKERNEL_INSTALL_DIR)/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dtb $(TI_SDK_PATH)/board-support/prebuilt-images/;
+	cp $(LINUXKERNEL_INSTALL_DIR)/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb $(TI_SDK_PATH)/board-support/prebuilt-images/;
+	cp $(LINUXKERNEL_INSTALL_DIR)/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_sd.dtb $(TI_SDK_PATH)/board-support/prebuilt-images/;
 endif
 
 linux-dtbs_install: linux-dtbs_stage
@@ -342,7 +346,7 @@ ifeq ($(SOC_TYPE),gp)
 		exit 1; \
 	fi
 	install -d $(DESTDIR)/boot
-	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
+	@for DTB in      ti/k3-am68-sk-base-board.dtb     ti/k3-am68-sk-bb-csi2-ov5640.dtbo     ti/k3-am68-sk-bb-rpi-cam-imx219.dtbo     ti/k3-am68-sk-fpdlink-fusion.dtbo     ti/k3-am68-sk-rpi-hdr-ehrpwm.dtbo     ti/k3-am68-sk-som-ddr_mem_carveout.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-cm-1-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-0-3.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-0.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-1.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-2.dtbo     ti/k3-j721e-fpdlink-imx390-rcm-1-3.dtbo     ti/k3-j721s2-common-proc-board.dtb     ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb     ti/k3-j721s2-common-proc-board_sbl_sd.dtb     ti/k3-j721s2-cpb-csi2-ov5640.dtbo     ti/k3-j721s2-fpdlink-cpb-fusion.dtbo     ti/k3-j721s2-gesi-exp-board.dtbo      ti/k3-j721s2-vision-apps.dtbo     ti/k3-j721s2-edgeai-apps.dtbo 	ti/k3-am68-sk-reve1-base-board.dtb 	ti/k3-am68-sk-reve1-bb-csi2-ov5640.dtbo 	ti/k3-am68-sk-reve1-bb-rpi-cam-imx219.dtbo ; do \
 		install -m 0644 $(TI_SDK_PATH)/board-support/built-images/$$(basename $$DTB) $(DESTDIR)/boot/; \
 	done
 endif
diff --git a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 9de4c0876..68c274112 100644
--- a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -19,7 +19,11 @@ / {
 
 	chosen {
 		stdout-path = "serial2:115200n8";
-		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait";
+	};
+
+	dma_buf_phys {
+		compatible = "ti,dma-buf-phys";
 	};
 
 	aliases {
@@ -976,3 +980,31 @@ gpio {
 		};
 	};
 };
+
+&main_i2c1 {
+    status = "disabled";
+};
+
+&main_i2c4 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+	status = "disabled";
+};
+
+&serdes_wiz0 {
+    status = "disabled";
+};
+
+&dss {
+    status = "disabled";
+};
+
+&ti_csi2rx0 {
+    status = "disabled";
+};
+
+&ti_csi2rx1 {
+    status = "disabled";
+};
diff --git a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dts b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dts
new file mode 100644
index 000000000..b6edae529
--- /dev/null
+++ b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_emmc_uda.dts
@@ -0,0 +1,1001 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0_sbl.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
+
+/ {
+	compatible = "ti,j721s2-evm", "ti,j721s2";
+	model = "Texas Instruments J721S2 EVM";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
+	};
+
+	dma_buf_phys {
+		compatible = "ti,dma-buf-phys";
+	};
+
+	aliases {
+		serial2 = &main_uart0;
+		mmc0 = &main_sdhci0;
+		mmc1 = &main_sdhci1;
+		can0 = &mcu_mcan0;
+		can1 = &main_mcan0;
+		can2 = &mcu_mcan1;
+		can3 = &main_mcan1;
+		can4 = &main_mcan2;
+		can5 = &main_mcan13;
+		can6 = &main_mcan14;
+		can7 = &main_mcan15;
+		can8 = &main_mcan16;
+		ethernet1 = &main_cpsw_port1;
+	};
+
+	evm_12v0: fixedregulator-evm12v0 {
+		/* main supply */
+		compatible = "regulator-fixed";
+		regulator-name = "evm_12v0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: fixedregulator-vsys3v3 {
+		/* Output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_5v0: fixedregulator-vsys5v0 {
+		/* Output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: fixedregulator-sd {
+		/* Output of TPS22918 */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vsys_3v3>;
+		gpio = <&wkup_gpio0 18 GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_sd_dv: gpio-regulator-TLV71033 {
+		/* Output of TLV71033 */
+		compatible = "regulator-gpio";
+		regulator-name = "tlv71033";
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vsys_5v0>;
+		gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+	};
+
+	transceiver1: can-phy1 {
+		compatible = "ti,tcan1043";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 66 GPIO_ACTIVE_LOW>;
+		enable-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
+	};
+
+	transceiver2: can-phy2 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 19 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver3: can-phy3 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan0_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 1 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver4: can-phy4 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan1_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 16 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver5: can-phy5 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 17 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver6: can-phy6 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan13_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 22 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver7: can-phy7 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan14_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 8 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver8: can-phy8 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan15_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver9: can-phy9 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan16_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 37 GPIO_ACTIVE_LOW>;
+	};
+
+	dp0_pwr_3v3: fixedregulator-dp0-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp0-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
+		enable-active-high;
+	};
+
+	dp1_pwr_3v3: regulator-dp1-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp1-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	dp0: dp0-connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+		dp-pwr-supply = <&dp0_pwr_3v3>;
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
+
+	panel {
+		compatible = "ti,panel-edp";
+		power-supply = <&dp1_pwr_3v3>;
+
+		port {
+			dp1_panel_in: endpoint {
+				remote-endpoint = <&dp1_out>;
+			};
+		};
+	};
+};
+
+&main_i2c4 {
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&main_i2c4_pins_default>;
+	clock-frequency = <400000>;
+	status = "disabled";
+	exp4: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&main_pmx0 {
+    main_uart0_pins_default: main_uart0_pins_default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x04C, PIN_INPUT, 11) /* CTSn */
+			J721S2_IOPAD(0x050, PIN_OUTPUT, 11) /* RTSn */
+			J721S2_IOPAD(0x0BC, PIN_INPUT, 11) /* RXD */
+			J721S2_IOPAD(0x0C0, PIN_OUTPUT, 11) /* TXD */
+		>;
+       };
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+			J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+			J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+			J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+			J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+			J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
+		>;
+	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+
+	main_mcan0_pins_default: main-mcan0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x068, PIN_INPUT, 0) /* (U28) MCAN0_RX */
+			J721S2_IOPAD(0x064, PIN_INPUT, 0) /* (W28) MCAN0_TX */
+		>;
+	};
+
+	main_mcan1_pins_default: main-mcan1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0c8, PIN_INPUT, 4) /* (AD28) EXT_REFCLK1.MCAN1_RX */
+			J721S2_IOPAD(0x06c, PIN_INPUT, 0) /* (V26) MCAN1_TX */
+		>;
+	};
+
+	main_mcan2_pins_default: main-mcan2-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x078, PIN_INPUT, 0) /* (Y25) MCAN2_RX */
+			J721S2_IOPAD(0x074, PIN_INPUT, 0) /* (R28) MCAN2_TX */
+		>;
+	};
+
+	main_mcan13_pins_default: main-mcan13-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x010, PIN_INPUT, 0) /* (AF28) MCAN13_RX */
+			J721S2_IOPAD(0x00c, PIN_INPUT, 0) /* (AE28) MCAN13_TX */
+		>;
+	};
+
+	main_mcan14_pins_default: main-mcan14-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x018, PIN_INPUT, 0) /* (W23) MCAN14_RX */
+			J721S2_IOPAD(0x014, PIN_INPUT, 0) /* (AD25) MCAN14_TX */
+		>;
+	};
+
+	main_mcan15_pins_default: main-mcan15-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x020, PIN_INPUT, 0) /* (AA23) MCAN15_RX */
+			J721S2_IOPAD(0x01c, PIN_INPUT, 0) /* (Y24) MCAN15_TX */
+		>;
+	};
+
+	main_mcan16_pins_default: main-mcan16-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+			J721S2_IOPAD(0x024, PIN_INPUT, 0) /* (Y28) MCAN16_TX */
+		>;
+	};
+
+	main_i2c4_pins_default: main-i2c4-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */
+			//J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */
+		>;
+	};
+
+	dp0_pins_default: dp0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0b8, PIN_INPUT, 3) /* (AA24) MCASP1_ACLKX.DP0_HPD */
+		>;
+	};
+
+	main_i2c5_pins_default: main-i2c5-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */
+			//J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */
+
+		>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+			J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+			J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+			J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+			J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+			J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+			J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+			J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+			J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+			J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+			J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+			J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+			J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+		>;
+	};
+
+	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+			J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+		>;
+	};
+
+	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+			J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
+		>;
+	};
+
+	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 7) /* (F25) WKUP_GPIO0_11 */
+			J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
+		>;
+	};
+
+	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C19) MCU_OSPI0_D0.WKUP_GPIO0_19 */
+		>;
+	};
+	
+	main_mcan0_gpio_pins_default: main-mcan0-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0c4, PIN_INPUT, 7) /* (E24) WKUP_GPIO0_1 */
+		>;
+	};
+
+	main_mcan1_gpio_pins_default: main-mcan1-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (D19) MCU_OSPI0_CLK.WKUP_GPIO0_16 */
+		>;
+	};
+
+	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (E20) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
+		>;
+	};
+
+	main_mcan13_gpio_pins_default: main-mcan13-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (F18) MCU_OSPI0_D3.WKUP_GPIO0_22 */
+		>;
+	};
+
+	main_mcan14_gpio_pins_default: main-mcan14-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 7) /* (F24) WKUP_GPIO0_8 */
+		>;
+	};
+
+	main_mcan15_gpio_pins_default: main-mcan15-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (G19) MCU_OSPI0_D5.WKUP_GPIO0_24 */
+		>;
+	};
+
+	main_mcan16_gpio_pins_default: main-mcan16-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (A20) MCU_OSPI1_D3.WKUP_GPIO0_37 */
+		>;
+	};
+
+	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+			J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+			J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+			J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+			J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+			J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+			//J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+			J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+		>;
+	};
+};
+
+&main_gpio2 {
+	status = "disabled";
+};
+
+&main_gpio4 {
+	status = "disabled";
+};
+
+&main_gpio6 {
+	status = "disabled";
+};
+
+&wkup_gpio1 {
+	status = "disabled";
+};
+
+&wkup_uart0 {
+	status = "reserved";
+};
+
+&main_uart0 {
+       /* UART for Main debug console*/
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart0_pins_default>;
+       power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+};
+
+&main_uart1 {
+	status = "disabled";
+};
+
+&main_uart2 {
+	status = "disabled";
+};
+
+&main_uart3 {
+	status = "disabled";
+};
+
+&main_uart4 {
+	status = "disabled";
+};
+
+&main_uart5 {
+	status = "disabled";
+};
+
+&main_uart6 {
+	status = "disabled";
+};
+
+&main_uart7 {
+	status = "disabled";
+};
+
+&main_uart8 {
+    status = "disabled";
+};
+
+&main_uart9 {
+	status = "disabled";
+};
+
+&main_i2c0 {
+	clock-frequency = <400000>;
+
+	exp1: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
+				  "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
+				  "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
+				  "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
+				  "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
+	};
+
+	exp2: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
+				  "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
+				  "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
+				  "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
+				  "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
+				  "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
+	};
+};
+
+&main_i2c1 {
+	status = "disabled";
+};
+
+&main_i2c2 {
+	status = "disabled";
+};
+
+&main_i2c3 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+//	pinctrl-names = "default";
+//	pinctrl-0 = <&main_i2c5_pins_default>;
+	clock-frequency = <400000>;
+	status = "disabled";
+
+	exp5: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&main_i2c6 {
+	status = "disabled";
+};
+
+&main_spi4 {
+	status = "disabled";
+};
+
+&mcu_spi0 {
+	status = "disabled";
+};
+
+&mcu_spi1 {
+	status = "disabled";
+};
+
+&mcu_spi2 {
+	status = "disabled";
+};
+
+&main_sdhci0 {
+	/* eMMC */
+        bus-width = <8> ;
+	non-removable;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&main_sdhci1 {
+	/* SD card */
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	pinctrl-names = "default";
+	disable-wp;
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vdd_sd_dv>;
+};
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy0>;
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+		      <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+	clock-frequency = <100000000>;
+};
+
+&serdes0 {
+	serdes0_pcie_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz0 1>;
+	};
+};
+
+&usb_serdes_mux {
+	idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&edp_serdes_mux {
+	idle-states = <1>; /* EDP0 to SERDES lane 2/3 */
+};
+
+&usbss0 {
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
+
+&pcie1_rc {
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
+&pcie1_ep {
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+	status = "disabled";
+};
+
+&ospi1 {
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+	status = "disabled";
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <40000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&tscadc0 {
+	status = "okay";
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&tscadc1 {
+	status = "okay";
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&mcu_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan0_pins_default>;
+	phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan1_pins_default>;
+	phys = <&transceiver2>;
+};
+
+&dss {
+	/*
+	 * These clock assignments are chosen to enable the following outputs:
+	 *
+	 * VP0 - DisplayPort SST
+	 * VP1 - DPI0
+	 * VP2 - DSI
+	 * VP3 - DPI1
+	 */
+
+	assigned-clocks = <&k3_clks 158 2>,
+			  <&k3_clks 158 5>,
+			  <&k3_clks 158 14>,
+			  <&k3_clks 158 18>;
+	assigned-clock-parents = <&k3_clks 158 3>,
+				 <&k3_clks 158 7>,
+				 <&k3_clks 158 16>,
+				 <&k3_clks 158 22>;
+};
+
+&dss_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dpi0_out: endpoint {
+			remote-endpoint = <&dp0_in>;
+		};
+	};
+
+	port@2 {
+		reg = <2>;
+		dpi2_out: endpoint {
+			remote-endpoint = <&dsi0_in>;
+		};
+	};
+};
+
+&dsi0_ports {
+	port@0 {
+		reg = <0>;
+		dsi0_out: endpoint {
+			remote-endpoint = <&dp1_in>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+		dsi0_in: endpoint {
+			remote-endpoint = <&dpi2_out>;
+		};
+	};
+};
+
+&dsi_edp_bridge_ports {
+	port@0 {
+		reg = <0>;
+		dp1_in: endpoint {
+			remote-endpoint = <&dsi0_out>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+		dp1_out: endpoint {
+			remote-endpoint = <&dp1_panel_in>;
+		};
+	};
+};
+
+&mhdp {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp0_pins_default>;
+	cdns,no-hpd;
+};
+
+&dp0_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dp0_in: endpoint {
+			remote-endpoint = <&dpi0_out>;
+		};
+	};
+
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp0_connector_in>;
+		};
+	};
+};
+
+&main_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan0_pins_default>;
+	phys = <&transceiver3>;
+};
+
+&main_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan1_pins_default>;
+	phys = <&transceiver4>;
+};
+
+&main_mcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan2_pins_default>;
+	phys = <&transceiver5>;
+};
+
+&main_mcan3 {
+	status = "disabled";
+};
+
+&main_mcan4 {
+	status = "disabled";
+};
+
+&main_mcan5 {
+	status = "disabled";
+};
+
+&main_mcan6 {
+	status = "disabled";
+};
+
+&main_mcan7 {
+	status = "disabled";
+};
+
+&main_mcan8 {
+	status = "disabled";
+};
+
+&main_mcan9 {
+	status = "disabled";
+};
+
+&main_mcan10 {
+	status = "disabled";
+};
+
+&main_mcan11 {
+	status = "disabled";
+};
+
+&main_mcan12 {
+	status = "disabled";
+};
+
+&main_mcan13 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan13_pins_default>;
+	phys = <&transceiver6>;
+};
+
+&main_mcan14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan14_pins_default>;
+	phys = <&transceiver7>;
+};
+
+&main_mcan15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan15_pins_default>;
+	phys = <&transceiver8>;
+};
+
+&main_mcan16 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan16_pins_default>;
+	phys = <&transceiver9>;
+};
+
+&main_mcan17 {
+	status = "disabled";
+};
+
+&main_cpsw {
+	status = "disabled";
+};
+
+&csi0_port0 {
+	status = "disabled";
+};
+
+&csi0_port1 {
+	status = "disabled";
+};
+
+&csi0_port2 {
+	status = "disabled";
+};
+
+&csi0_port3 {
+	status = "disabled";
+};
+
+&csi0_port4 {
+	status = "disabled";
+};
+
+&csi1_port0 {
+	status = "disabled";
+};
+
+&csi1_port1 {
+	status = "disabled";
+};
+
+&csi1_port2 {
+	status = "disabled";
+};
+
+&csi1_port3 {
+	status = "disabled";
+};
+
+&csi1_port4 {
+	status = "disabled";
+};
+
+&wkup_i2c0 {
+	status = "okay";
+	tps6594x: tps6594x@48 {
+		compatible = "ti,tps6594x";
+		reg = <0x48>;
+		ti,system-power-controller;
+
+		rtc {
+			compatible = "ti,tps6594x-rtc";
+		};
+
+		gpio {
+			compatible = "ti,tps6594x-gpio";
+		};
+	};
+};
+
+&main_i2c1 {
+    status = "disabled";
+};
+
+&main_i2c4 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+	status = "disabled";
+};
+
+&serdes_wiz0 {
+    status = "disabled";
+};
+
+&dss {
+    status = "disabled";
+};
+
+&ti_csi2rx0 {
+    status = "disabled";
+};
+
+&ti_csi2rx1 {
+    status = "disabled";
+};
diff --git a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_sd.dts b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_sd.dts
new file mode 100644
index 000000000..d67bd80c5
--- /dev/null
+++ b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board_sbl_sd.dts
@@ -0,0 +1,1001 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0_sbl.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
+
+/ {
+	compatible = "ti,j721s2-evm", "ti,j721s2";
+	model = "Texas Instruments J721S2 EVM";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait";
+	};
+
+	dma_buf_phys {
+		compatible = "ti,dma-buf-phys";
+	};
+
+	aliases {
+		serial2 = &main_uart0;
+		mmc0 = &main_sdhci0;
+		mmc1 = &main_sdhci1;
+		can0 = &mcu_mcan0;
+		can1 = &main_mcan0;
+		can2 = &mcu_mcan1;
+		can3 = &main_mcan1;
+		can4 = &main_mcan2;
+		can5 = &main_mcan13;
+		can6 = &main_mcan14;
+		can7 = &main_mcan15;
+		can8 = &main_mcan16;
+		ethernet1 = &main_cpsw_port1;
+	};
+
+	evm_12v0: fixedregulator-evm12v0 {
+		/* main supply */
+		compatible = "regulator-fixed";
+		regulator-name = "evm_12v0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: fixedregulator-vsys3v3 {
+		/* Output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_5v0: fixedregulator-vsys5v0 {
+		/* Output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: fixedregulator-sd {
+		/* Output of TPS22918 */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vsys_3v3>;
+		gpio = <&wkup_gpio0 18 GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_sd_dv: gpio-regulator-TLV71033 {
+		/* Output of TLV71033 */
+		compatible = "regulator-gpio";
+		regulator-name = "tlv71033";
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vsys_5v0>;
+		gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+	};
+
+	transceiver1: can-phy1 {
+		compatible = "ti,tcan1043";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 66 GPIO_ACTIVE_LOW>;
+		enable-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
+	};
+
+	transceiver2: can-phy2 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 19 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver3: can-phy3 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan0_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 1 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver4: can-phy4 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan1_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 16 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver5: can-phy5 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 17 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver6: can-phy6 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan13_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 22 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver7: can-phy7 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan14_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 8 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver8: can-phy8 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan15_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver9: can-phy9 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_mcan16_gpio_pins_default>;
+		standby-gpios = <&wkup_gpio0 37 GPIO_ACTIVE_LOW>;
+	};
+
+	dp0_pwr_3v3: fixedregulator-dp0-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp0-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
+		enable-active-high;
+	};
+
+	dp1_pwr_3v3: regulator-dp1-prw {
+		compatible = "regulator-fixed";
+		regulator-name = "dp1-pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	dp0: dp0-connector {
+		compatible = "dp-connector";
+		label = "DP0";
+		type = "full-size";
+		dp-pwr-supply = <&dp0_pwr_3v3>;
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
+
+	panel {
+		compatible = "ti,panel-edp";
+		power-supply = <&dp1_pwr_3v3>;
+
+		port {
+			dp1_panel_in: endpoint {
+				remote-endpoint = <&dp1_out>;
+			};
+		};
+	};
+};
+
+&main_i2c4 {
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&main_i2c4_pins_default>;
+	clock-frequency = <400000>;
+	status = "disabled";
+	exp4: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&main_pmx0 {
+    main_uart0_pins_default: main_uart0_pins_default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x04C, PIN_INPUT, 11) /* CTSn */
+			J721S2_IOPAD(0x050, PIN_OUTPUT, 11) /* RTSn */
+			J721S2_IOPAD(0x0BC, PIN_INPUT, 11) /* RXD */
+			J721S2_IOPAD(0x0C0, PIN_OUTPUT, 11) /* TXD */
+		>;
+       };
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
+			J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
+			J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+			J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
+			J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+			J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
+			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
+			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
+		>;
+	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+
+	main_mcan0_pins_default: main-mcan0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x068, PIN_INPUT, 0) /* (U28) MCAN0_RX */
+			J721S2_IOPAD(0x064, PIN_INPUT, 0) /* (W28) MCAN0_TX */
+		>;
+	};
+
+	main_mcan1_pins_default: main-mcan1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0c8, PIN_INPUT, 4) /* (AD28) EXT_REFCLK1.MCAN1_RX */
+			J721S2_IOPAD(0x06c, PIN_INPUT, 0) /* (V26) MCAN1_TX */
+		>;
+	};
+
+	main_mcan2_pins_default: main-mcan2-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x078, PIN_INPUT, 0) /* (Y25) MCAN2_RX */
+			J721S2_IOPAD(0x074, PIN_INPUT, 0) /* (R28) MCAN2_TX */
+		>;
+	};
+
+	main_mcan13_pins_default: main-mcan13-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x010, PIN_INPUT, 0) /* (AF28) MCAN13_RX */
+			J721S2_IOPAD(0x00c, PIN_INPUT, 0) /* (AE28) MCAN13_TX */
+		>;
+	};
+
+	main_mcan14_pins_default: main-mcan14-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x018, PIN_INPUT, 0) /* (W23) MCAN14_RX */
+			J721S2_IOPAD(0x014, PIN_INPUT, 0) /* (AD25) MCAN14_TX */
+		>;
+	};
+
+	main_mcan15_pins_default: main-mcan15-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x020, PIN_INPUT, 0) /* (AA23) MCAN15_RX */
+			J721S2_IOPAD(0x01c, PIN_INPUT, 0) /* (Y24) MCAN15_TX */
+		>;
+	};
+
+	main_mcan16_pins_default: main-mcan16-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+			J721S2_IOPAD(0x024, PIN_INPUT, 0) /* (Y28) MCAN16_TX */
+		>;
+	};
+
+	main_i2c4_pins_default: main-i2c4-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */
+			//J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */
+		>;
+	};
+
+	dp0_pins_default: dp0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0b8, PIN_INPUT, 3) /* (AA24) MCASP1_ACLKX.DP0_HPD */
+		>;
+	};
+
+	main_i2c5_pins_default: main-i2c5-pins-default {
+		pinctrl-single,pins = <
+			//J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */
+			//J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */
+
+		>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+			J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
+			J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
+			J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
+			J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+			J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
+			J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
+			J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
+			J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+			J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
+			J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
+			J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
+			J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
+		>;
+	};
+
+	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
+			J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
+		>;
+	};
+
+	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+			J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
+		>;
+	};
+
+	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 7) /* (F25) WKUP_GPIO0_11 */
+			J721S2_WKUP_IOPAD(0x180, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
+		>;
+	};
+
+	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C19) MCU_OSPI0_D0.WKUP_GPIO0_19 */
+		>;
+	};
+	
+	main_mcan0_gpio_pins_default: main-mcan0-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0c4, PIN_INPUT, 7) /* (E24) WKUP_GPIO0_1 */
+		>;
+	};
+
+	main_mcan1_gpio_pins_default: main-mcan1-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (D19) MCU_OSPI0_CLK.WKUP_GPIO0_16 */
+		>;
+	};
+
+	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (E20) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
+		>;
+	};
+
+	main_mcan13_gpio_pins_default: main-mcan13-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (F18) MCU_OSPI0_D3.WKUP_GPIO0_22 */
+		>;
+	};
+
+	main_mcan14_gpio_pins_default: main-mcan14-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 7) /* (F24) WKUP_GPIO0_8 */
+		>;
+	};
+
+	main_mcan15_gpio_pins_default: main-mcan15-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (G19) MCU_OSPI0_D5.WKUP_GPIO0_24 */
+		>;
+	};
+
+	main_mcan16_gpio_pins_default: main-mcan16-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (A20) MCU_OSPI1_D3.WKUP_GPIO0_37 */
+		>;
+	};
+
+	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+		pinctrl-single,pins = <
+			J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+			J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+			J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+			J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+			J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+			J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+			//J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+			J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+		>;
+	};
+};
+
+&main_gpio2 {
+	status = "disabled";
+};
+
+&main_gpio4 {
+	status = "disabled";
+};
+
+&main_gpio6 {
+	status = "disabled";
+};
+
+&wkup_gpio1 {
+	status = "disabled";
+};
+
+&wkup_uart0 {
+	status = "reserved";
+};
+
+&main_uart0 {
+       /* UART for Main debug console*/
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_uart0_pins_default>;
+       power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+};
+
+&main_uart1 {
+	status = "disabled";
+};
+
+&main_uart2 {
+	status = "disabled";
+};
+
+&main_uart3 {
+	status = "disabled";
+};
+
+&main_uart4 {
+	status = "disabled";
+};
+
+&main_uart5 {
+	status = "disabled";
+};
+
+&main_uart6 {
+	status = "disabled";
+};
+
+&main_uart7 {
+	status = "disabled";
+};
+
+&main_uart8 {
+    status = "disabled";
+};
+
+&main_uart9 {
+	status = "disabled";
+};
+
+&main_i2c0 {
+	clock-frequency = <400000>;
+
+	exp1: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
+				  "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
+				  "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
+				  "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
+				  "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
+	};
+
+	exp2: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
+				  "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
+				  "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
+				  "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
+				  "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
+				  "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
+	};
+};
+
+&main_i2c1 {
+	status = "disabled";
+};
+
+&main_i2c2 {
+	status = "disabled";
+};
+
+&main_i2c3 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+//	pinctrl-names = "default";
+//	pinctrl-0 = <&main_i2c5_pins_default>;
+	clock-frequency = <400000>;
+	status = "disabled";
+
+	exp5: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&main_i2c6 {
+	status = "disabled";
+};
+
+&main_spi4 {
+	status = "disabled";
+};
+
+&mcu_spi0 {
+	status = "disabled";
+};
+
+&mcu_spi1 {
+	status = "disabled";
+};
+
+&mcu_spi2 {
+	status = "disabled";
+};
+
+&main_sdhci0 {
+	/* eMMC */
+        bus-width = <8> ;
+	non-removable;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&main_sdhci1 {
+	/* SD card */
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	pinctrl-names = "default";
+	disable-wp;
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vdd_sd_dv>;
+};
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy0>;
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+		      <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+	clock-frequency = <100000000>;
+};
+
+&serdes0 {
+	serdes0_pcie_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz0 1>;
+	};
+};
+
+&usb_serdes_mux {
+	idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&edp_serdes_mux {
+	idle-states = <1>; /* EDP0 to SERDES lane 2/3 */
+};
+
+&usbss0 {
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
+
+&pcie1_rc {
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
+&pcie1_ep {
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+	status = "disabled";
+};
+
+&ospi1 {
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+	status = "disabled";
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <40000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&tscadc0 {
+	status = "okay";
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&tscadc1 {
+	status = "okay";
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&mcu_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan0_pins_default>;
+	phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan1_pins_default>;
+	phys = <&transceiver2>;
+};
+
+&dss {
+	/*
+	 * These clock assignments are chosen to enable the following outputs:
+	 *
+	 * VP0 - DisplayPort SST
+	 * VP1 - DPI0
+	 * VP2 - DSI
+	 * VP3 - DPI1
+	 */
+
+	assigned-clocks = <&k3_clks 158 2>,
+			  <&k3_clks 158 5>,
+			  <&k3_clks 158 14>,
+			  <&k3_clks 158 18>;
+	assigned-clock-parents = <&k3_clks 158 3>,
+				 <&k3_clks 158 7>,
+				 <&k3_clks 158 16>,
+				 <&k3_clks 158 22>;
+};
+
+&dss_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dpi0_out: endpoint {
+			remote-endpoint = <&dp0_in>;
+		};
+	};
+
+	port@2 {
+		reg = <2>;
+		dpi2_out: endpoint {
+			remote-endpoint = <&dsi0_in>;
+		};
+	};
+};
+
+&dsi0_ports {
+	port@0 {
+		reg = <0>;
+		dsi0_out: endpoint {
+			remote-endpoint = <&dp1_in>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+		dsi0_in: endpoint {
+			remote-endpoint = <&dpi2_out>;
+		};
+	};
+};
+
+&dsi_edp_bridge_ports {
+	port@0 {
+		reg = <0>;
+		dp1_in: endpoint {
+			remote-endpoint = <&dsi0_out>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+		dp1_out: endpoint {
+			remote-endpoint = <&dp1_panel_in>;
+		};
+	};
+};
+
+&mhdp {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp0_pins_default>;
+	cdns,no-hpd;
+};
+
+&dp0_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+		dp0_in: endpoint {
+			remote-endpoint = <&dpi0_out>;
+		};
+	};
+
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp0_connector_in>;
+		};
+	};
+};
+
+&main_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan0_pins_default>;
+	phys = <&transceiver3>;
+};
+
+&main_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan1_pins_default>;
+	phys = <&transceiver4>;
+};
+
+&main_mcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan2_pins_default>;
+	phys = <&transceiver5>;
+};
+
+&main_mcan3 {
+	status = "disabled";
+};
+
+&main_mcan4 {
+	status = "disabled";
+};
+
+&main_mcan5 {
+	status = "disabled";
+};
+
+&main_mcan6 {
+	status = "disabled";
+};
+
+&main_mcan7 {
+	status = "disabled";
+};
+
+&main_mcan8 {
+	status = "disabled";
+};
+
+&main_mcan9 {
+	status = "disabled";
+};
+
+&main_mcan10 {
+	status = "disabled";
+};
+
+&main_mcan11 {
+	status = "disabled";
+};
+
+&main_mcan12 {
+	status = "disabled";
+};
+
+&main_mcan13 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan13_pins_default>;
+	phys = <&transceiver6>;
+};
+
+&main_mcan14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan14_pins_default>;
+	phys = <&transceiver7>;
+};
+
+&main_mcan15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan15_pins_default>;
+	phys = <&transceiver8>;
+};
+
+&main_mcan16 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mcan16_pins_default>;
+	phys = <&transceiver9>;
+};
+
+&main_mcan17 {
+	status = "disabled";
+};
+
+&main_cpsw {
+	status = "disabled";
+};
+
+&csi0_port0 {
+	status = "disabled";
+};
+
+&csi0_port1 {
+	status = "disabled";
+};
+
+&csi0_port2 {
+	status = "disabled";
+};
+
+&csi0_port3 {
+	status = "disabled";
+};
+
+&csi0_port4 {
+	status = "disabled";
+};
+
+&csi1_port0 {
+	status = "disabled";
+};
+
+&csi1_port1 {
+	status = "disabled";
+};
+
+&csi1_port2 {
+	status = "disabled";
+};
+
+&csi1_port3 {
+	status = "disabled";
+};
+
+&csi1_port4 {
+	status = "disabled";
+};
+
+&wkup_i2c0 {
+	status = "okay";
+	tps6594x: tps6594x@48 {
+		compatible = "ti,tps6594x";
+		reg = <0x48>;
+		ti,system-power-controller;
+
+		rtc {
+			compatible = "ti,tps6594x-rtc";
+		};
+
+		gpio {
+			compatible = "ti,tps6594x-gpio";
+		};
+	};
+};
+
+&main_i2c1 {
+    status = "disabled";
+};
+
+&main_i2c4 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+	status = "disabled";
+};
+
+&serdes_wiz0 {
+    status = "disabled";
+};
+
+&dss {
+    status = "disabled";
+};
+
+&ti_csi2rx0 {
+    status = "disabled";
+};
+
+&ti_csi2rx1 {
+    status = "disabled";
+};
diff --git a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 7220e73c7..99793ad59 100644
--- a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -13,9 +13,9 @@
 / {
 	memory@80000000 {
 		device_type = "memory";
-		/* 16 GB RAM */
+		/* 4 GB RAM */
 		reg = <0x00 0x80000000 0x00 0x80000000>,
-		      <0x08 0x80000000 0x03 0x80000000>;
+		      <0x08 0x80000000 0x00 0x80000000>;
 	};
 
 	/* Reserving memory regions still pending */
@@ -452,3 +452,239 @@ port@1 {
 		};
 	};
 };
+
+&mcu_r5fss0_core0_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core1_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core0_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core1_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core0_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core1_memory_region {
+	status = "disabled";
+};
+
+&c71_0_dma_memory_region {
+	status = "disabled";
+};
+
+&c71_0_memory_region {
+	status = "disabled";
+};
+
+&c71_1_dma_memory_region {
+	status = "disabled";
+};
+
+&c71_1_memory_region {
+	status = "disabled";
+};
+
+&rtos_ipc_memory_region {
+	status = "disabled";
+};
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	vision_apps_mcu_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a0000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa0000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core0_memory_region: vision-apps-r5f-memory@a0100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa0100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a1000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_memory_region: vision-apps-r5f-memory@a1100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a2000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa2000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core0_memory_region: vision-apps-r5f-memory@a2100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa2100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a4000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa4000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core1_memory_region: vision-apps-r5f-memory@a4100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa4100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core0_dma_memory_region: vision-apps-r5f-dma-memory@a6000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa6000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core0_memory_region: vision-apps-r5f-memory@a6100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa6100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core1_dma_memory_region: vision-apps-r5f-dma-memory@a7000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa7000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core1_memory_region: vision-apps-r5f-memory@a7100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa7100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a8000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa8000000 0x00 0x02000000>;
+		no-map;
+	};
+	vision_apps_memory_region: vision-apps-dma-memory@aa000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xaa000000 0x00 0x06000000>;
+		no-map;
+	};
+	vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@b0000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb0000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@b0100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb0100000 0x00 0x05f00000>;
+		no-map;
+	};
+	vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b6000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb6000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b6100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb6100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_shared_region: vision_apps_shared-memories {
+		compatible = "dma-heap-carveout";
+		reg = <0x00 0xb8000000 0x00 0x20000000>;
+	};
+	vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@d8000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xd8000000 0x00 0x04000000>;
+		no-map;
+	};
+
+	/* This is for getting crash logs using Android downstream kernels */
+	ramoops@DD000000 {
+		compatible = "ramoops";
+		reg = <0x0 0xDD000000 0x0 0x40000>;
+		console-size = <0x10000>;
+		record-size = <0x10000>;
+		ftrace-size = <0x10000>;
+		pmsg-size = <0x20000>;
+	};
+
+	vision_apps_core_heaps_hi: vision-apps-core-heap-memory-hi@880000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x08 0x80000000 0x00 0x2c000000>;
+		no-map;
+	};
+	linux_cma_region: linux-cma-buffers@8ac000000 {
+		compatible = "shared-dma-pool";
+		reusable;
+		reg = <0x08 0xac000000 0x00 0x38000000>;
+		linux,cma-default;
+	};
+};
+
+&mcu_r5fss0_core0 {
+	memory-region = <&vision_apps_mcu_r5fss0_core0_dma_memory_region>,
+			<&vision_apps_mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_mcu_r5fss0_core1_memory_region>;
+	status = "disabled";
+};
+
+&main_r5fss0_core0 {
+	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	memory-region = <&vision_apps_main_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+	memory-region = <&vision_apps_c71_0_dma_memory_region>,
+			<&vision_apps_c71_0_memory_region>;
+};
+
+&c71_1 {
+	memory-region = <&vision_apps_c71_1_dma_memory_region>,
+			<&vision_apps_c71_1_memory_region>;
+};
diff --git a/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0_sbl.dtsi b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0_sbl.dtsi
new file mode 100644
index 000000000..8864953e3
--- /dev/null
+++ b/board-support/linux/arch/arm64/boot/dts/ti/k3-j721s2-som-p0_sbl.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SoM: https://www.ti.com/lit/zip/sprr439
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	memory@80000000 {
+		device_type = "memory";
+		/* 16 GB RAM */
+		reg = <0x00 0x80000000 0x00 0x80000000>,
+		      <0x08 0x80000000 0x00 0x80000000>;
+	};
+
+	/* Reserving memory regions still pending */
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_1_memory_region: c71-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a8000000 {
+			reg = <0x00 0xa8000000 0x00 0x01c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	mux0: mux-controller0 {
+		compatible = "gpio-mux";
+		#mux-state-cells = <1>;
+		mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	mux1: mux-controller1 {
+		compatible = "gpio-mux";
+		#mux-state-cells = <1>;
+		mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
+	};
+
+
+	vsys_io_1v8: regulator-vsys-io-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_io_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_io_1v2: regulator-vsys-io-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_io_1v2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	edp1_refclk: clock-edp1-refclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <19200000>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+		pinctrl-single,pins = <
+			// J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+			J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+			J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+			J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+			J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+			// J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+			J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+			J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+			//J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+			J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+			//J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+			J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+			J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+			J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+			//J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+		>;
+	};
+};
+
+&main_pmx0 {
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
+			J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+		>;
+	};
+
+};
+
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	exp_som: gpio@21 {
+		compatible = "ti,tca6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+				  "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
+				   "GPIO_LIN_EN", "CAN_STB";
+	};
+};
+
+
+&ospi0 {
+//	pinctrl-names = "default";
+//	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+	status = "disabled";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "disabled";
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c71_1: mbox-c71-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	status = "disabled";
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
+
+&mailbox1_cluster0 {
+	status = "disabled";
+};
+
+&mailbox1_cluster1 {
+	status = "disabled";
+};
+
+&mailbox1_cluster2 {
+	status = "disabled";
+};
+
+&mailbox1_cluster3 {
+	status = "disabled";
+};
+
+&mailbox1_cluster4 {
+	status = "disabled";
+};
+
+&mailbox1_cluster5 {
+	status = "disabled";
+};
+
+&mailbox1_cluster6 {
+	status = "disabled";
+};
+
+&mailbox1_cluster7 {
+	status = "disabled";
+};
+
+&mailbox1_cluster8 {
+	status = "disabled";
+};
+
+&mailbox1_cluster9 {
+	status = "disabled";
+};
+
+&mailbox1_cluster10 {
+	status = "disabled";
+};
+
+&mailbox1_cluster11 {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
+
+&c71_1 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
+	memory-region = <&c71_1_dma_memory_region>,
+			<&c71_1_memory_region>;
+};
+
+&main_i2c4 {
+	dsi_edp_bridge: dsi-edp-bridge@2c {
+		compatible = "ti,sn65dsi86";
+		reg = <0x2c>;
+
+		clock-names = "refclk";
+		clocks = <&edp1_refclk>;
+
+		enable-gpios = <&exp_som 5 0>;
+
+		vpll-supply = <&vsys_io_1v8>;
+		vccio-supply = <&vsys_io_1v8>;
+		vcca-supply = <&vsys_io_1v2>;
+		vcc-supply = <&vsys_io_1v2>;
+
+		dsi_edp_bridge_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+			};
+			port@1 {
+				reg = <1>;
+			};
+		};
+	};
+};
+
+&mcu_r5fss0_core0_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core1_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core0_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss0_core1_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core0_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core0_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core1_dma_memory_region {
+	status = "disabled";
+};
+
+&main_r5fss1_core1_memory_region {
+	status = "disabled";
+};
+
+&c71_0_dma_memory_region {
+	status = "disabled";
+};
+
+&c71_0_memory_region {
+	status = "disabled";
+};
+
+&c71_1_dma_memory_region {
+	status = "disabled";
+};
+
+&c71_1_memory_region {
+	status = "disabled";
+};
+
+&rtos_ipc_memory_region {
+	status = "disabled";
+};
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	vision_apps_mcu_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a0000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa0000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core0_memory_region: vision-apps-r5f-memory@a0100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa0100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a1000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_mcu_r5fss0_core1_memory_region: vision-apps-r5f-memory@a1100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa1100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a2000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa2000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core0_memory_region: vision-apps-r5f-memory@a2100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa2100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a4000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa4000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss0_core1_memory_region: vision-apps-r5f-memory@a4100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa4100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core0_dma_memory_region: vision-apps-r5f-dma-memory@a6000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa6000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core0_memory_region: vision-apps-r5f-memory@a6100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa6100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core1_dma_memory_region: vision-apps-r5f-dma-memory@a7000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa7000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_main_r5fss1_core1_memory_region: vision-apps-r5f-memory@a7100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa7100000 0x00 0x00f00000>;
+		no-map;
+	};
+	vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a8000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xa8000000 0x00 0x02000000>;
+		no-map;
+	};
+	vision_apps_memory_region: vision-apps-dma-memory@aa000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xaa000000 0x00 0x06000000>;
+		no-map;
+	};
+	vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@b0000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb0000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@b0100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb0100000 0x00 0x05f00000>;
+		no-map;
+	};
+	vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b6000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb6000000 0x00 0x00100000>;
+		no-map;
+	};
+	vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b6100000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xb6100000 0x00 0x01f00000>;
+		no-map;
+	};
+	vision_apps_shared_region: vision_apps_shared-memories {
+		compatible = "dma-heap-carveout";
+		reg = <0x00 0xb8000000 0x00 0x20000000>;
+	};
+	vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@d8000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x00 0xd8000000 0x00 0x04000000>;
+		no-map;
+	};
+
+	/* This is for getting crash logs using Android downstream kernels */
+	ramoops@DD000000 {
+		compatible = "ramoops";
+		reg = <0x0 0xDD000000 0x0 0x40000>;
+		console-size = <0x10000>;
+		record-size = <0x10000>;
+		ftrace-size = <0x10000>;
+		pmsg-size = <0x20000>;
+	};
+
+	vision_apps_core_heaps_hi: vision-apps-core-heap-memory-hi@880000000 {
+		compatible = "shared-dma-pool";
+		reg = <0x08 0x80000000 0x00 0x2c000000>;
+		no-map;
+	};
+	linux_cma_region: linux-cma-buffers@8ac000000 {
+		compatible = "shared-dma-pool";
+		reusable;
+		reg = <0x08 0xac000000 0x00 0x38000000>;
+		linux,cma-default;
+	};
+};
+
+&mcu_r5fss0_core0 {
+	memory-region = <&vision_apps_mcu_r5fss0_core0_dma_memory_region>,
+			<&vision_apps_mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_mcu_r5fss0_core1_memory_region>;
+	status = "disabled";
+};
+
+&main_r5fss0_core0 {
+	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	memory-region = <&vision_apps_main_r5fss0_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
+			<&vision_apps_main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+	memory-region = <&vision_apps_c71_0_dma_memory_region>,
+			<&vision_apps_c71_0_memory_region>;
+};
+
+&c71_1 {
+	memory-region = <&vision_apps_c71_1_dma_memory_region>,
+			<&vision_apps_c71_1_memory_region>;
+};
+

rtos sdk patch：

commit 9a583f65e73d6d60f462717747ac8d429b7c9b8e
Author: NM_liuli <liuli@nullmax.ai>
Date:   Wed Sep 27 12:02:22 2023 +0800

    [RTOS]Config SBL[2/2]

diff --git a/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/constructappimageshlos.sh b/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/constructappimageshlos.sh
index c666d0c04..fa329cdff 100755
--- a/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/constructappimageshlos.sh
+++ b/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/constructappimageshlos.sh
@@ -7,7 +7,7 @@
 MY_BOARD=$1
 
 # OS options are: linux or qnx
-OS=qnx
+OS=linux
 
 # Linux-specific paths
 # --------------------
@@ -17,7 +17,7 @@ OS=qnx
 # base-board.dtb (k3-j72*-common-proc-board.dtb), and Image files
 
 # Linux build directory containing all the locally-built Linux-related binaries
-LINUX_BUILD_DIR_PATH=USER_DEFINED_PATH
+LINUX_BUILD_DIR_PATH=${PWD}/../../../../../../../linux-sdk/board-support/prebuilt-images
 
 # QNX-specific paths
 # ------------------
@@ -40,7 +40,9 @@ PDK_INSTALL_PATH="${SDK_INSTALL_PATH}/pdk_j721s2/packages"
 SBL_REPO_PATH="${PDK_INSTALL_PATH}/ti/boot/sbl"
 MULTICORE_APPIMAGE_GEN_TOOL_PATH="${SBL_REPO_PATH}/tools/multicoreImageGen/bin"
 SBL_OUT2RPRC_GEN_TOOL_PATH="${SBL_REPO_PATH}/tools/out2rprc/bin"
-MULTICOREAPP_BIN_PATH=${PWD}/../../binary/bin/${MY_BOARD}
+MULTICOREAPP_BIN_PATH="${SDK_INSTALL_PATH}/vision_apps/out/sbl_bootfiles/rprcs"
+
+LINUX_GCC_TOOL_PATH="${SDK_INSTALL_PATH}/../linux-sdk/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/"
 
 LDS_PATH=${PWD}/${OS}
 
@@ -73,7 +75,8 @@ for i in "${GenFiles[@]}"
 do
     echo "Generating $i image"
     if [ $OS == "linux" ]; then
-        aarch64-none-linux-gnu-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
+       # aarch64-none-linux-gnu-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
+	${LINUX_GCC_TOOL_PATH}/aarch64-none-linux-gnu-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
     fi
     if [ $OS == "qnx" ]; then
         ${TOOLCHAIN_PATH_GCC_ARCH64}/aarch64-unknown-nto-qnx7.0.0-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
diff --git a/pdk_j721s2/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c b/pdk_j721s2/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
index a0b416e75..183e251f7 100644
--- a/pdk_j721s2/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
+++ b/pdk_j721s2/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
@@ -939,7 +939,7 @@ static pinmuxPerCfg_t gUart6PinCfg[] =
     },
     {PINMUX_END}
 };
-
+#if 0
 static pinmuxPerCfg_t gUart9PinCfg[] =
 {
     /* MyUART9 -> UART9_RXD -> V27 */
@@ -954,15 +954,41 @@ static pinmuxPerCfg_t gUart9PinCfg[] =
     },
     {PINMUX_END}
 };
+#endif
+static pinmuxPerCfg_t gUart0PinCfg[] =
+{
+    /* MyUART9 -> UART9_RXD -> V27 */
+    {
+        PIN_MCASP1_AXR1, PIN_MODE(11) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyUART9 -> UART9_TXD -> W27 */
+    {
+        PIN_MCASP1_AXR2, PIN_MODE(11) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* V28 */
+    {
+        PIN_MCASP1_AFSX, PIN_MODE(11) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* T28 */
+    {
+        PIN_MCASP1_AXR0, PIN_MODE(11) | \
+         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
 
 static pinmuxModuleCfg_t gUartPinCfg[] =
 {
+    {0, TRUE, gUart0PinCfg},
     {8, TRUE, gUart8PinCfg},
     {2, TRUE, gUart2PinCfg},
     {5, TRUE, gUart5PinCfg},
     {3, TRUE, gUart3PinCfg},
     {6, TRUE, gUart6PinCfg},
-    {9, TRUE, gUart9PinCfg},
+   // {9, TRUE, gUart9PinCfg},
     {PINMUX_END}
 };
 
@@ -1068,6 +1094,7 @@ static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
         PIN_MCU_SPI0_CS0, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
+#if 0 //remove for sbl
     /* MyWKUP_GPIO0 -> WKUP_GPIO0_66 -> G25 */
     {
         PIN_WKUP_GPIO0_66, PIN_MODE(7) | \
@@ -1083,6 +1110,7 @@ static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
         PIN_WKUP_GPIO0_11, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
+#endif
         /* MyMCU_OSPI1 -> WKUP_GPIO0_38 -> D20  MCU_OSPI1_CSn0 close*/
     {
         PIN_MCU_OSPI1_CSN0, PIN_MODE(7) | \
diff --git a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_cfg.h b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_cfg.h
index c5abae1d9..2c26f031d 100644
--- a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_cfg.h
+++ b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_cfg.h
@@ -61,7 +61,7 @@ extern "C" {
 #undef BOARD_DDR_ENABLE_DDR_MEM_PRIME
 
 /* UART LLD instance number for primary UART port */
-#define BOARD_UART_INSTANCE                             (8U)
+#define BOARD_UART_INSTANCE                             (0U)
 /* UART LLD instance number for MAIN UART1 port */
 #define BOARD_UART1_INSTANCE                            (1U)
 /* UART LLD instance number for MAIN UART2 port */
diff --git a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddr.h b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddr.h
index 60213e0eb..b75c22e10 100644
--- a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddr.h
+++ b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddr.h
@@ -86,7 +86,7 @@ extern "C" {
 
 #define BOARD_DDR_INSTANCE_0                    (0U)
 #define BOARD_DDR_INSTANCE_1                    (1U)
-#define BOARD_DDR_INSTANCE_MAX                  (2U)
+#define BOARD_DDR_INSTANCE_MAX                  (1U)
 
 #define BOARD_DDR_LOCK0                         (0x115008U)
 #define BOARD_DDR_LOCK1                         (0x11500CU)
diff --git a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
index feec6d630..b04e7e45d 100644
--- a/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
+++ b/pdk_j721s2/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2021, Texas Instruments Incorporated
+/* Copyright (c) 2019, Texas Instruments Incorporated
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -28,24 +28,24 @@
  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
 
 /*
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0
- * This file was generated on 10/25/2021
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
+ * This file was generated on 05/30/2023
 */
 
 #define DDRSS_PLL_FHS_CNT 10
 #define DDRSS_PLL_FREQUENCY_0 27500000
-#define DDRSS_PLL_FREQUENCY_1 1066500000
-#define DDRSS_PLL_FREQUENCY_2 1066500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
 
 #define DDRSS_CTL_REG_INIT_COUNT (459U)
 #define DDRSS_PHY_INDEP_REG_INIT_COUNT (300U)
 #define DDRSS_PHY_REG_INIT_COUNT (1423U)
 
 #define MULTI_DDR_CFG_INTRLV_GRAN 0
-#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_INTRLV_SIZE 7
 #define MULTI_DDR_CFG_ECC_ENABLE 0
 #define MULTI_DDR_CFG_HYBRID_SELECT 0
-#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 1
 
 uint32_t DDRSS0_ctlReg[] = {
     0x00000B00U,
@@ -59,14 +59,14 @@ uint32_t DDRSS0_ctlReg[] = {
     0x0001ADAFU,
     0x00000005U,
     0x0000006EU,
-    0x000681C8U,
-    0x004111C9U,
+    0x0004E200U,
+    0x0030D400U,
     0x00000005U,
-    0x000010A9U,
-    0x000681C8U,
-    0x004111C9U,
+    0x00000C80U,
+    0x0004E200U,
+    0x0030D400U,
     0x00000005U,
-    0x000010A9U,
+    0x00000C80U,
     0x01010000U,
     0x02011001U,
     0x02010000U,
@@ -76,7 +76,7 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x03020200U,
-    0x00005656U,
+    0x00004040U,
     0x00100000U,
     0x00000000U,
     0x00000000U,
@@ -86,56 +86,56 @@ uint32_t DDRSS0_ctlReg[] = {
     0x12481248U,
     0x00050804U,
     0x09040008U,
-    0x15000204U,
-    0x1760008BU,
-    0x1500422BU,
-    0x1760008BU,
-    0x2000422BU,
+    0x10000204U,
+    0x15480068U,
+    0x10003120U,
+    0x15480068U,
+    0x20003120U,
     0x000A0A09U,
     0x0400078AU,
-    0x1E161104U,
-    0x10012458U,
-    0x1E161110U,
-    0x10012458U,
-    0x02030410U,
-    0x2C040500U,
-    0x08292C29U,
+    0x17100D04U,
+    0x0C00DB60U,
+    0x17100D0CU,
+    0x0C00DB60U,
+    0x0203040CU,
+    0x21040500U,
+    0x08222122U,
     0x14000E0AU,
-    0x04010A0AU,
-    0x01010004U,
-    0x04545408U,
-    0x04313104U,
-    0x00003131U,
+    0x03010A0AU,
+    0x01010003U,
+    0x04424208U,
+    0x04252504U,
+    0x00002525U,
     0x00010100U,
     0x03010000U,
-    0x00001508U,
+    0x00001008U,
     0x000000CEU,
-    0x0000032BU,
-    0x00002073U,
-    0x0000032BU,
-    0x00002073U,
+    0x000001C0U,
+    0x00001858U,
+    0x000001C0U,
+    0x00001858U,
     0x00000005U,
-    0x00050000U,
-    0x00CB0012U,
-    0x00CB0408U,
-    0x00400408U,
+    0x00040000U,
+    0x00700012U,
+    0x00700304U,
+    0x00400304U,
     0x00120103U,
-    0x00100005U,
-    0x2F080010U,
-    0x0505012FU,
-    0x0401030AU,
-    0x041E100BU,
-    0x100B0401U,
-    0x0001041EU,
-    0x00160016U,
-    0x033B033BU,
-    0x033B033BU,
+    0x000C0005U,
+    0x2408000CU,
+    0x05050124U,
+    0x0301030AU,
+    0x03170C08U,
+    0x0C080301U,
+    0x00010317U,
+    0x00100010U,
+    0x01CC01CCU,
+    0x01CC01CCU,
     0x03050505U,
     0x03010303U,
-    0x200B100BU,
-    0x04041004U,
-    0x200B100BU,
-    0x04041004U,
+    0x18080C08U,
+    0x03030C03U,
+    0x18080C08U,
+    0x03030C03U,
     0x03010000U,
     0x00010000U,
     0x00000000U,
@@ -157,20 +157,20 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00003380U,
     0x00000000U,
     0x000005A2U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
     0x00000000U,
-    0x0000E325U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
+    0x0000AA68U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
     0x00000000U,
-    0x0000E325U,
+    0x0000AA68U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -179,8 +179,8 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x0B030500U,
-    0x00040B04U,
+    0x08030500U,
+    0x00030803U,
     0x0A090000U,
     0x0A090701U,
     0x0900000EU,
@@ -215,11 +215,11 @@ uint32_t DDRSS0_ctlReg[] = {
     0x000B0000U,
     0x000E0006U,
     0x000E0404U,
-    0x00D601ABU,
-    0x10100216U,
-    0x01AB0216U,
-    0x021600D6U,
-    0x02161010U,
+    0x00A00140U,
+    0x0C0C0190U,
+    0x01400190U,
+    0x019000A0U,
+    0x01900C0CU,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -277,17 +277,17 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00000000U,
     0x15110000U,
     0x00040C18U,
+    0xF000C000U,
+    0x0000F000U,
     0x00000000U,
     0x00000000U,
+    0xC0000000U,
+    0xF000F000U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
+    0xF000C000U,
+    0x0000F000U,
     0x00000000U,
     0x00000000U,
     0x00030000U,
@@ -309,19 +309,19 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00370040U,
     0x00020008U,
     0x00400100U,
-    0x00400855U,
+    0x00300640U,
     0x01000200U,
-    0x08550040U,
-    0x00000040U,
-    0x006B0003U,
-    0x0100006BU,
-    0x00000000U,
-    0x00000000U,
+    0x06400040U,
+    0x00000030U,
+    0x00500003U,
+    0x01000050U,
+    0x03030303U,
+    0x01010000U,
     0x00000202U,
-    0x00001FFFU,
-    0x3FFF2000U,
-    0x03FF0000U,
-    0x000103FFU,
+    0x00000FFFU,
+    0x1FFF1000U,
+    0x01FF0000U,
+    0x000101FFU,
     0x0FFF0B00U,
     0x01010001U,
     0x01010101U,
@@ -366,15 +366,15 @@ uint32_t DDRSS0_ctlReg[] = {
     0x01000101U,
     0x01010001U,
     0x00010101U,
-    0x050A0A03U,
-    0x10081F1FU,
-    0x00090310U,
-    0x0B0C030FU,
-    0x0B0C0306U,
-    0x0C090006U,
-    0x0100000CU,
-    0x08040801U,
-    0x00000004U,
+    0x050C0C03U,
+    0x0C082020U,
+    0x0009030CU,
+    0x090D030FU,
+    0x090D0306U,
+    0x0D090006U,
+    0x0100000DU,
+    0x06030601U,
+    0x00000003U,
     0x00000000U,
     0x00010000U,
     0x00280D00U,
@@ -435,7 +435,7 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x3A3A1B00U,
+    0x33331B00U,
     0x000A0000U,
     0x0000019CU,
     0x00000200U,
@@ -445,22 +445,22 @@ uint32_t DDRSS0_ctlReg[] = {
     0x000004D4U,
     0x00001018U,
     0x00000204U,
-    0x000040E6U,
+    0x000030B0U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
-    0x0000C2B2U,
-    0x000288FCU,
-    0x00000E15U,
-    0x000040E6U,
+    0x00009210U,
+    0x0001E6E0U,
+    0x00000E18U,
+    0x000030B0U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
-    0x0000C2B2U,
-    0x000288FCU,
-    0x02020E15U,
+    0x00009210U,
+    0x0001E6E0U,
+    0x02020E18U,
     0x03030202U,
     0x00000022U,
     0x00000000U,
@@ -471,8 +471,8 @@ uint32_t DDRSS0_ctlReg[] = {
     0x00000000U,
     0x00030000U,
     0x0007001FU,
-    0x001B0033U,
-    0x001B0033U,
+    0x0016002EU,
+    0x0016002EU,
     0x00000000U,
     0x00000000U,
     0x02000000U,
@@ -556,7 +556,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
     0x00000000U,
     0x00000000U,
     0x000F0F00U,
-    0x0000001BU,
+    0x00000019U,
     0x000007D0U,
     0x00000300U,
     0x00000000U,
@@ -583,7 +583,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
     0x00000000U,
     0x0000FFFFU,
     0x00000000U,
-    0x00080000U,
+    0x00080100U,
     0x02000200U,
     0x01000100U,
     0x01000000U,
@@ -673,18 +673,18 @@ uint32_t DDRSS0_phyIndepReg[] = {
     0x00000000U,
     0x00010000U,
     0x00000000U,
-    0x2B2B0200U,
+    0x20200200U,
     0x00000034U,
-    0x00000064U,
-    0x00020064U,
+    0x00000060U,
+    0x00020060U,
     0x02000200U,
     0x48120C04U,
-    0x00154812U,
+    0x00104812U,
     0x000000CEU,
-    0x0000032BU,
-    0x00002073U,
-    0x0000032BU,
-    0x04002073U,
+    0x000001C0U,
+    0x00001858U,
+    0x000001C0U,
+    0x04001858U,
     0x01010404U,
     0x00001501U,
     0x00150015U,
@@ -695,80 +695,80 @@ uint32_t DDRSS0_phyIndepReg[] = {
     0x00000101U,
     0x00000000U,
     0x00000000U,
-    0x15040000U,
-    0x0E0E0215U,
+    0x18040000U,
+    0x0E0E0218U,
     0x00040402U,
     0x000D0035U,
-    0x00218049U,
-    0x00218049U,
+    0x001C0044U,
+    0x001C0044U,
     0x01010101U,
-    0x0004000EU,
-    0x00040216U,
-    0x01000216U,
+    0x0003000EU,
+    0x00030190U,
+    0x01000190U,
     0x000F000FU,
-    0x02170100U,
-    0x01000217U,
-    0x02170217U,
+    0x01910100U,
+    0x01000191U,
+    0x01910191U,
     0x32103200U,
     0x01013210U,
     0x0A070601U,
-    0x1F130A0DU,
-    0x1F130A14U,
-    0x0000C014U,
+    0x180F090DU,
+    0x180F0911U,
+    0x0000C011U,
     0x00C01000U,
     0x00C01000U,
     0x00021000U,
-    0x0024000EU,
-    0x00240216U,
-    0x00110216U,
+    0x001E000EU,
+    0x001E0190U,
+    0x00110190U,
     0x32000056U,
     0x00000301U,
-    0x005B0036U,
+    0x005E0034U,
     0x03013212U,
-    0x00003600U,
-    0x3212005BU,
+    0x00003400U,
+    0x3212005EU,
     0x09000301U,
     0x04010504U,
     0x040006C9U,
     0x0A032001U,
-    0x2C31110AU,
-    0x00002918U,
-    0x6001071CU,
-    0x1E202008U,
-    0x2C311116U,
-    0x00002918U,
-    0x6001071CU,
-    0x1E202008U,
-    0x00019C16U,
+    0x21250D0AU,
+    0x00002216U,
+    0x4800C570U,
+    0x17182006U,
+    0x21250D10U,
+    0x00002216U,
+    0x4800C570U,
+    0x17182006U,
+    0x00019C10U,
     0x00001018U,
-    0x000040E6U,
-    0x000288FCU,
-    0x000040E6U,
-    0x000288FCU,
-    0x033B0016U,
-    0x0303033BU,
+    0x000030B0U,
+    0x0001E6E0U,
+    0x000030B0U,
+    0x0001E6E0U,
+    0x01CC0010U,
+    0x030301CCU,
     0x002AF803U,
     0x0001ADAFU,
     0x00000005U,
     0x0000006EU,
-    0x00000016U,
-    0x000681C8U,
+    0x00000010U,
+    0x0004E200U,
     0x0001ADAFU,
     0x00000005U,
-    0x000010A9U,
-    0x0000033BU,
-    0x000681C8U,
+    0x00000C80U,
+    0x000001CCU,
+    0x0004E200U,
     0x0001ADAFU,
     0x00000005U,
-    0x000010A9U,
-    0x0100033BU,
+    0x00000C80U,
+    0x010001CCU,
     0x00370040U,
     0x00010008U,
-    0x08550040U,
-    0x00010040U,
-    0x08550040U,
-    0x00000340U,
-    0x006B006BU,
+    0x06400040U,
+    0x00010030U,
+    0x06400040U,
+    0x00000330U,
+    0x00500050U,
     0x08040404U,
     0x00000055U,
     0x55083C5AU,
@@ -845,7 +845,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -912,13 +912,13 @@ uint32_t DDRSS0_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -926,7 +926,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -943,8 +943,8 @@ uint32_t DDRSS0_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -1101,7 +1101,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -1168,13 +1168,13 @@ uint32_t DDRSS0_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -1182,7 +1182,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -1199,8 +1199,8 @@ uint32_t DDRSS0_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -1357,7 +1357,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -1424,13 +1424,13 @@ uint32_t DDRSS0_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -1438,7 +1438,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -1455,8 +1455,8 @@ uint32_t DDRSS0_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -1613,7 +1613,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -1680,13 +1680,13 @@ uint32_t DDRSS0_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -1694,7 +1694,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -1711,8 +1711,8 @@ uint32_t DDRSS0_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -2123,7 +2123,7 @@ uint32_t DDRSS0_phyReg[] = {
     0x01200F02U,
     0x00194280U,
     0x00000004U,
-    0x00052000U,
+    0x00042000U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -2250,14 +2250,14 @@ uint32_t DDRSS1_ctlReg[] = {
     0x0001ADAFU,
     0x00000005U,
     0x0000006EU,
-    0x000681C8U,
-    0x004111C9U,
+    0x0004E200U,
+    0x0030D400U,
     0x00000005U,
-    0x000010A9U,
-    0x000681C8U,
-    0x004111C9U,
+    0x00000C80U,
+    0x0004E200U,
+    0x0030D400U,
     0x00000005U,
-    0x000010A9U,
+    0x00000C80U,
     0x01010000U,
     0x02011001U,
     0x02010000U,
@@ -2267,7 +2267,7 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x03020200U,
-    0x00005656U,
+    0x00004040U,
     0x00100000U,
     0x00000000U,
     0x00000000U,
@@ -2277,56 +2277,56 @@ uint32_t DDRSS1_ctlReg[] = {
     0x12481248U,
     0x00050804U,
     0x09040008U,
-    0x15000204U,
-    0x1760008BU,
-    0x1500422BU,
-    0x1760008BU,
-    0x2000422BU,
+    0x10000204U,
+    0x11480068U,
+    0x10003120U,
+    0x11480068U,
+    0x20003120U,
     0x000A0A09U,
     0x0400078AU,
-    0x1E161104U,
-    0x10012458U,
-    0x1E161110U,
-    0x10012458U,
-    0x02030410U,
-    0x2C040500U,
-    0x08292C29U,
+    0x17100D04U,
+    0x0C00DB60U,
+    0x17100D0CU,
+    0x0C00DB60U,
+    0x0203040CU,
+    0x21040500U,
+    0x081F211FU,
     0x14000E0AU,
-    0x04010A0AU,
-    0x01010004U,
-    0x04545408U,
-    0x04313104U,
-    0x00003131U,
+    0x03010A0AU,
+    0x01010003U,
+    0x043F3F08U,
+    0x04252504U,
+    0x00002525U,
     0x00010100U,
     0x03010000U,
     0x00001508U,
     0x000000CEU,
-    0x0000032BU,
-    0x00002073U,
-    0x0000032BU,
-    0x00002073U,
+    0x00000260U,
+    0x00001858U,
+    0x00000260U,
+    0x00001858U,
     0x00000005U,
     0x00050000U,
-    0x00CB0012U,
-    0x00CB0408U,
-    0x00400408U,
+    0x00980012U,
+    0x00980304U,
+    0x00400304U,
     0x00120103U,
-    0x00100005U,
-    0x2F080010U,
-    0x0505012FU,
-    0x0401030AU,
-    0x041E100BU,
-    0x100B0401U,
-    0x0001041EU,
+    0x000C0005U,
+    0x2408000CU,
+    0x05050124U,
+    0x0301030AU,
+    0x03170C08U,
+    0x0C080301U,
+    0x00010317U,
     0x00160016U,
-    0x033B033BU,
-    0x033B033BU,
+    0x026C026CU,
+    0x026C026CU,
     0x03050505U,
     0x03010303U,
-    0x200B100BU,
-    0x04041004U,
-    0x200B100BU,
-    0x04041004U,
+    0x18080C08U,
+    0x03030C03U,
+    0x18080C08U,
+    0x03030C03U,
     0x03010000U,
     0x00010000U,
     0x00000000U,
@@ -2348,20 +2348,20 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00003380U,
     0x00000000U,
     0x000005A2U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
     0x00000000U,
-    0x0000E325U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
-    0x00081CC0U,
+    0x0000AA68U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
+    0x00061600U,
     0x00000000U,
-    0x0000E325U,
+    0x0000AA68U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -2370,8 +2370,8 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x0B030500U,
-    0x00040B04U,
+    0x08030500U,
+    0x00030803U,
     0x0A090000U,
     0x0A090701U,
     0x0900000EU,
@@ -2406,11 +2406,11 @@ uint32_t DDRSS1_ctlReg[] = {
     0x000B0000U,
     0x000E0006U,
     0x000E0404U,
-    0x00D601ABU,
-    0x10100216U,
-    0x01AB0216U,
-    0x021600D6U,
-    0x02161010U,
+    0x00A00140U,
+    0x0C0C0190U,
+    0x01400190U,
+    0x019000A0U,
+    0x01900C0CU,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -2468,17 +2468,17 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00000000U,
     0x15110000U,
     0x00040C18U,
+    0xF000C000U,
+    0x0000F000U,
     0x00000000U,
     0x00000000U,
+    0xC0000000U,
+    0xF000F000U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
-    0x00000000U,
+    0xF000C000U,
+    0x0000F000U,
     0x00000000U,
     0x00000000U,
     0x00030000U,
@@ -2500,13 +2500,13 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00370040U,
     0x00020008U,
     0x00400100U,
-    0x00400855U,
+    0x00300640U,
     0x01000200U,
-    0x08550040U,
-    0x00000040U,
-    0x006B0003U,
-    0x0100006BU,
-    0x00000000U,
+    0x06400040U,
+    0x00000030U,
+    0x00500003U,
+    0x01000050U,
+    0x03030303U,
     0x00000000U,
     0x00000202U,
     0x00001FFFU,
@@ -2557,15 +2557,15 @@ uint32_t DDRSS1_ctlReg[] = {
     0x01000101U,
     0x01010001U,
     0x00010101U,
-    0x050A0A03U,
-    0x10081F1FU,
-    0x00090310U,
-    0x0B0C030FU,
-    0x0B0C0306U,
-    0x0C090006U,
-    0x0100000CU,
-    0x08040801U,
-    0x00000004U,
+    0x050C0C03U,
+    0x0C082020U,
+    0x0009030CU,
+    0x090D030FU,
+    0x090D0306U,
+    0x0D090006U,
+    0x0100000DU,
+    0x06030601U,
+    0x00000003U,
     0x00000000U,
     0x00010000U,
     0x00280D00U,
@@ -2626,7 +2626,7 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00000000U,
     0x00000000U,
     0x00000000U,
-    0x3A3A1B00U,
+    0x33331B00U,
     0x000A0000U,
     0x0000019CU,
     0x00000200U,
@@ -2636,22 +2636,22 @@ uint32_t DDRSS1_ctlReg[] = {
     0x000004D4U,
     0x00001018U,
     0x00000204U,
-    0x000040E6U,
+    0x000030B0U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
-    0x0000C2B2U,
-    0x000288FCU,
-    0x00000E15U,
-    0x000040E6U,
+    0x00009210U,
+    0x0001E6E0U,
+    0x00000E18U,
+    0x000030B0U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
     0x00000200U,
-    0x0000C2B2U,
-    0x000288FCU,
-    0x02020E15U,
+    0x00009210U,
+    0x0001E6E0U,
+    0x02020E18U,
     0x03030202U,
     0x00000022U,
     0x00000000U,
@@ -2662,8 +2662,8 @@ uint32_t DDRSS1_ctlReg[] = {
     0x00000000U,
     0x00030000U,
     0x0007001FU,
-    0x001B0033U,
-    0x001B0033U,
+    0x0016002EU,
+    0x0016002EU,
     0x00000000U,
     0x00000000U,
     0x02000000U,
@@ -2747,7 +2747,7 @@ uint32_t DDRSS1_phyIndepReg[] = {
     0x00000000U,
     0x00000000U,
     0x000F0F00U,
-    0x0000001BU,
+    0x00000019U,
     0x000007D0U,
     0x00000300U,
     0x00000000U,
@@ -2864,18 +2864,18 @@ uint32_t DDRSS1_phyIndepReg[] = {
     0x00000000U,
     0x00010000U,
     0x00000000U,
-    0x2B2B0200U,
+    0x20200200U,
     0x00000034U,
-    0x00000064U,
-    0x00020064U,
+    0x00000060U,
+    0x00020060U,
     0x02000200U,
     0x48120C04U,
     0x00154812U,
     0x000000CEU,
-    0x0000032BU,
-    0x00002073U,
-    0x0000032BU,
-    0x04002073U,
+    0x00000260U,
+    0x00001858U,
+    0x00000260U,
+    0x04001858U,
     0x01010404U,
     0x00001501U,
     0x00150015U,
@@ -2886,80 +2886,80 @@ uint32_t DDRSS1_phyIndepReg[] = {
     0x00000101U,
     0x00000000U,
     0x00000000U,
-    0x15040000U,
-    0x0E0E0215U,
+    0x18040000U,
+    0x0E0E0218U,
     0x00040402U,
     0x000D0035U,
-    0x00218049U,
-    0x00218049U,
+    0x001C0044U,
+    0x001C0044U,
     0x01010101U,
-    0x0004000EU,
-    0x00040216U,
-    0x01000216U,
+    0x0003000EU,
+    0x00030190U,
+    0x01000190U,
     0x000F000FU,
-    0x02170100U,
-    0x01000217U,
-    0x02170217U,
+    0x01910100U,
+    0x01000191U,
+    0x01910191U,
     0x32103200U,
     0x01013210U,
     0x0A070601U,
-    0x1F130A0DU,
-    0x1F130A14U,
-    0x0000C014U,
+    0x180F090DU,
+    0x180F0911U,
+    0x0000C011U,
     0x00C01000U,
     0x00C01000U,
     0x00021000U,
-    0x0024000EU,
-    0x00240216U,
-    0x00110216U,
+    0x001E000EU,
+    0x001E0190U,
+    0x00110190U,
     0x32000056U,
     0x00000301U,
-    0x005B0036U,
+    0x005E0030U,
     0x03013212U,
-    0x00003600U,
-    0x3212005BU,
+    0x00003000U,
+    0x3212005EU,
     0x09000301U,
     0x04010504U,
     0x040006C9U,
     0x0A032001U,
-    0x2C31110AU,
-    0x00002918U,
-    0x6001071CU,
-    0x1E202008U,
-    0x2C311116U,
-    0x00002918U,
-    0x6001071CU,
-    0x1E202008U,
-    0x00019C16U,
+    0x21250D0AU,
+    0x00001F12U,
+    0x4800C570U,
+    0x17182006U,
+    0x21250D10U,
+    0x00001F12U,
+    0x4800C570U,
+    0x17182006U,
+    0x00019C10U,
     0x00001018U,
-    0x000040E6U,
-    0x000288FCU,
-    0x000040E6U,
-    0x000288FCU,
-    0x033B0016U,
-    0x0303033BU,
+    0x000030B0U,
+    0x0001E6E0U,
+    0x000030B0U,
+    0x0001E6E0U,
+    0x026C0016U,
+    0x0303026CU,
     0x002AF803U,
     0x0001ADAFU,
     0x00000005U,
     0x0000006EU,
     0x00000016U,
-    0x000681C8U,
+    0x0004E200U,
     0x0001ADAFU,
     0x00000005U,
-    0x000010A9U,
-    0x0000033BU,
-    0x000681C8U,
+    0x00000C80U,
+    0x0000026CU,
+    0x0004E200U,
     0x0001ADAFU,
     0x00000005U,
-    0x000010A9U,
-    0x0100033BU,
+    0x00000C80U,
+    0x0100026CU,
     0x00370040U,
     0x00010008U,
-    0x08550040U,
-    0x00010040U,
-    0x08550040U,
-    0x00000340U,
-    0x006B006BU,
+    0x06400040U,
+    0x00010030U,
+    0x06400040U,
+    0x00000330U,
+    0x00500050U,
     0x08040404U,
     0x00000055U,
     0x55083C5AU,
@@ -3036,7 +3036,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -3103,13 +3103,13 @@ uint32_t DDRSS1_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -3117,7 +3117,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -3134,8 +3134,8 @@ uint32_t DDRSS1_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -3292,7 +3292,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -3359,13 +3359,13 @@ uint32_t DDRSS1_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -3373,7 +3373,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -3390,8 +3390,8 @@ uint32_t DDRSS1_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -3548,7 +3548,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -3615,13 +3615,13 @@ uint32_t DDRSS1_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -3629,7 +3629,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -3646,8 +3646,8 @@ uint32_t DDRSS1_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -3804,7 +3804,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00000808U,
     0x0F000000U,
     0x00000F0FU,
-    0x10200000U,
+    0x10400000U,
     0x0C002006U,
     0x00000000U,
     0x00000000U,
@@ -3871,13 +3871,13 @@ uint32_t DDRSS1_phyReg[] = {
     0x00100010U,
     0x00050010U,
     0x51517041U,
-    0x31C06001U,
+    0x31C06000U,
     0x07AB0340U,
     0x00C0C001U,
-    0x0E0D0001U,
+    0x0B0A0001U,
     0x10001000U,
-    0x0C083E42U,
-    0x0F0C3701U,
+    0x0C073E42U,
+    0x0F0C2D01U,
     0x01000140U,
     0x0C000420U,
     0x00000198U,
@@ -3885,7 +3885,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x00030200U,
     0x02800000U,
     0x80800000U,
-    0x000E2010U,
+    0x000B2010U,
     0x76543210U,
     0x00000008U,
     0x02800280U,
@@ -3902,8 +3902,8 @@ uint32_t DDRSS1_phyReg[] = {
     0x00A000A0U,
     0x00A000A0U,
     0x00A000A0U,
-    0x01C200A0U,
-    0x01A00005U,
+    0x011900A0U,
+    0x01A00004U,
     0x00000000U,
     0x00000000U,
     0x00080200U,
@@ -4314,7 +4314,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x01200F02U,
     0x00194280U,
     0x00000004U,
-    0x00052000U,
+    0x00042000U,
     0x00000000U,
     0x00000000U,
     0x00000000U,
@@ -4429,6 +4429,7 @@ uint32_t DDRSS1_phyReg[] = {
     0x20040006U,
 };
 
+
 uint16_t DDRSS_ctlRegNum[] = {
     0,
     1,
diff --git a/pdk_j721s2/packages/ti/boot/sbl/build/boot_app.mk b/pdk_j721s2/packages/ti/boot/sbl/build/boot_app.mk
index 6fb94f11a..74a327d9c 100644
--- a/pdk_j721s2/packages/ti/boot/sbl/build/boot_app.mk
+++ b/pdk_j721s2/packages/ti/boot/sbl/build/boot_app.mk
@@ -40,6 +40,8 @@ ifeq ($(BOOTMODE), ospi)
     SRCS_COMMON += boot_app_ospi.c
 else ifeq ($(BOOTMODE), mmcsd)
     SRCS_COMMON += boot_app_mmcsd.c
+else ifeq ($(BOOTMODE), emmc)
+    SRCS_COMMON += boot_app_mmcsd.c
 endif
 
 ifeq ($(BOOTMODE), mmcsd)
@@ -50,6 +52,14 @@ ifeq ($(BOOTMODE), mmcsd)
     endif
     CFLAGS_LOCAL_COMMON += -DBOOT_MMCSD
 endif
+ifeq ($(BOOTMODE), emmc)
+    ifeq ($(BUILD_HS), yes)
+        COMP_LIST_COMMON += mmcsd sbl_lib_mmcsd_hs fatfs_indp
+    else 
+        COMP_LIST_COMMON += mmcsd sbl_lib_mmcsd fatfs_indp
+    endif
+    CFLAGS_LOCAL_COMMON += -DBOOT_EMMC
+endif
 ifeq ($(BOOTMODE), ospi)
     ifeq ($(BUILD_HS), yes)
         COMP_LIST_COMMON += spi sbl_lib_cust_hs
diff --git a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
index 4c0c49950..faa160a94 100644
--- a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
+++ b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
@@ -76,7 +76,7 @@
 #include <ti/drv/sciclient/sciserver_tirtos.h>
 #endif
 
-#if defined(BOOT_MMCSD)
+#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
 #include "boot_app_mmcsd.h"
 #elif defined(BOOT_OSPI)
 #include "boot_app_ospi.h"
@@ -196,7 +196,7 @@ uint32_t Boot_App()
     /* Configuration of items needed by apps on some cores, before they boot */
     BootApp_AppSetup();
 
-#if defined(BOOT_MMCSD)
+#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
 
     retVal = BootApp_MMCBootImageInit();
     if (retVal != CSL_PASS)
@@ -222,7 +222,7 @@ uint32_t Boot_App()
         {
             UART_printf("Loading BootImage\n");
 
-            #if defined(BOOT_MMCSD)
+            #if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
                 retVal = BootApp_MMCSDBootStageImage(&gK3xx_evmEntry, mmcsd_main_domain_rtos_image_name[j]);
             #endif
 
@@ -269,7 +269,7 @@ uint32_t Boot_App()
         } /* if (retVal == CSL_PASS) */
     } /* for (j = 0; j < NUM_BOOT_STAGES; j++) */
 
-#if defined(BOOT_MMCSD)
+#if defined(BOOT_MMCSD) ||  defined(BOOT_EMMC) 
     BootApp_MMCBootImageDeInit();
 #endif
 
diff --git a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_mmcsd.c b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_mmcsd.c
index d6fca8337..cbd0fed3b 100644
--- a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_mmcsd.c
+++ b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/boot_app_mmcsd.c
@@ -69,20 +69,88 @@
 #include "boot_app_priv.h"
 #include "boot_app_mmcsd.h"
 
+#if defined(BOOT_EMMC)
+MMCSD_v2_HwAttrs MMCSDInitCfg_EMMC =
+{
+    1,
+    CSL_MMCSD0_CTL_CFG_BASE,
+    CSL_MMCSD0_SS_CFG_BASE , /* SS Registers */
+    CSL_MMCSD0_SS_CFG_BASE + 0x100,/* PHY  Registers */
+    CSLR_R5FSS0_CORE1_INTR_MMCSD0_EMMCSS_INTR_0, /* Corresponds to MAIN_R5_CORE1
+                                                    This will update dynamically either through
+                                                    dedicated interrupt line or query from BoardCfg*/
+    0,
+    200000000U,
+    25000000U,
+    MMCSD_CARD_EMMC,
+    MMCSD_BUS_WIDTH_8BIT,
+    (MMCSD_BUS_VOLTAGE_1_8V | MMCSD_BUS_VOLTAGE_3_3V),
+    1,
+    0,
+    NULL, /* ioDelay Fn */
+    NULL,
+    NULL, // MMCSD_inputClockControl,
+    0,  /* Enable DMA by default */
+    0, /* edmaChRx */
+    0, /* edmaChTx */
+    0U,
+    0U,
+    0U,
+    0U,
+    0U,
+    NULL,
+    0, /* Crossbar default for IPU1 */
+    0, /* Crossbar mux in */
+    0,  /* Cross bar instance number for IRQ66 used in eventNum */
+    MMCSD_SUPPORT_MMC_ALL, /* Supported modes */
+    MMCSD_configSocIntrPath,
+    MMCSD_HW_PHY,
+    MMCSD_AUTO_HW_TUNING
+};
+#endif
+
 int32_t BootApp_MMCBootImageInit()
 {
     int32_t retVal = E_PASS;
     MMCSD_v2_HwAttrs hwAttrsConfig;
 
+
     if (MMCSD_socGetInitCfg(FATFS_initCfg[0].drvInst,&hwAttrsConfig) != 0)
     {
         UART_printf("\nUnable to get config.Exiting. TEST FAILED.\r\n");
         retVal = E_FAIL;
     }
 
+
+#if defined(BOOT_EMMC)
+    hwAttrsConfig = MMCSDInitCfg_EMMC;
+#endif
+
     hwAttrsConfig.enableInterrupt = ((uint32_t)(0U));
     hwAttrsConfig.configSocIntrPath=NULL;
 
+#if defined(EMMC_DEBUG)
+    char str[400];
+    sprintf(str ,"\n Aodlee instNum=%d baseAddr=%d ssBaseAddr=%d phyBaseAddr=%d intNum=%d \r\n", \
+        hwAttrsConfig.instNum, hwAttrsConfig.baseAddr, hwAttrsConfig.baseAddr, hwAttrsConfig.ssBaseAddr, hwAttrsConfig.phyBaseAddr);
+    UART_printf(str);
+    sprintf(str, "\n Aodlee eventId=%d inputClk=%d outputClk=%d cardType=%d supportedBusWidth=%d \r\n", \
+        hwAttrsConfig.eventId, hwAttrsConfig.inputClk, hwAttrsConfig.outputClk, hwAttrsConfig.cardType, hwAttrsConfig.supportedBusWidth);
+    UART_printf(str);
+    sprintf(str, "\n Aodlee supportedBusVoltages=%d isHighSpeed=%d enableInterrupt=%d enableDma=%d rxDmaEventNumber=%d \r\n", \
+        hwAttrsConfig.supportedBusVoltages, hwAttrsConfig.isHighSpeed, hwAttrsConfig.enableInterrupt, hwAttrsConfig.enableDma, hwAttrsConfig.rxDmaEventNumber);
+    UART_printf(str);
+    sprintf(str, "\n Aodlee txDmaEventNumber=%d edmaTxTCC=%d edmaRxTCC=%d edmaTxTC=%d edmaRxTC=%d \r\n", \
+        hwAttrsConfig.txDmaEventNumber, hwAttrsConfig.edmaTxTCC, hwAttrsConfig.edmaRxTCC, hwAttrsConfig.edmaTxTC, hwAttrsConfig.edmaRxTC);
+    UART_printf(str);
+    sprintf(str, "\n Aodlee version=%d muxNum=%d muxInEvent=%d muxOutEvent=%d supportedModes=%d \r\n", \
+        hwAttrsConfig.version, hwAttrsConfig.muxNum, hwAttrsConfig.muxInEvent, hwAttrsConfig.muxOutEvent, hwAttrsConfig.supportedModes);
+    UART_printf(str);
+    sprintf(str, "\n Aodlee phyType=%d tuningType=%d \r\n", \
+        hwAttrsConfig.phyType, hwAttrsConfig.tuningType);
+    UART_printf(str);
+#endif
+
     if (MMCSD_socSetInitCfg(FATFS_initCfg[0].drvInst,&hwAttrsConfig) != 0)
     {
         UART_printf("\nUnable to set config.Exiting. TEST FAILED.\r\n");
diff --git a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/soc/j721s2/boot_core_defs.c b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/soc/j721s2/boot_core_defs.c
index 9d5127a20..64dff54b4 100644
--- a/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/soc/j721s2/boot_core_defs.c
+++ b/pdk_j721s2/packages/ti/boot/sbl/example/boot_app/soc/j721s2/boot_core_defs.c
@@ -248,7 +248,7 @@ const uint32_t ospi_main_domain_flash_rtos_images[NUM_BOOT_STAGES] = {
 #endif
 };
 #endif
-#if defined(BOOT_MMCSD)
+#if defined(BOOT_MMCSD) || defined(BOOT_EMMC)
 TCHAR mmcsd_main_domain_rtos_image_name[NUM_BOOT_STAGES][MAX_APPIMAGE_NAME_LEN] = {
     "0:/lateapp1",
     /* Load remaining cores before MPU/HLOS to avoid contention for control of SD card */
diff --git a/pdk_j721s2/packages/ti/boot/sbl/sbl_component.mk b/pdk_j721s2/packages/ti/boot/sbl/sbl_component.mk
index beaea05e8..efb006742 100644
--- a/pdk_j721s2/packages/ti/boot/sbl/sbl_component.mk
+++ b/pdk_j721s2/packages/ti/boot/sbl/sbl_component.mk
@@ -1219,7 +1219,7 @@ export sbl_boot_multicore_xip_entry_SBL_APPIMAGEGEN
 # SBL log level
 # no logs = 0, only errors =1, normal logs = 2, all logs = 3
 
-SBL_CFLAGS += -DSBL_LOG_LEVEL=2
+SBL_CFLAGS += -DSBL_LOG_LEVEL=3
 
 SBL_CFLAGS += -DSBL_ENABLE_PLL
 SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
@@ -1318,8 +1318,8 @@ endif
 CUST_SBL_TEST_SOCS = j721e j7200 j721s2 j784s4
 CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm
 ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 j784s4))
-CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
-CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
+CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
+CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
 # NOTE: To measure Early CAN response uncomment below line and comment above line
 #CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_SKIP_PINMUX_ENABLE -DSBL_USE_MCU_DOMAIN_ONLY"
 endif
@@ -1687,6 +1687,32 @@ sbl_EXAMPLE_LIST += boot_app_mmcsd
 boot_app_mmcsd_SBL_APPIMAGEGEN = yes
 export boot_app_mmcsd_SBL_APPIMAGEGEN
 
+# Boot App EMMC
+boot_app_emmc_COMP_LIST = boot_app_emmc
+boot_app_emmc_RELPATH = ti/boot/sbl/example/boot_app
+boot_app_emmc_CUSTOM_BINPATH = $(PDK_SBL_COMP_PATH)/example/boot_app/binary/$(BOARD)/emmc
+boot_app_emmc_PATH = $(PDK_SBL_COMP_PATH)/example/boot_app
+boot_app_emmc_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/boot_app.mk BOOTMODE=emmc BUILD_HS=no HLOSBOOT=none
+export boot_app_emmc_MAKEFILE
+boot_app_emmc_BOARD_DEPENDENCY = yes
+boot_app_emmc_SOC_DEPENDENCY = yes
+boot_app_emmc_CORE_DEPENDENCY = yes
+export boot_app_emmc_COMP_LIST
+export boot_app_emmc_BOARD_DEPENDENCY
+export boot_app_emmc_SOC_DEPENDENCY
+export boot_app_emmc_CORE_DEPENDENCY
+boot_app_emmc_PKG_LIST = boot_app_emmc
+boot_app_emmc_INCLUDE = $(boot_app_emmc_PATH)
+boot_app_emmc_SOCLIST = $(sbl_SOCLIST)
+boot_app_emmc_BOARDLIST = $(sbl_BOARDLIST)
+export boot_app_emmc_SOCLIST
+export boot_app_emmc_BOARDLIST
+boot_app_emmc_$(SOC)_CORELIST = mcu1_0
+export boot_app_emmc_$(SOC)_CORELIST
+sbl_EXAMPLE_LIST += boot_app_emmc
+boot_app_emmc_SBL_APPIMAGEGEN = yes
+export boot_app_emmc_SBL_APPIMAGEGEN
+
 # Boot App MMCSD to boot qnx
 boot_app_mmcsd_qnx_COMP_LIST = boot_app_mmcsd_qnx
 boot_app_mmcsd_qnx_RELPATH = ti/boot/sbl/example/boot_app
@@ -1739,6 +1765,32 @@ sbl_EXAMPLE_LIST += boot_app_mmcsd_linux
 boot_app_mmcsd_linux_SBL_APPIMAGEGEN = yes
 export boot_app_mmcsd_linux_SBL_APPIMAGEGEN
 
+# Boot App EMMC to boot linux
+boot_app_emmc_linux_COMP_LIST = boot_app_emmc_linux
+boot_app_emmc_linux_RELPATH = ti/boot/sbl/example/boot_app
+boot_app_emmc_linux_CUSTOM_BINPATH = $(PDK_SBL_COMP_PATH)/example/boot_app/binary/$(BOARD)/emmc
+boot_app_emmc_linux_PATH = $(PDK_SBL_COMP_PATH)/example/boot_app
+boot_app_emmc_linux_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/boot_app.mk BOOTMODE=emmc BUILD_HS=no HLOSBOOT=linux
+export boot_app_emmc_linux_MAKEFILE
+boot_app_emmc_linux_BOARD_DEPENDENCY = yes
+boot_app_emmc_linux_SOC_DEPENDENCY = yes
+boot_app_emmc_linux_CORE_DEPENDENCY = yes
+export boot_app_emmc_linux_COMP_LIST
+export boot_app_emmc_linux_BOARD_DEPENDENCY
+export boot_app_emmc_linux_SOC_DEPENDENCY
+export boot_app_emmc_linux_CORE_DEPENDENCY
+boot_app_emmc_linux_PKG_LIST = boot_app_emmc_linux
+boot_app_emmc_linux_INCLUDE = $(boot_app_emmc_linux_PATH)
+boot_app_emmc_linux_SOCLIST = $(sbl_SOCLIST)
+boot_app_emmc_linux_BOARDLIST = $(sbl_BOARDLIST)
+export boot_app_emmc_linux_SOCLIST
+export boot_app_emmc_linux_BOARDLIST
+boot_app_emmc_linux_$(SOC)_CORELIST = mcu1_0
+export boot_app_emmc_linux_$(SOC)_CORELIST
+sbl_EXAMPLE_LIST += boot_app_emmc_linux
+boot_app_emmc_linux_SBL_APPIMAGEGEN = yes
+export boot_app_emmc_linux_SBL_APPIMAGEGEN
+
 # Boot App OSPI HS
 boot_app_ospi_hs_COMP_LIST = boot_app_ospi_hs
 boot_app_ospi_hs_RELPATH = ti/boot/sbl/example/boot_app
diff --git a/pdk_j721s2/packages/ti/boot/sbl/src/emmc/sbl_emmc.c b/pdk_j721s2/packages/ti/boot/sbl/src/emmc/sbl_emmc.c
index 86467abcc..e80c88a1f 100755
--- a/pdk_j721s2/packages/ti/boot/sbl/src/emmc/sbl_emmc.c
+++ b/pdk_j721s2/packages/ti/boot/sbl/src/emmc/sbl_emmc.c
@@ -272,6 +272,7 @@ int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
 
     hwAttrsConfig.enableInterrupt = ((uint32_t)(0U));
     hwAttrsConfig.configSocIntrPath=NULL;
+    hwAttrsConfig.enableDma = 0;
 
 #ifdef EMMC_BOOT0
     hwAttrsConfig.enableDma = 1;
diff --git a/vision_apps/makerules/makefile_sbl.mak b/vision_apps/makerules/makefile_sbl.mak
index 17062efeb..33211bd43 100644
--- a/vision_apps/makerules/makefile_sbl.mak
+++ b/vision_apps/makerules/makefile_sbl.mak
@@ -30,7 +30,8 @@ OSPI_LOCATION_HLOS_KERNEL_IMAGE=7C0000
 OSPI_PATTERN=3FE0000
 OSPI_PATTERN_FILE=$(PDK_PATH)/packages/ti/board/src/flash/nor/ospi/nor_spi_patterns.bin
 
-SBL_BOOTFILES_PATH=$(VISION_APPS_PATH)/out/sbl_bootfiles
+SBL_BOOTFILES_MMCSD_PATH=$(VISION_APPS_PATH)/out/sbl_bootfiles_mmcsd
+SBL_BOOTFILES_EMMC_PATH=$(VISION_APPS_PATH)/out/sbl_bootfiles_emmc
 
 #UNIFLASH INFO
 UNIFLASH_VERSION=uniflash_6.0.0
@@ -47,7 +48,7 @@ endif
 #SBL INFO
 SBL_CORE=mcu1_0
 BOARD=$(BUILD_PDK_BOARD)
-ATF_OPTEE_PATH=$(SBL_BOOTFILES_PATH)/atf_optee_dir
+ATF_OPTEE_PATH=$(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir
 ATF_TARGET_BOARD=generic
 ifeq ($(SOC),j784s4)
 	ATF_TARGET_BOARD=j784s4
@@ -63,40 +64,40 @@ REMOTE_CORE_LIST_LATEAPP2=
 CERT_SCRIPT=$(PDK_PATH)/packages/ti/build/makerules/x509CertificateGen.sh
 
 ifeq ($(BUILD_CPU_MCU2_0),yes)
-	REMOTE_CORE_LIST_LATEAPP1+=10 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu2_0.out.rprc
+	REMOTE_CORE_LIST_LATEAPP1+=10 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu2_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU2_1),yes)
-	REMOTE_CORE_LIST_LATEAPP1+=11 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu2_1.out.rprc
+	REMOTE_CORE_LIST_LATEAPP1+=11 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu2_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU3_0),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=12 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu3_0.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=12 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu3_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU3_1),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=13 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu3_1.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=13 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu3_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU4_0),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=14 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu4_0.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=14 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu4_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU4_1),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=15 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu4_1.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=15 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu4_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C6x_1),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=16 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c6x_1.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=16 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c6x_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C6x_2),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=17 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c6x_2.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=17 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c6x_2.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_1),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=18 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_1.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=18 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_2),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=19 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_2.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=19 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_2.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_3),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=20 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_3.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=20 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_3.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_4),yes)
-	REMOTE_CORE_LIST_LATEAPP2+=21 $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_4.out.rprc
+	REMOTE_CORE_LIST_LATEAPP2+=21 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_4.out.rprc
 endif
 
 USE_OPTEE ?= 1
@@ -152,31 +153,37 @@ sbl_atf_optee_scrub:
 
 sbl_pdk_sd:
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build sbl_mmcsd_img DISABLE_RECURSE_DEPS=no BOARD=$(BOARD) CORE=$(SBL_CORE) -s
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)/mmcsd/bin/sbl_mmcsd_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_PATH)/tiboot3.bin
-	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs.bin $(SBL_BOOTFILES_PATH)/tifs.bin
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)/mmcsd/bin/sbl_mmcsd_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_MMCSD_PATH)/tiboot3.bin
+	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs.bin $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin
+
+sbl_pdk_emmc:
+	$(MAKE) -C $(PDK_PATH)/packages/ti/build sbl_emmc_uda_img DISABLE_RECURSE_DEPS=no BOARD=$(BOARD) CORE=$(SBL_CORE) -s
+	mkdir -p $(SBL_BOOTFILES_EMMC_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)/emmc_uda/bin/sbl_emmc_uda_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_EMMC_PATH)/tiboot3.bin
+	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs.bin $(SBL_BOOTFILES_EMMC_PATH)/tifs.bin
 
 sbl_pdk_sd_hs:
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build sbl_mmcsd_img_hs DISABLE_RECURSE_DEPS=no BOARD=$(BOARD) CORE=$(SBL_CORE) -s
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)_hs/mmcsd/bin/sbl_mmcsd_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_PATH)/tiboot3.bin.signed
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)_hs/mmcsd/bin/sbl_mmcsd_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_MMCSD_PATH)/tiboot3.bin.signed
 ifeq ($(HS_SR), 2_0)
-	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs_sr2-hs-enc.bin $(SBL_BOOTFILES_PATH)/tifs.bin.signed
+	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs_sr2-hs-enc.bin $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin.signed
 else ifeq ($(HS_SR), 1_1)
-	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs_sr1.1-hs-enc.bin $(SBL_BOOTFILES_PATH)/tifs.bin.signed
+	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs_sr1.1-hs-enc.bin $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin.signed
 else
-	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs-hs-enc.bin $(SBL_BOOTFILES_PATH)/tifs.bin.signed
+	cp $(PDK_PATH)/packages/ti/drv/sciclient/soc/$(SCICLIENT_VERSION)/tifs-hs-enc.bin $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin.signed
 endif
 
 sbl_pdk_ospi:
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build sbl_cust_img DISABLE_RECURSE_DEPS=no BOARD=$(BOARD) CORE=$(SBL_CORE) -s
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)/cust/bin/sbl_cust_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_PATH)/
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)/cust/bin/sbl_cust_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_MMCSD_PATH)/
 
 sbl_pdk_ospi_hs:
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build sbl_cust_img_hs DISABLE_RECURSE_DEPS=no BOARD=$(BOARD) CORE=$(SBL_CORE) -s
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)_hs/cust/bin/sbl_cust_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_PATH)/sbl_cust_img_$(SBL_CORE)_release.tiimage.signed
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/binary/$(BOARD)_hs/cust/bin/sbl_cust_img_$(SBL_CORE)_release.tiimage $(SBL_BOOTFILES_MMCSD_PATH)/sbl_cust_img_$(SBL_CORE)_release.tiimage.signed
 
 #################
 ## MCU BootApp
@@ -194,12 +201,12 @@ endif
 ifeq ($(BUILD_LINUX_A72), yes)
 	$(MAKE) -C $(MCUSW_PATH)/build can_boot_app_mcu_rtos -s HLOSBOOT=linux BOOTMODE=mmcsd BOARD=$(BOARD) CORE=$(SBL_CORE) BUILD_OS_TYPE=freertos CANFUNC=none
 endif
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(MCUSW_PATH)/binary/can_boot_app_mcu_rtos/bin/$(BOARD)/can_boot_app_mcu_rtos_$(SBL_CORE)_release.appimage $(SBL_BOOTFILES_PATH)/app
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(MCUSW_PATH)/binary/can_boot_app_mcu_rtos/bin/$(BOARD)/can_boot_app_mcu_rtos_$(SBL_CORE)_release.appimage $(SBL_BOOTFILES_MMCSD_PATH)/app
 
 sbl_mcusw_bootimage_sd_hs:
 	$(MAKE) sbl_mcusw_bootimage_sd
-	$(CERT_SCRIPT)  -b $(SBL_BOOTFILES_PATH)/app -o $(SBL_BOOTFILES_PATH)/app.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT)  -b $(SBL_BOOTFILES_MMCSD_PATH)/app -o $(SBL_BOOTFILES_MMCSD_PATH)/app.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
 
 sbl_mcusw_bootimage_ospi:
 	$(MAKE) sbl_mcusw_bootimage_touch
@@ -209,102 +216,129 @@ endif
 ifeq ($(BUILD_LINUX_A72), yes)
 	$(MAKE) -C $(MCUSW_PATH)/build can_boot_app_mcu_rtos -s HLOSBOOT=linux BOOTMODE=ospi BOARD=$(BOARD) CORE=$(SBL_CORE) BUILD_OS_TYPE=freertos CANFUNC=none
 endif
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(MCUSW_PATH)/binary/can_boot_app_mcu_rtos/bin/$(BOARD)/can_boot_app_mcu_rtos_$(SBL_CORE)_release.appimage $(SBL_BOOTFILES_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(MCUSW_PATH)/binary/can_boot_app_mcu_rtos/bin/$(BOARD)/can_boot_app_mcu_rtos_$(SBL_CORE)_release.appimage $(SBL_BOOTFILES_MMCSD_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage
 
 sbl_mcusw_bootimage_ospi_hs:
 	$(MAKE) sbl_mcusw_bootimage_ospi
-	$(CERT_SCRIPT)  -b $(SBL_BOOTFILES_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage -o $(SBL_BOOTFILES_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT)  -b $(SBL_BOOTFILES_MMCSD_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage -o $(SBL_BOOTFILES_MMCSD_PATH)/can_boot_app_mcu_rtos_$(SBL_CORE)_release_ospi.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
 
 
 #################
 ## PDK BootApp
 #################
 pdk_bootapp_sd:
-	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_mmcsd_qnx DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)/mmcsd/sbl_boot_app_mmcsd_qnx_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage $(SBL_BOOTFILES_PATH)/app
+	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_mmcsd_linux DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)/mmcsd/sbl_boot_app_mmcsd_linux_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage $(SBL_BOOTFILES_MMCSD_PATH)/app
+
+pdk_bootapp_emmc:
+	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_emmc_linux DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
+	mkdir -p $(SBL_BOOTFILES_EMMC_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)/emmc/sbl_boot_app_emmc_linux_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage $(SBL_BOOTFILES_EMMC_PATH)/app
 
 pdk_bootapp_sd_hs: pdk_bootapp_sd
-	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_mmcsd_qnx_hs DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)_hs/mmcsd/sbl_boot_app_mmcsd_qnx_hs_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage.signed $(SBL_BOOTFILES_PATH)/app.signed
+	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_mmcsd_linux_hs DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)_hs/mmcsd/sbl_boot_app_mmcsd_linux_hs_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage.signed $(SBL_BOOTFILES_MMCSD_PATH)/app.signed
 
 pdk_bootapp_ospi: pdk_bootapp_sd
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_ospi_qnx DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
-	mkdir -p $(SBL_BOOTFILES_PATH)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)/ospi/sbl_boot_app_ospi_qnx_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage $(SBL_BOOTFILES_PATH)/app_ospi
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)
+	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)/ospi/sbl_boot_app_ospi_qnx_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage $(SBL_BOOTFILES_MMCSD_PATH)/app_ospi
 
 pdk_bootapp_ospi_hs: pdk_bootapp_ospi
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build boot_app_ospi_qnx_hs DISABLE_RECURSE_DEPS=no -s BOARD=$(BOARD) CORE=$(SBL_CORE)
-	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)_hs/ospi/sbl_boot_app_ospi_qnx_hs_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage.signed $(SBL_BOOTFILES_PATH)/app_ospi.signed
+	cp $(PDK_PATH)/packages/ti/boot/sbl/example/boot_app/binary/$(BOARD)_hs/ospi/sbl_boot_app_ospi_qnx_hs_$(BOARD)_$(SBL_CORE)_freertos_TestApp_release.appimage.signed $(SBL_BOOTFILES_MMCSD_PATH)/app_ospi.signed
 
 
 sbl_vision_apps_bootimage_1:
-	mkdir -p $(SBL_BOOTFILES_PATH)/rprcs
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/rprcs
 ifeq ($(BUILD_CPU_MCU2_0),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_0.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_0.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu2_0.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu2_0.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu2_0.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu2_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU2_1),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_1.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_1.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu2_1.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu2_1.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu2_1.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu2_1.out.rprc
 endif
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/lateapp1 $(REMOTE_CORE_LIST_LATEAPP1)
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1 $(REMOTE_CORE_LIST_LATEAPP1)
 
 sbl_vision_apps_bootimage_hs_1:
 	$(MAKE) sbl_vision_apps_bootimage_1
-	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_PATH)/lateapp1 -o $(SBL_BOOTFILES_PATH)/lateapp1.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1 -o $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
 
 sbl_vision_apps_bootimage_2:
-	mkdir -p $(SBL_BOOTFILES_PATH)/rprcs
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/rprcs
 ifeq ($(BUILD_CPU_MCU3_0),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_0.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_0.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu3_0.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu3_0.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu3_0.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu3_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU3_1),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_1.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_1.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu3_1.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu3_1.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu3_1.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu3_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU4_0),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_0.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_0.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu4_0.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu4_0.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu4_0.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu4_0.out.rprc
 endif
 ifeq ($(BUILD_CPU_MCU4_1),yes)
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_1.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_1.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_mcu4_1.out.rprc
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu4_1.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_mcu4_1.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_mcu4_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C6x_1),yes)
-	$(CGT6X_ROOT)/bin/strip6x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_1.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_1.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c6x_1.out.rprc
+	$(CGT6X_ROOT)/bin/strip6x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c6x_1.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c6x_1.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c6x_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C6x_2),yes)
-	$(CGT6X_ROOT)/bin/strip6x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_2.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_2.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c6x_2.out.rprc
+	$(CGT6X_ROOT)/bin/strip6x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c6x_2.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c6x_2.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c6x_2.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_1),yes)
-	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_1.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_1.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_1.out.rprc
+	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_1.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_1.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_1.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_2),yes)
-	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_2.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_2.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_2.out.rprc
+	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_2.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_2.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_2.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_3),yes)
-	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_3.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_3.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_3.out.rprc
+	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_3.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_3.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_3.out.rprc
 endif
 ifeq ($(BUILD_CPU_C7x_4),yes)
-	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_4.out
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_4.out $(SBL_BOOTFILES_PATH)/rprcs/vx_app_rtos_qnx_c7x_4.out.rprc
+	$(CGT7X_ROOT)/bin/strip7x -p $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_4.out
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_linux_c7x_4.out $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/vx_app_rtos_linux_c7x_4.out.rprc
 endif
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/lateapp2 $(REMOTE_CORE_LIST_LATEAPP2)
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2 $(REMOTE_CORE_LIST_LATEAPP2)
 
 sbl_vision_apps_bootimage_hs_2:
 	$(MAKE) sbl_vision_apps_bootimage_2
-	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_PATH)/lateapp2 -o $(SBL_BOOTFILES_PATH)/lateapp2.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2 -o $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
 
 sbl_vision_apps_bootimage: sbl_vision_apps_bootimage_1 sbl_vision_apps_bootimage_2
 
+sbl_emmc_uda_copy:
+	mkdir -p $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1 $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/lateapp1
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2 $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/lateapp2
+	cp $(SBL_BOOTFILES_EMMC_PATH)/app $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+	cp $(SBL_BOOTFILES_EMMC_PATH)/atf_optee.appimage $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+	cp $(SBL_BOOTFILES_EMMC_PATH)/tiboot3.bin $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+	cp $(SBL_BOOTFILES_EMMC_PATH)/tidtb_linux.appimage $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+	cp $(SBL_BOOTFILES_EMMC_PATH)/tikernelimage_linux.appimage $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+	cp $(SBL_BOOTFILES_EMMC_PATH)/tifs.bin $(SBL_BOOTFILES_EMMC_PATH)/sbl_emmc_uda/
+
+sbl_mmcsd_copy:
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1 $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/lateapp1
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2 $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/lateapp2
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/app $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tiboot3.bin $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tidtb_linux.appimage $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tikernelimage_linux.appimage $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin $(SBL_BOOTFILES_MMCSD_PATH)/sbl_mmcsd/
+
 sbl_vision_apps_bootimage_hs:sbl_vision_apps_bootimage_hs_1 sbl_vision_apps_bootimage_hs_2
 
 sbl_qnx_bootimage:
@@ -312,40 +346,41 @@ ifeq ($(BUILD_QNX_A72), yes)
 ifeq ("$(wildcard $(QNX_BOOT_PATH)/qnx-ifs)","")
 	$(error qnx-ifs is still not built!)
 endif
-	mkdir -p $(SBL_BOOTFILES_PATH)/rprcs
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/rprcs
 	curr_dir=$(PWD)
 ifeq ($(USE_OPTEE),$(filter $(USE_OPTEE), 1))
 	cd $(ATF_OPTEE_PATH) && \
-	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/atf_optee.lds -o $(SBL_BOOTFILES_PATH)/rprcs/atf_optee.elf && \
+	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/atf_optee.lds -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.elf && \
 	cd $(QNX_BOOT_PATH) && \
-	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/ifs_qnx.lds -o $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.elf && \
+	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/ifs_qnx.lds -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.elf && \
 	cd $(curr_dir)
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_PATH)/rprcs/atf_optee.elf $(SBL_BOOTFILES_PATH)/rprcs/atf_optee.rprc
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.elf $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.rprc
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/atf_optee.appimage 0 $(SBL_BOOTFILES_PATH)/rprcs/atf_optee.rprc
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage 0 $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.elf $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.elf $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage 0 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage 0 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.rprc
 else
 	cd $(ATF_OPTEE_PATH) && \
-	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/atf_only.lds -o $(SBL_BOOTFILES_PATH)/rprcs/atf_only.elf && \
+	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/atf_only.lds -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_only.elf && \
 	cd $(QNX_BOOT_PATH) && \
-	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/ifs_qnx.lds -o $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.elf && \
+	$(QNX_BASE)/host/linux/x86_64/usr/bin/$(QNX_CROSS_COMPILER_TOOL)ld -T $(LDS_PATH)/ifs_qnx.lds -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.elf && \
 	cd $(curr_dir)
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_PATH)/rprcs/atf_only.elf $(SBL_BOOTFILES_PATH)/rprcs/atf_only.rprc
-	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.elf $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.rprc
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/atf_optee.appimage 0 $(SBL_BOOTFILES_PATH)/rprcs/atf_only.rprc
-	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage 0 $(SBL_BOOTFILES_PATH)/rprcs/ifs_qnx.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_only.elf $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_only.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.elf $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage 0 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_only.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage 0 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/ifs_qnx.rprc
 endif
 endif
 
 sbl_qnx_bootimage_hs:
 ifeq ($(BUILD_QNX_A72), yes)
 	$(MAKE) sbl_qnx_bootimage
-	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_PATH)/atf_optee.appimage -o $(SBL_BOOTFILES_PATH)/atf_optee.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
-	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage -o $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage -o $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+	$(CERT_SCRIPT) -b $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage -o $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
 endif
 
 ifeq ($(BOOTAPP),$(filter $(BOOTAPP), pdk))
 bootapp_sd: pdk_bootapp_sd
+bootapp_emmc: pdk_bootapp_emmc
 bootapp_sd_hs: pdk_bootapp_sd_hs
 bootapp_ospi: pdk_bootapp_ospi
 bootapp_ospi_hs: pdk_bootapp_ospi_hs
@@ -358,14 +393,54 @@ bootapp_ospi_hs: sbl_mcusw_bootimage_ospi_hs
 endif
 
 sbl_linux_bootimage:
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/bl31.bin       $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/bl32.bin       $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/k3-j721s2-common-proc-board.dtb $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir/k3-j721e-common-proc-board.dtb
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/Image          $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir
+	mkdir -p $(SBL_BOOTFILES_MMCSD_PATH)/rprcs
+	cd $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/atf_optee.lds          -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.elf
+	cd $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/tidtb_linux.lds         -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tidtb_linux.elf
+	cd $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/tikernelimage_linux.lds -o $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tikernelimage_linux.elf
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.elf           $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tidtb_linux.elf         $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tidtb_linux.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tikernelimage_linux.elf $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tikernelimage_linux.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage 0           $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/atf_optee.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/tidtb_linux.appimage 0         $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tidtb_linux.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_MMCSD_PATH)/tikernelimage_linux.appimage 0 $(SBL_BOOTFILES_MMCSD_PATH)/rprcs/tikernelimage_linux.rprc
+
+sbl_linux_bootimage_emmc:
+	mkdir -p $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/bl31.bin       $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/bl32.bin       $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/k3-j721s2-common-proc-board_sbl_emmc_uda.dtb $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir/k3-j721e-common-proc-board.dtb
+	cp $(PSDK_LINUX_PATH)/board-support/prebuilt-images/Image          $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir
+	mkdir -p $(SBL_BOOTFILES_EMMC_PATH)/rprcs
+	cd $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/atf_optee.lds          -o $(SBL_BOOTFILES_EMMC_PATH)/rprcs/atf_optee.elf
+	cd $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/tidtb_linux.lds         -o $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tidtb_linux.elf
+	cd $(SBL_BOOTFILES_EMMC_PATH)/atf_optee_dir && \
+	$(VISION_APPS_PATH)/../gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-ld -T $(LDS_PATH)/tikernelimage_linux.lds -o $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tikernelimage_linux.elf
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_EMMC_PATH)/rprcs/atf_optee.elf           $(SBL_BOOTFILES_EMMC_PATH)/rprcs/atf_optee.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tidtb_linux.elf         $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tidtb_linux.rprc
+	$(SBL_OUT2RPRC_GEN_TOOL_PATH)/out2rprc.exe $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tikernelimage_linux.elf $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tikernelimage_linux.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_EMMC_PATH)/atf_optee.appimage 0           $(SBL_BOOTFILES_EMMC_PATH)/rprcs/atf_optee.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_EMMC_PATH)/tidtb_linux.appimage 0         $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tidtb_linux.rprc
+	$(MULTICORE_APPIMAGE_GEN_TOOL_PATH)/MulticoreImageGen LE $(DEV_ID) $(SBL_BOOTFILES_EMMC_PATH)/tikernelimage_linux.appimage 0 $(SBL_BOOTFILES_EMMC_PATH)/rprcs/tikernelimage_linux.rprc
+
 
 sbl_bootimage_sd: sbl_pdk_sd bootapp_sd
+sbl_bootimage_emmc: sbl_pdk_emmc bootapp_emmc
 sbl_bootimage_ospi: sbl_pdk_ospi bootapp_ospi
 
 sbl_bootimage_sd_hs: sbl_pdk_sd_hs bootapp_sd_hs
 sbl_bootimage_ospi_hs: sbl_pdk_ospi_hs bootapp_ospi_hs
 
-sbl_bootimage: sbl_bootimage_sd sbl_bootimage_ospi sbl_atf_optee sbl_vision_apps_bootimage sbl_qnx_bootimage sbl_linux_bootimage
+sbl_bootimage: sbl_bootimage_sd sbl_bootimage_ospi sbl_bootimage_emmc sbl_atf_optee sbl_vision_apps_bootimage sbl_qnx_bootimage sbl_linux_bootimage sbl_linux_bootimage_emmc sbl_mmcsd_copy sbl_emmc_uda_copy
 
 sbl_bootimage_hs: sbl_bootimage_sd_hs sbl_bootimage_ospi_hs sbl_atf_optee sbl_vision_apps_bootimage_hs sbl_qnx_bootimage_hs
 
@@ -379,13 +454,13 @@ endif
 sbl_bootimage_flash_sbl_sysfw_bootapp:
 ifeq ($(UNIFLASH_FOUND), yes)
 	#SBL Image
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/sbl_cust_img_mcu1_0_release.tiimage -d 3 -o $(OSPI_LOCATION_SBL_IMAGE) || true
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/sbl_cust_img_mcu1_0_release.tiimage -d 3 -o $(OSPI_LOCATION_SBL_IMAGE) || true
 	#OSPI Patten file
 	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(OSPI_PATTERN_FILE) -d 3 -o $(OSPI_PATTERN) || true
 	#SYSFW BIN
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/tifs.bin -d 3 -o $(OSPI_LOCATION_SYSFW_BIN) || true
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin -d 3 -o $(OSPI_LOCATION_SYSFW_BIN) || true
 	#Boot App
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/can_boot_app_mcu_rtos_mcu1_0_release_ospi.appimage -d 3 -o $(OSPI_LOCATION_BOOT_APP) || true
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/can_boot_app_mcu_rtos_mcu1_0_release_ospi.appimage -d 3 -o $(OSPI_LOCATION_BOOT_APP) || true
 else
 	echo "Uniflash not found! Please install uniflash or update the uniflash path in makefile"
 endif
@@ -393,9 +468,9 @@ endif
 sbl_bootimage_flash_hlos:
 ifeq ($(UNIFLASH_FOUND), yes)
 	#ATF Image
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/atf_optee.appimage -d 3 -o $(OSPI_LOCATION_ATF_IMAGE) || true
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage -d 3 -o $(OSPI_LOCATION_ATF_IMAGE) || true
 	#HLOS Image
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage -d 3 -o $(OSPI_LOCATION_HLOS_KERNEL_IMAGE) || true
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage -d 3 -o $(OSPI_LOCATION_HLOS_KERNEL_IMAGE) || true
 else
 	echo "Uniflash not found! Please install uniflash or update the uniflash path in makefile"
 endif
@@ -403,37 +478,47 @@ endif
 sbl_bootimage_flash_rtosapp:
 ifeq ($(UNIFLASH_FOUND), yes)
 	#Multicore Image 1
-	cp -fv $(SBL_BOOTFILES_PATH)/lateapp1 $(SBL_BOOTFILES_PATH)/lateapp1.appimage
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/lateapp1.appimage -d 3 -o $(OSPI_LOCATION_MULTI_CORE_IMAGE_1) || true
-	rm -rf $(SBL_BOOTFILES_PATH)/lateapp1.appimage
+	cp -fv $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1 $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1.appimage
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1.appimage -d 3 -o $(OSPI_LOCATION_MULTI_CORE_IMAGE_1) || true
+	rm -rf $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1.appimage
 	#Multicore Image 2
-	cp -fv $(SBL_BOOTFILES_PATH)/lateapp2 $(SBL_BOOTFILES_PATH)/lateapp2.appimage
-	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_PATH)/lateapp2.appimage -d 3 -o $(OSPI_LOCATION_MULTI_CORE_IMAGE_2) || true
-	rm -rf $(SBL_BOOTFILES_PATH)/lateapp2.appimage
+	cp -fv $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2 $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2.appimage
+	$(UNIFLASH_SCRIPT) --mode processors -c $(UNIFLASH_COM_PORT) -f $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2.appimage -d 3 -o $(OSPI_LOCATION_MULTI_CORE_IMAGE_2) || true
+	rm -rf $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2.appimage
 else
 	echo "Uniflash not found! Please install uniflash or update the uniflash path in makefile"
 endif
 
-sbl_bootimage_install_sd: sbl_vision_apps_bootimage sbl_qnx_bootimage sbl_linux_bootimage
-	cp $(SBL_BOOTFILES_PATH)/tiboot3.bin $(SBL_SD_FS_PATH)
-	cp $(SBL_BOOTFILES_PATH)/tifs.bin $(SBL_SD_FS_PATH)
-	cp $(SBL_BOOTFILES_PATH)/app $(SBL_SD_FS_PATH)
-	cp $(SBL_BOOTFILES_PATH)/lateapp* $(SBL_SD_FS_PATH)
-ifeq ($(BUILD_QNX_A72), yes)
-	cp $(SBL_BOOTFILES_PATH)/atf_optee.appimage $(SBL_SD_FS_PATH)
-	cp $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage $(SBL_SD_FS_PATH)
+# sbl_bootimage_install_sd: sbl_vision_apps_bootimage sbl_qnx_bootimage sbl_linux_bootimage
+sbl_bootimage_install_sd: sbl_vision_apps_bootimage  sbl_linux_bootimage
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tiboot3.bin $(SBL_SD_FS_PATH)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin $(SBL_SD_FS_PATH)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/app $(SBL_SD_FS_PATH)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp* $(SBL_SD_FS_PATH)
+ifeq ($(BUILD_LINUX_A72), yes)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage           $(SBL_SD_FS_PATH)/atf_optee.appimage
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tidtb_linux.appimage         $(SBL_SD_FS_PATH)/tidtb_linux.appimage
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tikernelimage_linux.appimage $(SBL_SD_FS_PATH)/tikernelimage_linux.appimage
+else 
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage $(SBL_SD_FS_PATH)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage $(SBL_SD_FS_PATH)
 endif
 	sync
 
-sbl_bootimage_hs_install_sd: sbl_vision_apps_bootimage_hs sbl_qnx_bootimage_hs
-	cp $(SBL_BOOTFILES_PATH)/tiboot3.bin.signed $(SBL_SD_FS_PATH)/tiboot3.bin
-	cp $(SBL_BOOTFILES_PATH)/tifs.bin.signed $(SBL_SD_FS_PATH)/tifs.bin
-	cp $(SBL_BOOTFILES_PATH)/app.signed $(SBL_SD_FS_PATH)/app
-	cp $(SBL_BOOTFILES_PATH)/lateapp1.signed $(SBL_SD_FS_PATH)/lateapp1
-	cp $(SBL_BOOTFILES_PATH)/lateapp2.signed $(SBL_SD_FS_PATH)/lateapp2
-ifeq ($(BUILD_QNX_A72), yes)
-	cp $(SBL_BOOTFILES_PATH)/atf_optee.appimage.signed $(SBL_SD_FS_PATH)/atf_optee.appimage
-	cp $(SBL_BOOTFILES_PATH)/ifs_qnx.appimage.signed $(SBL_SD_FS_PATH)/ifs_qnx.appimage
+# sbl_bootimage_hs_install_sd: sbl_vision_apps_bootimage_hs sbl_qnx_bootimage_hs
+sbl_bootimage_hs_install_sd: sbl_vision_apps_bootimage_hs sbl_linux_bootimage_hs
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tiboot3.bin.signed $(SBL_SD_FS_PATH)/tiboot3.bin
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tifs.bin.signed $(SBL_SD_FS_PATH)/tifs.bin
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/app.signed $(SBL_SD_FS_PATH)/app
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp1.signed $(SBL_SD_FS_PATH)/lateapp1
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/lateapp2.signed $(SBL_SD_FS_PATH)/lateapp2
+# ifeq ($(BUILD_QNX_A72), yes)
+# 	cp $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage.signed $(SBL_SD_FS_PATH)/atf_optee.appimage
+# 	cp $(SBL_BOOTFILES_MMCSD_PATH)/ifs_qnx.appimage.signed $(SBL_SD_FS_PATH)/ifs_qnx.appimage
+ifeq ($(BUILD_LINUX_A72), yes)
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/atf_optee.appimage.signed           $(SBL_SD_FS_PATH)/atf_optee.appimage
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tidtb_linux.appimage.signed         $(SBL_SD_FS_PATH)/tidtb_linux.appimage
+	cp $(SBL_BOOTFILES_MMCSD_PATH)/tikernelimage_linux.appimage.signed $(SBL_SD_FS_PATH)/tikernelimage_linux.appimage
 endif
 	sync
 
@@ -448,6 +533,6 @@ sbl_bootimage_scrub: sbl_atf_optee_scrub
 	rm -rf $(PDK_PATH)/packages/ti/binary/ti/boot/
 	rm -rf $(PDK_PATH)/packages/ti/boot/sbl/binary
 	rm -rf $(MCUSW_PATH)/binary
-	rm -rf $(SBL_BOOTFILES_PATH)/
+	rm -rf $(SBL_BOOTFILES_MMCSD_PATH)/
 
 sbl_bootimage_clean: sbl_bootimage_scrub
diff --git a/vision_apps/makerules/makefile_sbl_combined_appimage.mak b/vision_apps/makerules/makefile_sbl_combined_appimage.mak
index 3183671fe..e0e5b0075 100644
--- a/vision_apps/makerules/makefile_sbl_combined_appimage.mak
+++ b/vision_apps/makerules/makefile_sbl_combined_appimage.mak
@@ -17,7 +17,8 @@ COMBINED_APPIMAGE_TOOL_PATH=$(SBL_REPO_PATH)/tools/combined_appimage
 ##############
 ### Main
 ##############
-sbl_combined_bootimage: sbl_sd atf_optee sbl_vision_apps sbl_qnx_combined_bootimage
+# sbl_combined_bootimage: sbl_sd atf_optee sbl_vision_apps sbl_qnx_combined_bootimage
+sbl_combined_bootimage: sbl_sd atf_optee sbl_vision_apps sbl_linux_combined_bootimage
 
 ##############
 ### Install
@@ -28,6 +29,12 @@ sbl_combined_bootimage_install_sd: sbl_combined_bootimage
 	cp $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/app $(SBL_SD_FS_PATH)
 	sync
 
+sbl_combined_bootimage_install_sd_hs: sbl_combined_bootimage
+	cp $(VISION_APPS_PATH)/out/sbl_bootfiles/tiboot3.bin.signed  $(SBL_SD_FS_PATH)/tiboot3.bin
+	cp $(VISION_APPS_PATH)/out/sbl_bootfiles/tifs.bin.signed     $(SBL_SD_FS_PATH)/tifs.bin
+	cp $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/app.signed $(SBL_SD_FS_PATH)/app
+	sync
+
 ##############
 ### SBL
 ##############
@@ -62,60 +69,92 @@ INPUT_IMG_PATH = $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/vision_apps
 sbl_vision_apps: sbl_sd
 	mkdir -p $(INPUT_IMG_PATH)
 	# build DM image
+ifeq ($(BUILD_LINUX_A72), yes)
+	$(eval FREDY_OS_TYPE=linux)
+else
+	$(eval FREDY_OS_TYPE=qnx)
+endif 
 ifeq ($(BUILD_CPU_MCU1_0),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu1_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu1_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu1_0.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu1_0.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu1_0.xer5f
 else
 	$(MAKE) -C $(PDK_PATH)/packages/ti/build   ipc_qnx_echo_testb_freertos CORE=mcu1_0 BOARD=$(BOARD) SOC=$(SOC) BUILD_PROFILE=release -s
-	cp $(PDK_PATH)/packages/ti/binary/ipc_qnx_echo_testb_freertos/bin/$(BOARD)/ipc_qnx_echo_testb_freertos_mcu1_0_release_strip.xer5f $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+#	cp $(PDK_PATH)/packages/ti/binary/ipc_qnx_echo_testb_freertos/bin/$(BOARD)/ipc_qnx_echo_testb_freertos_mcu1_0_release_strip.xer5f $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+#	cp $(PDK_PATH)/packages/ti/binary/ipc_qnx_echo_testb_freertos/bin/$(BOARD)/ipc_qnx_echo_testb_freertos_mcu1_0_release_strip.xer5f $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu1_0.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU2_0),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_0.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_0.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_0.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU2_1),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu2_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_1.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_1.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_1.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU3_0),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_0.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_0.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_0.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU3_1),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu3_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_1.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_1.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_1.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU4_0),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_0.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_0.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_0.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_0.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_0.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_0.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_0.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_0.xer5f
 endif
 ifeq ($(BUILD_CPU_MCU4_1),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_1.xer5f
-	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_1.xer5f
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_mcu4_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_1.xer5f
+#	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu4_1.xer5f
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/R5F/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_1.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_1.xer5f
+	$(TIARMCGT_LLVM_ROOT)/bin/tiarmstrip -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu4_1.xer5f
 endif
 ifeq ($(BUILD_CPU_C6x_1),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
-	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
+#	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_1.xe66
+	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_1.xe66
 endif
 ifeq ($(BUILD_CPU_C6x_2),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
-	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c6x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
+#	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/C66/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_2.xe66
+	$(CGT6X_ROOT)/bin/strip6x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_2.xe66
 endif
 ifeq ($(BUILD_CPU_C7x_1),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
-	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
+#	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_1.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_1.xe71
+	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_1.xe71
 endif
 ifeq ($(BUILD_CPU_C7x_2),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
-	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
+#	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_2.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_2.xe71
+	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_2.xe71
 endif
 ifeq ($(BUILD_CPU_C7x_3),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_3.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
-	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_3.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
+#	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_3.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_3.xe71
+	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_3.xe71
 endif
 ifeq ($(BUILD_CPU_C7x_4),yes)
-	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_4.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
-	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
+#	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(QNX_APP_PROFILE)/vx_app_rtos_qnx_c7x_4.out $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
+#	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
+	cp $(VISION_APPS_PATH)/out/$(TARGET_SOC)/$(C7X_TARGET)/$(RTOS)/$(LINUX_APP_PROFILE)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_4.out $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_4.xe71
+	$(CGT7X_ROOT)/bin/strip7x -p $(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_4.xe71
 endif
 
 ##############################
@@ -124,57 +163,77 @@ endif
 OUT_DIR=$(VISION_APPS_PATH)/out/sbl_combined_bootfiles/
 ATF_IMG=mpu1_0,$(COMBINED_APPIMAGE_ATF_OPTEE_PATH)/bl31.bin,0x70000000,0x70000000
 OPTEE_IMG=load_only,$(COMBINED_APPIMAGE_ATF_OPTEE_PATH)/bl32.bin,0x9e800000,0x9e800000
-KERNEL_IMG=load_only,$(QNX_BOOT_PATH)/qnx-ifs,0x80080000,0x80080000
-DTB_IMG=
-SPL_IMG=
-  IMG1=mcu1_0,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu1_0.xer5f
+ifeq ($(BUILD_LINUX_A72), yes)
+KERNEL_IMG=load_only,$(ATF_OPTEE_PATH)/Image,0x80080000,0x80080000
+#KERNEL_IMG=load_only,$(LINUX_FS_PATH)/boot/Image,0x80080000,0x80080000
+else
+endif 
+
+ifeq ($(BUILD_LINUX_A72), yes)
+DTB_IMG=load_only,$(ATF_OPTEE_PATH)/base-board.dtb,0x9e800000,0x9e800000
+#SPL_IMG=load_only,$(ATF_OPTEE_PATH)/base-board.dtb,0x9e800000,0x9e800000
+SPL_IMG=load_only,$(ATF_OPTEE_PATH)/u-boot-spl.bin,0x80080000,0x80080000
+endif
+
+
+  IMG1=mcu1_0,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu1_0.xer5f
 ifeq ($(BUILD_CPU_MCU2_0),yes)
-  IMG2=mcu2_0,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
+ # IMG2=mcu2_0,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_0.xer5f
+  IMG2=mcu2_0,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_0.xer5f
 else
   IMG2=
 endif
 ifeq ($(BUILD_CPU_MCU2_1),yes)
-  IMG3=mcu2_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
+#  IMG3=mcu2_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu2_1.xer5f
+  IMG3=mcu2_1,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu2_1.xer5f
 else
   IMG3=
 endif
 ifeq ($(BUILD_CPU_MCU3_0),yes)
-  IMG4=mcu3_0,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
+#  IMG4=mcu3_0,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_0.xer5f
+  IMG4=mcu3_0,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_0.xer5f
 else
   IMG4=
 endif
 ifeq ($(BUILD_CPU_MCU3_1),yes)
-  IMG5=mcu3_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
+#  IMG5=mcu3_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_mcu3_1.xer5f
+  IMG5=mcu3_1,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_mcu3_1.xer5f
 else
   IMG5=
 endif
 ifeq ($(BUILD_CPU_C6x_1),yes)
-  IMG6=c66xdsp_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
+#  IMG6=c66xdsp_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_1.xe66
+  IMG6=c66xdsp_1,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_1.xe66
 else
   IMG6=
 endif
 ifeq ($(BUILD_CPU_C6x_2),yes)
-  IMG7=c66xdsp_2,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
+#  IMG7=c66xdsp_2,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c6x_2.xe66
+  IMG7=c66xdsp_2,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c6x_2.xe66
 else
   IMG7=
 endif
 ifeq ($(BUILD_CPU_C7x_1),yes)
-  IMG8=c7x_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
+#  IMG8=c7x_1,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_1.xe71
+  IMG8=c7x_1,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_1.xe71
 else
   IMG8=
 endif
 ifeq ($(BUILD_CPU_C7x_2),yes)
-  IMG9=c7x_2,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
+#  IMG9=c7x_2,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_2.xe71
+  IMG9=c7x_2,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_2.xe71
 else
   IMG9=
 endif
 ifeq ($(BUILD_CPU_C7x_3),yes)
-  IMG10=c7x_3,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
+#  IMG10=c7x_3,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_3.xe71
+  IMG10=c7x_3,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_3.xe71
 else
   IMG10=
 endif
 ifeq ($(BUILD_CPU_C7x_4),yes)
-  IMG11=c7x_4,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
+#  IMG11=c7x_4,$(INPUT_IMG_PATH)/vx_app_rtos_qnx_c7x_4.xe71
+  IMG11=c7x_4,$(INPUT_IMG_PATH)/vx_app_rtos_$(FREDY_OS_TYPE)_c7x_4.xe71
 else
   IMG11=
 endif
@@ -189,6 +248,25 @@ sbl_qnx_combined_bootimage: atf_optee sbl_vision_apps
 	echo "done"
 	echo "---------------------------"
 
+sbl_linux_combined_bootimage: atf_optee sbl_vision_apps
+	echo "---------------------------"
+	echo "start"
+	echo "---------------------------"
+	cp -v $(PDK_PATH)/packages/ti/boot/sbl/tools/combined_appimage/bin/j721e_evm/base-board.dtb  $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/atf_optee_dir/
+	cp -v $(PSDK_LINUX_PATH)/board-support/prebuilt-images/u-boot-spl.bin-j7-evm $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/atf_optee_dir/u-boot-spl.bin
+	cp -v $(PSDK_LINUX_PATH)/board-support/prebuilt-images/Image $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/atf_optee_dir/
+	$(MAKE) -C $(COMBINED_APPIMAGE_TOOL_PATH) PDK_INSTALL_PATH=$(PDK_PATH)/packages OUT_DIR=$(OUT_DIR) \
+			ATF_IMG=$(ATF_IMG) OPTEE_IMG=$(OPTEE_IMG) KERNEL_IMG=$(KERNEL_IMG) DTB_IMG=$(DTB_IMG) SPL_IMG=$(SPL_IMG) \
+			IMG1=$(IMG1) IMG2=$(IMG2) IMG3=$(IMG3) IMG4=$(IMG4) IMG5=$(IMG5) IMG6=$(IMG6) IMG7=$(IMG7) IMG8=$(IMG8)
+	# $(MAKE) -C $(COMBINED_APPIMAGE_TOOL_PATH)
+	mv $(OUT_DIR)/combined.appimage $(OUT_DIR)/app
+	echo "---------------------------"
+	echo "done"
+	echo "---------------------------"
+
+sbl_linux_combined_bootimage_hs: sbl_linux_combined_bootimage
+	$(CERT_SCRIPT)  -b $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/app -o $(VISION_APPS_PATH)/out/sbl_combined_bootfiles/app.signed -c R5 -l 0x0 -k $(PDK_PATH)/packages/ti/build/makerules/k3_dev_mpk.pem
+
 ##############
 ### clean up
 ##############
diff --git a/vision_apps/platform/j721s2/rtos/common/app_cfg.h b/vision_apps/platform/j721s2/rtos/common/app_cfg.h
index 089714e05..392310acf 100755
--- a/vision_apps/platform/j721s2/rtos/common/app_cfg.h
+++ b/vision_apps/platform/j721s2/rtos/common/app_cfg.h
@@ -70,7 +70,7 @@
 #define ENABLE_PRINTF_REDIRECT
 
 #define ENABLE_IPC_MPU1_0
-#define ENABLE_IPC_MCU1_0
+//#define ENABLE_IPC_MCU1_0
 //#define ENABLE_IPC_MCU1_1
 #define ENABLE_IPC_MCU2_0
 #define ENABLE_IPC_MCU2_1
diff --git a/vision_apps/vision_apps_build_flags.mak b/vision_apps/vision_apps_build_flags.mak
index cbb199983..5c78f8a08 100755
--- a/vision_apps/vision_apps_build_flags.mak
+++ b/vision_apps/vision_apps_build_flags.mak
@@ -21,7 +21,7 @@ BUILD_CPU_C6x_2?=yes
 BUILD_CPU_C7x_1?=yes
 else ifeq ($(SOC),j721s2)
 BUILD_CPU_MPU1?=yes
-BUILD_CPU_MCU1_0?=yes
+BUILD_CPU_MCU1_0?=no
 BUILD_CPU_MCU2_0?=yes
 BUILD_CPU_MCU2_1?=yes
 BUILD_CPU_MCU3_0?=no

Dear Brijesh,

      Are there any new analytical progresses? Thank you very much.

Hi Brijesh，

       please help me check,  Thank you very much. 

Hi  Brijesh，  

    Yes，this the same ticket.

    Because I accidentally closed this ticket, I have made a new one.