AM6442: Running enet_icssg_layer2 example on R5F in combination with linux

Artur Toews

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

How to run the enet_layer2_icssg (ti.com) example together with Linux?

I'm able to run the ipc_rpmsg_echo_linux (ti.com) example, but when I try to start the icssg example from CCS I get stuck in `Module_clockSetFrequency()`.

And if I try to load it from linux I get this message:

root@am64xx-evm:~ echo start > /sys/class/remoteproc/remoteproc1/state
[ 446.709498] remoteproc remoteproc1: powering up 78000000.r5f
[ 446.717302] remoteproc remoteproc1: Booting fw image am64-main-r5f0_0-fw, size 2484656
-sh: echo: write error: Invalid argument[ 446.718777] remoteproc remoteproc1: Boot failed: -22

Can you please give some advise how to proceed?

BR
Artur

8 months ago

0 Nick Saulnier 8 months ago

TI__Guru* 78735 points

Hello Artur,

First, have you updated your Linux devicetree file so that ICSSG is disabled from Linux?

The new AM64x multicore academy has not been published yet, so I'll refer you to the AM62x version of page "How to allocate peripherals":
https://dev.ti.com/tirex/explore/node?node=A__AWq4FjhshhpOKvzFp789JQ__AM62-ACADEMY__uiYMDcq__LATEST

Note: booting R5F projects from Linux

The unmodified enet_layer2 project will fail to boot from Linux remoteproc, because the project does not include a resource table by default. For more information, refer to the AM62x version of page "Application Development on Remote Cores"
https://dev.ti.com/tirex/explore/node?node=A__AVn3JGT9fqm0PbS.pegO-g__AM62-ACADEMY__uiYMDcq__LATEST

Second, which boot flow are you using? SBL? SPL?

For more information about boot flow, refer to the AM62x version of page "Booting and disabling processor cores"
https://dev.ti.com/tirex/explore/node?node=A__ATV8lNuOMfaMT1..qF.S4g__AM62-ACADEMY__uiYMDcq__LATEST

The reason the boot flow matters that it dictates which board config file is used, the one that is in the MCU+ SDK (which uses SBL by default), or the one that is in the Linux SDK (which uses SPL by default). When I last checked in SDK 8.6, each SDK had slightly different settings in their board config files.

For more information from the last time I looked into this usecase, take a look at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1206420/processor-sdk-am64x-enet-open-failure-from-r5-when-a53-is-running/4596608#4596608

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi Nick,

thank you. Your link were helpful. I'm now able modify the icssg example an I'm now able to start it from linux and attach with CCS.

I disabled the icssg entries in the device-tree:

diff --git a/k3-am642-evm.dts b/k3-am642-evm.dts
index 0e20b0c..44dae9c 100644
--- a/k3-am642-evm.dts
+++ b/k3-am642-evm.dts
@@ -234,6 +234,7 @@
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_rgmii1_pins_default>;
+ status = "disabled";

sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
@@ -778,6 +779,7 @@
};

&icssg1_mdio {
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&icssg1_mdio1_pins_default>;

but now I'm hanging in Module_clockEnable().
It seems that one of the clocks:

SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {

{ TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_CORE_CLK, 250000000 },
{ TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_UCLK_CLK, 192000000 },
{ TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_IEP_CLK, 200000000 },

{ TISCI_DEV_UART1, TISCI_DEV_UART1_FCLK_CLK, 48000000 },

{ SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
};

cannot be enabled.

Do I need to load anything into the PRUs?

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

That looks like a good start! You disabled the PRU Ethernet driver from Linux. However, I bet the PRU_ICSSG itself is still enabled from when it was defined in k3-am64-main.dtsi.

Please also add these lines to k3-am642-evm.dts:

&icssg0 {
    status = "disabled";
};

&icssg1 {
    status = "disabled";
};

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hello Nick,

I'm getting forward. I've past the Module_clockEnable(), but the application still failes :-(.

root@am64xx-evm:~ cat /sys/kernel/debug/remoteproc/remoteproc1/trace0
[r5f0-0] 0.002331s : ==========================
[r5f0-0] 0.002602s : MULTIPORT TEST
[r5f0-0] 0.004308s : ==========================
[r5f0-0] 0.006762s :
[r5f0-0] 0.006819s : Init all peripheral clocks
[r5f0-0] 0.009256s : ----------------------------------------------
[r5f0-0] 0.013413s : Enabling clocks!
[r5f0-0] 0.015029s :
[r5f0-0] 0.015052s : Open all peripherals
[r5f0-0] 0.016968s : ----------------------------------------------
[r5f0-0] 0.021652s :
[r5f0-0] 0.021681s : Init configs EnetType:2, InstId :1
[r5f0-0] 0.024423s : ----------------------------------------------
[r5f0-0] 0.031284s : EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xfffffffb
EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xfffffffb
EnetHostPortDma_open: Failed to open Enet DMA RX channel: -1
Icssg_openDma: icssg1: failed to open ICSSG Host Port RX
Icssg_open: icssg1: failed to open DMA: -1
EnetPer_open: icssg1: Failed to open: -1
Enet_open: icssg1: Failed to open: -1
Enet_open failed62370s :
[r5f0-0] 0.064038s : Assertion @ Line: 335 in syscfg/ti_enet_open_close.c: hEnet != NULL_PTR : failed !!!

Do you have an Idea?

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

It failed to open the DMA channel, which makes me suspect that the DMA channels for PRU Ethernet were given to the Linux A53 cores instead of the R5F in the board config file.

1) Which R5F core are you trying to use? The dev team has been testing on R5F0_0, so that is the safest core to use in your tests here

2) which boot flow are you using? SBL? SPL?

Please take a look at the e2e thread I pointed to in the earlier response:

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi Nick,

We didn't care, but SPL I assume that we are using SPL beacuse we created the image with yocto, based on the ti project.

Do we have to switch to SBL?
As far as I understood from this side Booting and disabling processor cores the main benifit is that the SBL can boot r5f already in the bootloader stage instead of waiting for the linux to be booted.

If we can continue with SPL, where do I find the board config, and what do I have to change then?

Regards,
Artur

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

SPL is fine.

All the other information you are looking for should be in that response that I've already linked to twice. Please try following the steps in my response on April 18, 2023: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1206420/processor-sdk-am64x-enet-open-failure-from-r5-when-a53-is-running/4596608#4596608

Regards,

Nick

0 Nick Saulnier 8 months ago in reply to Nick Saulnier

TI__Guru* 78735 points

Also, what version of the SDK are you using?

My response linked above is good through SDK 8.6. And you can find information about integrating the updated board config file in the K3 Image Gen folder and using that to generate the .bin file in the Uboot SDK docs for SDK 8.6: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_06_00_42/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html (search for K3IG_DIR)

It looks like SDK 9.0 changed to using binman to generate the uboot files. So the files that are listed in the (out of date) K3 Resource Partition Tool documentation that are supposed to go into folder k3-image-gen in SDK 8.6, no longer go there because that folder does not exist in SDK 9.0 (https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/09_00_00_03/exports/docs/linux/How_to_Guides/Host/K3_Resource_Partitioning_Tool.html#generating-output-files)

Starting in SDK 9.0, the board config settings are now kept in the ti-u-boot directory:
ti-processor-sdk-linux-am64xx-evm-09.00.00.03/board-support/ti-u-boot$ ls board/ti/am64x/
am64x.env board-cfg.yaml evm.c Kconfig MAINTAINERS Makefile pm-cfg.yaml rm-cfg.yaml sec-cfg.yaml

I do not have time today to test the SDK 9.0 version of the K3 Resource Partition Tool to see if it generates .yaml output files that can be used. Let me know if this is an avenue you need me to take a look at more.

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi Nick,

I changed my board config according to this patch.

diff --git a/soc/am64x/evm/rm-cfg.c b/soc/am64x/evm/rm-cfg.c
index 9ee3904..5f8d376 100644
--- a/soc/am64x/evm/rm-cfg.c
+++ b/soc/am64x/evm/rm-cfg.c
@@ -847,7 +847,7 @@ const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
                        .num_resource = 8,
                        .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
                                        RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
-                       .host_id = HOST_ID_A53_2,
+                       .host_id = HOST_ID_MAIN_0_R5_1,
                },
                /* Packet DMA Free rings for Rx channel */
                {
@@ -952,7 +952,7 @@ const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
                        .num_resource = 64,
                        .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
                                        RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
-                       .host_id = HOST_ID_A53_2,
+                       .host_id = HOST_ID_MAIN_0_R5_1,
                },
                /* Packet DMA Free Tx channels */
                {
@@ -1041,7 +1041,7 @@ const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
                        .num_resource = 8,
                        .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
                                        RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
-                       .host_id = HOST_ID_A53_2,
+                       .host_id = HOST_ID_MAIN_0_R5_1,
                },
                /* Packet DMA Free Rx channels */
                {
@@ -1243,7 +1243,7 @@ const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
                        .num_resource = 4,
                        .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
                                        RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
-                       .host_id = HOST_ID_A53_2,
+                       .host_id = HOST_ID_MAIN_0_R5_1,
                },
                /* Packet DMA ICSSG1 Rx flows */
                {
@@ -1251,7 +1251,7 @@ const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
                        .num_resource = 64,
                        .type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
                                        RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
-                       .host_id = HOST_ID_A53_2,
+                       .host_id = HOST_ID_MAIN_0_R5_1,
                },
                /* Packet DMA Ring accelerator error event */
                {

But unfortunately I still get the same error message in r5f core:

root@am64xx-evm:~ cat /sys/kernel/debug/remoteproc/remoteproc1/trace0
[r5f0-0] 0.004535s : [IPC RPMSG ECHO] Nov 10 2023 08:36:17
[r5f0-0] 0.005155s : [IPC RPMSG ECHO] Remote Core waiting for messages at end point 13 ... !!!
[r5f0-0] 0.011540s : [IPC RPMSG ECHO] Remote Core waiting for messages at end point 14 ... !!!
[r5f0-0] 0.018037s : ==========================
[r5f0-0] 0.020459s : MULTIPORT TEST
[r5f0-0] 0.022886s : ==========================
[r5f0-0] 0.025339s :
[r5f0-0] 0.025398s : Init all peripheral clocks
[r5f0-0] 0.027835s : ----------------------------------------------
[r5f0-0] 0.031990s : Enabling clocks!
[r5f0-0] 0.033665s :
[r5f0-0] 0.033686s : Open all peripherals
[r5f0-0] 0.035547s : ----------------------------------------------
[r5f0-0] 0.040237s :
[r5f0-0] 0.040268s : Init configs EnetType:2, InstId :1
[r5f0-0] 0.043002s : ----------------------------------------------
[r5f0-0] 0.049996s : EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xffffffff
EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xffffffff
EnetHostPortDma_open: Failed to open Enet DMA RX channel: -1
Icssg_openDma: icssg1: failed to open ICSSG Host Port RX
Icssg_open: icssg1: failed to open DMA: -1
EnetPer_open: icssg1: Failed to open: -1
Enet_open: icssg1: Failed to open: -1
Enet_open failed80949s :
[r5f0-0] 0.082617s : Assertion @ Line: 335 in syscfg/ti_enet_open_close.c: hEnet != NULL_PTR : failed !!!

0 Artur Toews 8 months ago in reply to Artur Toews

Prodigy 120 points

I do not use the PSDK. Create my own image with yocto, but I'm based to REV 2a5a0339d5bd28d6f6aedaf02a6aaa9b73a248e4 of `meta-ti`.
As far as understood I had to change the `ti-sci-fw` receipe to modify the board config.

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

1) Off the top of my head I am not sure how to map that revision number to a version of Linux. Can you provide more information about the version of MCU+ SDK you are using, and the version of Linux you are using?

2) Can you provide the steps that you are following to pull the board config settings into the boot files?

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi,

1) The meta-ti uses u-boot ti-u-boot REV 78a217ca9ea687ee5c3e7dd3a339a1f7d136e93d and ti-linux-kernel REV 8b51d20b6e6e1b9277b59b7aaed8a97eff43097f.
According to the tags I assume it is the same revision than used for SDK 8.5
The MCU+-SDK is 09_00_00_30.

2) I created a ti-sci-fw_git.bbappend in our custom layer which applies the patch above. I assume the ti-sci-fw receipe is responsable to create my tiboot3.bin which contains the "RM config" and the "board config".

Regards,
Artur

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

Please give me a day or so to try generating the config files to compare against yours. Feel free to ping the thread if I have not responded by Monday.

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi Nick,

Have you got any further?

Regards,

Artur

0 Artur Toews 8 months ago in reply to Artur Toews

Prodigy 120 points

Ping

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

Thank you for the ping, I'm back from Thanksgiving vacation now.

When I did a diff between the default AM64x MCU+ SDK board config settings and the default Linux SDK board config settings for SDK 8.5, it looks like you are modifying the 5 entries I would expect for using the PRU Ethernet DMA. I'll include the partial diff here:

•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0/1_TX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0/1_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0/1_TX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0/1_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0/1_RX_CHAN), 
o	Linux host_id A53, MCU+ host_id MAIN_0_R5_0 and MAIN_0_R5_1
o	So it looks like with SBL boot PRUETH only supports R5, with SPL boot PRUETH only supports Linux A53

and then the full list of differences I found here (just in case a future reader finds it helpful):

differences between SDK 8.5 MCU+ SDK RM settings, and the Linux SDK 8.5 generated rm-cfg.c file.
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT), 
o	36 resources in MCU+ to A53_2, 35 resources in Linux to A53_2
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT) 
o	17 resources in MCU+ to TISCI_HOST_ID_ALL, 16 resources in Linux to host_id is TISCI_HOST_ID_ALL
o	This is in addition to hundreds of other resources assigned directly to each core, so would this have an impact?

•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT), 
o	In linux, 12 resources to A53_2. In MCU+, 8 to Linux, 2 to MAIN_0_R5_1, 2 to MAIN_0_R5_3
o	i.e., R5F0 does not have access to Main GPIO peripheral with default Linux configs

•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN), 
o	MCU+ has host_id set to all, Linux has routed to A53, shared with MAIN_0_R5_0
o	What does this mean? Can R5 use CPSW if using SPL boot? If so, can both cores, or only R5F0_0 during secure mode (is this boot time?)

•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2/3_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2/3_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2/3_CHAN), 
o	Linux host ID A53_2, MCU+ host_id all
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN), 
o	Only defined in MCU+

•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0/1_TX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0/1_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0/1_TX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0/1_RX_CHAN),
•	.type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0/1_RX_CHAN), 
o	Linux host_id A53, MCU+ host_id MAIN_0_R5_0 and MAIN_0_R5_1
o	So it looks like with SBL boot PRUETH only supports R5, with SPL boot PRUETH only supports Linux A53

I am going to send your thread over to a team member more familiar with the MCU+ SDK networking to see if they have any additional thoughts about what might be going on.

Regards,

Nick

0 Nitika Verma 8 months ago in reply to Nick Saulnier

TI__Expert 4540 points

Hi Artur,

Were you able to make any progress with the above shared board config diff?

I am looking into the issue, do let me know if you have any more findings.

Regards,

Nitika

0 Artur Toews 8 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nitika,

no. I'm still waiting for your advise. I've made the changes but without success.

Therefore I asked if I have changed the correct file.

Regards,

Artur

0 Artur Toews 8 months ago in reply to Artur Toews

Prodigy 120 points

BTW: I didn't read any recommendations for action from Nick's answer, only the status quo of his investigation. Or what should I change in my rm.cfg.c?

0 Nick Saulnier 8 months ago in reply to Artur Toews

TI__Guru* 78735 points

Hello Artur,

To clarify, it looked like you made the changes I would have suggested. So I have passed your thread over to Nitika for more guidance.

Regards,

Nick

0 Artur Toews 8 months ago in reply to Nick Saulnier

Prodigy 120 points

Hi Nikita,

this is my current rm-cfg.c:

/*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "common.h"
#include <hosts.h>
#include <devices.h>
#include <resasg_types.h>

const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
	.rm_boardcfg = {
		/* boardcfg_abi_rev */
		.rev = {
			.boardcfg_abi_maj = 0x0,
			.boardcfg_abi_min = 0x1,
		},

		/* boardcfg_rm_host_cfg */
		.host_cfg = {
			.subhdr = {
				.magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_host_cfg),
			},
			.host_cfg_entries = {
				{
					.host_id = HOST_ID_A53_2,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_M4_0,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
			}
		},

		/* boardcfg_rm_resasg */
		.resasg = {
			.subhdr = {
				.magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_resasg),
			},
			.resasg_entries_size =
				BOARDCFG_RM_RESASG_ENTRIES *
				sizeof (struct boardcfg_rm_resasg_entry),
			.reserved = 0,
			/* .resasg_entries is set via boardcfg_rm_local */
		},
	},

	/* This is actually part of .resasg */
	.resasg_entries = {
		/* Compare event Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Main GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 14,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* MCU GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_M4_0,
		},
		/* Timesync Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 41,
			.type = RESASG_UTYPE (AM64X_DEV_TIMESYNC_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global event trigger */
		{
			.start_resource = 50176,
			.num_resource = 136,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Split TR Rx channel */
		{
			.start_resource = 48,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 60,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 62,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 66,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Rings for Split TR Tx channel */
		{
			.start_resource = 28,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 40,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 42,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 46,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Split TR Rx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Split TR Tx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* DMASS Interrupt aggregator Virtual interrupts */
		{
			.start_resource = 5,
			.num_resource = 35,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 58,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 92,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 106,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 168,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_M4_0,
		},
		/* DMASS Interrupt aggregator Global events */
		{
			.start_resource = 16,
			.num_resource = 512,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 784,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 976,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 1232,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 1424,
			.num_resource = 96,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 1520,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS timer manager event */
		{
			.start_resource = 0,
			.num_resource = 1024,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx channel error event */
		{
			.start_resource = 4096,
			.num_resource = 42,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx flow completion event */
		{
			.start_resource = 4608,
			.num_resource = 112,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx channel error event */
		{
			.start_resource = 5120,
			.num_resource = 29,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow completion event */
		{
			.start_resource = 5632,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow starvation event */
		{
			.start_resource = 6144,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow firewall event */
		{
			.start_resource = 6656,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel error event */
		{
			.start_resource = 8192,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel data completion event */
		{
			.start_resource = 8704,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel ring completion event */
		{
			.start_resource = 9216,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel error event */
		{
			.start_resource = 9728,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel data completion event */
		{
			.start_resource = 10240,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel ring completion event */
		{
			.start_resource = 10752,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel error event */
		{
			.start_resource = 11264,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel data completion event */
		{
			.start_resource = 11776,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel ring completion event */
		{
			.start_resource = 12288,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS UDMA global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Free rings for Tx channel */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Tx channel */
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Tx channel1 */
		{
			.start_resource = 88,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Tx channel */
		{
			.start_resource = 96,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for ICSSG1 Tx channel */
		{
			.start_resource = 104,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Free rings for Rx channel */
		{
			.start_resource = 112,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 119,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 121,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 125,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 127,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Rx channel */
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Rx channel1 */
		{
			.start_resource = 144,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rings for SA2UL Rx channel2 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for SA2UL Rx channel3 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Rx channel */
		{
			.start_resource = 160,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for ICSSG1 Rx channel */
		{
			.start_resource = 224,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Free Tx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Tx channels */
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Tx channel1 */
		{
			.start_resource = 25,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Tx channels */
		{
			.start_resource = 26,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA ICSSG1 Tx channels */
		{
			.start_resource = 34,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Free Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Free flows for Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Rx channel */
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA CPSW Rx flows */
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Rx channel0 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel1 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel2 */
		{
			.start_resource = 19,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel2 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 */
		{
			.start_resource = 20,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Rx channel */
		{
			.start_resource = 21,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA ICSSG0 Rx flows */
		{
			.start_resource = 48,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA ICSSG1 Rx channel */
		{
			.start_resource = 25,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA ICSSG1 Rx flows */
		{
			.start_resource = 112,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Ring accelerator error event */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA virt_id range */
		{
			.start_resource = 2,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_VIRTID),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for IPC */
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 22,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 26,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_ALL,
		},
	},
};

before I tried this one, but with the same result:

/*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "common.h"
#include <hosts.h>
#include <devices.h>
#include <resasg_types.h>

const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
	.rm_boardcfg = {
		/* boardcfg_abi_rev */
		.rev = {
			.boardcfg_abi_maj = 0x0,
			.boardcfg_abi_min = 0x1,
		},

		/* boardcfg_rm_host_cfg */
		.host_cfg = {
			.subhdr = {
				.magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_host_cfg),
			},
			.host_cfg_entries = {
				{
					.host_id = HOST_ID_A53_2,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_M4_0,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
			}
		},

		/* boardcfg_rm_resasg */
		.resasg = {
			.subhdr = {
				.magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_resasg),
			},
			.resasg_entries_size =
				BOARDCFG_RM_RESASG_ENTRIES *
				sizeof (struct boardcfg_rm_resasg_entry),
			.reserved = 0,
			/* .resasg_entries is set via boardcfg_rm_local */
		},
	},

	/* This is actually part of .resasg */
	.resasg_entries = {
		/* Compare event Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Main GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 14,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* MCU GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_M4_0,
		},
		/* Timesync Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 41,
			.type = RESASG_UTYPE (AM64X_DEV_TIMESYNC_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global event trigger */
		{
			.start_resource = 50176,
			.num_resource = 136,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Split TR Rx channel */
		{
			.start_resource = 48,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 60,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 62,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 66,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Rings for Split TR Tx channel */
		{
			.start_resource = 28,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 40,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 42,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 46,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Split TR Rx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Split TR Tx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* DMASS Interrupt aggregator Virtual interrupts */
		{
			.start_resource = 5,
			.num_resource = 35,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 58,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 92,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 106,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 168,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_M4_0,
		},
		/* DMASS Interrupt aggregator Global events */
		{
			.start_resource = 16,
			.num_resource = 512,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 784,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 976,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 1232,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 1424,
			.num_resource = 96,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 1520,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS timer manager event */
		{
			.start_resource = 0,
			.num_resource = 1024,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx channel error event */
		{
			.start_resource = 4096,
			.num_resource = 42,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx flow completion event */
		{
			.start_resource = 4608,
			.num_resource = 112,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx channel error event */
		{
			.start_resource = 5120,
			.num_resource = 29,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow completion event */
		{
			.start_resource = 5632,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow starvation event */
		{
			.start_resource = 6144,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow firewall event */
		{
			.start_resource = 6656,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel error event */
		{
			.start_resource = 8192,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel data completion event */
		{
			.start_resource = 8704,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel ring completion event */
		{
			.start_resource = 9216,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel error event */
		{
			.start_resource = 9728,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel data completion event */
		{
			.start_resource = 10240,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel ring completion event */
		{
			.start_resource = 10752,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel error event */
		{
			.start_resource = 11264,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel data completion event */
		{
			.start_resource = 11776,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel ring completion event */
		{
			.start_resource = 12288,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS UDMA global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Free rings for Tx channel */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Tx channel */
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Tx channel1 */
		{
			.start_resource = 88,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Tx channel */
		{
			.start_resource = 96,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG1 Tx channel */
		{
			.start_resource = 104,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free rings for Rx channel */
		{
			.start_resource = 112,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 119,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 121,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 125,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 127,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Rx channel */
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Rx channel1 */
		{
			.start_resource = 144,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rings for SA2UL Rx channel2 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for SA2UL Rx channel3 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Rx channel */
		{
			.start_resource = 160,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG1 Rx channel */
		{
			.start_resource = 224,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free Tx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Tx channels */
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Tx channel1 */
		{
			.start_resource = 25,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Tx channels */
		{
			.start_resource = 26,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG1 Tx channels */
		{
			.start_resource = 34,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Free flows for Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Rx channel */
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA CPSW Rx flows */
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Rx channel0 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel1 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel2 */
		{
			.start_resource = 19,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel2 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 */
		{
			.start_resource = 20,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Rx channel */
		{
			.start_resource = 21,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Rx flows */
		{
			.start_resource = 48,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG1 Rx channel */
		{
			.start_resource = 25,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA ICSSG1 Rx flows */
		{
			.start_resource = 112,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Ring accelerator error event */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA virt_id range */
		{
			.start_resource = 2,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_VIRTID),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for IPC */
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 22,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 26,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_ALL,
		},
	},
};

Regards,

Artur

0 Nitika Verma 8 months ago in reply to Artur Toews

TI__Expert 4540 points

Hi Artur,

As Nick mentioned earlier, you have made the changes that would be required.

There is a chance you are not building the updated board config files into the uboot files, that could cause issues as well.

Please see: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_05_00_21/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html

The specific steps where those board config files are built into the uboot files are here:

$ export K3IG_DIR=<path-to-k3-image-gen>

To build tiboot3-am64x-gp-evm.bin. Saved in $K3IG_DIR. Requires u-boot-spl.bin and ti-sci-firmware-am64x-gp.bin.

$ cd $K3IG_DIR

$ make CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=am64x SOC_TYPE=gp SBL=$UBOOT_DIR/out/r5/spl/u-boot-spl.bin SYSFW_DIR=$SYSFW_DIR

Regards,

Nitika

0 Artur Toews 8 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nikita,

as I already metioned. We use meta-ti in our yocto project to build the tiboot3.bin.

Currently we are using this receipe:
ti-sci-fw_git.bb « ti-sci-fw « recipes-bsp « meta-ti-bsp - meta-ti - Layer containing TI hardware support metadata (yoctoproject.org)

But we are overwriting the original rm-cfg.c with the content above.

This receipe does exactly what you described.

Have you been able to load mcu code with using the icssg unit with my rm-cfg.c? Maybe I'm missing something.

0 Nitika Verma 8 months ago in reply to Artur Toews

TI__Expert 4540 points

Hi Artur,

I will try this on my end and compare our configurations to narrow down on the issue. Allow me some time to do that.

Regards,

Nitika

0 Artur Toews 8 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nitika,

thank you.

I changed my rm-cfg.c again:

/*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (C) 2019-2021 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "common.h"
#include <hosts.h>
#include <devices.h>
#include <resasg_types.h>

const struct boardcfg_rm_local am64x_boardcfg_rm_data = {
	.rm_boardcfg = {
		/* boardcfg_abi_rev */
		.rev = {
			.boardcfg_abi_maj = 0x0,
			.boardcfg_abi_min = 0x1,
		},

		/* boardcfg_rm_host_cfg */
		.host_cfg = {
			.subhdr = {
				.magic = BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_host_cfg),
			},
			.host_cfg_entries = {
				{
					.host_id = HOST_ID_A53_2,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_M4_0,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_0_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_1,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
				{
					.host_id = HOST_ID_MAIN_1_R5_3,
					.allowed_atype = 0b101010,
					.allowed_qos = 0xAAAA,
					.allowed_orderid = 0xAAAAAAAA,
					.allowed_priority = 0xAAAA,
					.allowed_sched_priority = 0xAA,
				},
			}
		},

		/* boardcfg_rm_resasg */
		.resasg = {
			.subhdr = {
				.magic = BOARDCFG_RM_RESASG_MAGIC_NUM,
				.size = sizeof (struct boardcfg_rm_resasg),
			},
			.resasg_entries_size =
				BOARDCFG_RM_RESASG_ENTRIES *
				sizeof (struct boardcfg_rm_resasg_entry),
			.reserved = 0,
			/* .resasg_entries is set via boardcfg_rm_local */
		},
	},

	/* This is actually part of .resasg */
	.resasg_entries = {
		/* Compare event Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 16,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_CMP_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Main GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 14,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_MAIN_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* MCU GPIO Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_M4_0,
		},
		/* Timesync Interrupt Router */
		{
			.start_resource = 0,
			.num_resource = 41,
			.type = RESASG_UTYPE (AM64X_DEV_TIMESYNC_EVENT_INTROUTER0,
					RESASG_SUBTYPE_IR_OUTPUT),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global event trigger */
		{
			.start_resource = 50176,
			.num_resource = 136,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Rings for Split TR Rx channel */
		{
			.start_resource = 48,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 54,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 60,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 62,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 66,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Rings for Split TR Tx channel */
		{
			.start_resource = 28,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 34,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 40,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 42,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 46,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Block copy channels */
		{
			.start_resource = 0,
			.num_resource = 12,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 12,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 20,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 26,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 27,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Block Copy DMA Split TR Rx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* Block Copy DMA Split TR Tx channels */
		{
			.start_resource = 0,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 6,
			.num_resource = 6,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 12,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 14,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 18,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_BCDMA_0,
					RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		/* DMASS Interrupt aggregator Virtual interrupts */
		{
			.start_resource = 5,
			.num_resource = 35,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 44,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 58,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 92,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 106,
			.num_resource = 14,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 168,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_VINT),
			.host_id = HOST_ID_M4_0,
		},
		/* DMASS Interrupt aggregator Global events */
		{
			.start_resource = 16,
			.num_resource = 512,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 528,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 784,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 976,
			.num_resource = 256,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 1232,
			.num_resource = 192,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 1424,
			.num_resource = 96,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_M4_0,
		},
		{
			.start_resource = 1520,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS timer manager event */
		{
			.start_resource = 0,
			.num_resource = 1024,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx channel error event */
		{
			.start_resource = 4096,
			.num_resource = 42,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Tx flow completion event */
		{
			.start_resource = 4608,
			.num_resource = 112,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx channel error event */
		{
			.start_resource = 5120,
			.num_resource = 29,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow completion event */
		{
			.start_resource = 5632,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow starvation event */
		{
			.start_resource = 6144,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rx flow firewall event */
		{
			.start_resource = 6656,
			.num_resource = 176,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel error event */
		{
			.start_resource = 8192,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel data completion event */
		{
			.start_resource = 8704,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA BC channel ring completion event */
		{
			.start_resource = 9216,
			.num_resource = 28,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel error event */
		{
			.start_resource = 9728,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel data completion event */
		{
			.start_resource = 10240,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Tx channel ring completion event */
		{
			.start_resource = 10752,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel error event */
		{
			.start_resource = 11264,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel data completion event */
		{
			.start_resource = 11776,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Block copy DMA Rx channel ring completion event */
		{
			.start_resource = 12288,
			.num_resource = 20,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_INTAGGR_0,
					RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
			.host_id = HOST_ID_ALL,
		},
		/* DMASS UDMA global config */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Free rings for Tx channel */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Tx channel */
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Tx channel1 */
		{
			.start_resource = 88,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Tx channel */
		{
			.start_resource = 96,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Rings for ICSSG1 Tx channel */
		{
			.start_resource = 104,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free rings for Rx channel */
		{
			.start_resource = 112,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 116,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 119,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 121,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 125,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 127,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Rings for CPSW Rx channel */
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 128,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA Rings for SA2UL Rx channel1 */
		{
			.start_resource = 144,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA Rings for SA2UL Rx channel2 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for SA2UL Rx channel3 */
		{
			.start_resource = 152,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for ICSSG0 Rx channel */
		{
			.start_resource = 160,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Rings for ICSSG1 Rx channel */
		{
			.start_resource = 224,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free Tx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Tx channels */
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Tx channel1 */
		{
			.start_resource = 25,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Tx channels */
		{
			.start_resource = 26,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA ICSSG1 Tx channels */
		{
			.start_resource = 34,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Free Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA Free flows for Rx channels */
		{
			.start_resource = 0,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 4,
			.num_resource = 3,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 7,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 9,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 13,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 15,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
			.host_id = HOST_ID_M4_0,
		},
		/* Packet DMA CPSW Rx channel */
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA CPSW Rx flows */
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		{
			.start_resource = 16,
			.num_resource = 16,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		/* Packet DMA SA2UL Rx channel0 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel1 flows */
		{
			.start_resource = 32,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA SA2UL Rx channel2 */
		{
			.start_resource = 19,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel2 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 */
		{
			.start_resource = 20,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA SA2UL Rx channel3 flows */
		{
			.start_resource = 40,
			.num_resource = 8,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA ICSSG0 Rx channel */
		{
			.start_resource = 21,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA ICSSG0 Rx flows */
		{
			.start_resource = 48,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA ICSSG1 Rx channel */
		{
			.start_resource = 25,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA ICSSG1 Rx flows */
		{
			.start_resource = 112,
			.num_resource = 64,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_PKTDMA_0,
					RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		/* Packet DMA Ring accelerator error event */
		{
			.start_resource = 0,
			.num_resource = 1,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_ERROR_OES),
			.host_id = HOST_ID_ALL,
		},
		/* Packet DMA virt_id range */
		{
			.start_resource = 2,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_VIRTID),
			.host_id = HOST_ID_A53_2,
		},
		/* Packet DMA Rings for IPC */
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_0,
		},
		{
			.start_resource = 20,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_1,
		},
		{
			.start_resource = 22,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_0_R5_3,
		},
		{
			.start_resource = 24,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_1,
		},
		{
			.start_resource = 26,
			.num_resource = 2,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_MAIN_1_R5_3,
		},
		{
			.start_resource = 28,
			.num_resource = 4,
			.type = RESASG_UTYPE (AM64X_DEV_DMASS0_RINGACC_0,
					RESASG_SUBTYPE_RA_GENERIC_IPC),
			.host_id = HOST_ID_ALL,
		},
	},
};

Now my error message a little different:
cat /sys/kernel/debug/remoteproc/remoteproc1/trace0 [r5f0-0] 0.005996s : [IPC RPMSG ECHO] Nov 10 2023 08:36:17 [r5f0-0] 0.006620s : [IPC RPMSG ECHO] Remote Core waiting for messages at end point 13 ... !!! [r5f0-0] 0.013009s : [IPC RPMSG ECHO] Remote Core waiting for messages at end point 14 ... !!! [r5f0-0] 0.019506s : ========================== [r5f0-0] 0.021927s : MULTIPORT TEST [r5f0-0] 0.024352s : ========================== [r5f0-0] 0.026805s : [r5f0-0] 0.026864s : Init all peripheral clocks [r5f0-0] 0.029301s : ---------------------------------------------- [r5f0-0] 0.033456s : Enabling clocks! [r5f0-0] 0.035132s : [r5f0-0] 0.035152s : Open all peripherals [r5f0-0] 0.037016s : ---------------------------------------------- [r5f0-0] 0.041716s : [r5f0-0] 0.041748s : Init configs EnetType:2, InstId :1 [r5f0-0] 0.044468s : ---------------------------------------------- [r5f0-0] 0.051495s : EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xffffffff Assertion @ Line: 2643 in /nightlybuilds/mcupsdk_internal/jenkins/ [r5f0-0] 0.063004s : mcu_plus_sdk_am64x_09_00_00_35/source/networking/enet/core/src/dma/udma/enet_udma.c: false

Maybe that helps to find where the problem is.

0 Nitika Verma 8 months ago in reply to Artur Toews

TI__Expert 4540 points

Thanks Artur,

It seems like the UDMA channel is already reserved by some peripheral which is causing this failure. I will look into this.

Regards,

Nitika

0 Nitika Verma 7 months ago in reply to Nitika Verma

TI__Expert 4540 points

Hi Artur,

With the latest rm-cfg.c file changes shared by you. I am able to load the example and get the logs (attached below) from remoteproc.

==========================
      MULTIPORT TEST      
==========================

Init all peripheral clocks
----------------------------------------------
Enabling clocks!

Open all peripherals
----------------------------------------------

Init  configs EnetType:2, InstId :1
----------------------------------------------
Mdio_open: MDIO Manual_Mode enabled
icssg1-p1: Open port 1
EnetPhy_bindDriver: PHY 15: OUI:080028 Model:0f Ver:01 <-> 'dp83869' : OK
icssg1-p1: Open port 2
PHY 15 is alive
icssg1-p1: Register async IOCTL callback
icssg1-p1: Register TX timestamp callback

Attach core id 1 on all peripherals
----------------------------------------------
icssg1-p1: Attach core

Create RX tasks
----------------------------------------------
icssg1-p1: Create RX task
icssg1-p1: Waiting for link up...

Enet Multiport Menu:
 'T'  -  Enable timestamp prints
 't'  -  Disable timestamp prints
 's'  -  Print statistics
 'r'  -  Reset statistics
 'm'  -  Show allocated MAC addresses
 'd'  -  Enable dscp based priority mapping
 'x'  -  Stop the test

Regards,

Nitika

0 Artur Toews 7 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nitika,

that sounds promising. Then we have to find out, what's different on my side.

Which project did you use for the MCU side? And what did you change to get it running?

On which core did you load the application?

Regards,

Artur

+1 Nitika Verma 7 months ago in reply to Artur Toews

TI__Expert 4540 points

Hi Artur,

Processor SDK version: 08_05_00_21

MCU+ SDK version: 09_00_00_30

Project on the MCU side: enet_layer2_icssg

Please find the procedure and file modification done on my side (modified files are present in the attached zip folder at the end):

MCU+ SDK side:

1. Add resource table to the firmware using the syscfg and linker file of ipc_rpmsg_echo_linux example as reference. (files in the zip - example.syscfg, linker.cmd)

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1193620/faq-am62x-am64x-how-to-allow-linux-to-load-m4f-r5f-firmware-by-adding-a-resource-table

2. Build the example to get the .out file, copy this file to the /lib/firmware/pdk-ipc of the root partition.

Processor SDK side:

1. Update the Linux devicetree file to disable ICSSG from Linux.(modified file in the zip - k3-am642-evm.dts)

2. Update the rm-cfg.c file to assign the DMA channels for PRU Ethernet to R5F instead of the Linux A53 cores (modified file in the zip - rm-cfg.c)

3. Build the modified k3-am642-evm.dts file to generate corresponding .dtb file and replace it in /boot of the root partition.

4. Build u-boot and sysfw-image to generate the tiboot3.bin file. Replace the tiboot3 in the boot partition with our generated file.

Booting remote core from linux:

Follow the steps from here to boot remote core R5F0-0 from Linux.

You can find the modified files here: enet_icssg_with_linux.zip

Regards,

Nitika

0 Artur Toews 7 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nitika,

I cannot find the differences to my application. I didn't try to get it running with the ti-image, yet, but I'm confused why it does not work with my custom setup.

MCU + SDK

1. Copy your example.syscfg and linker.cmd to my project

2. Compile and copy to /lib/firmware

Linux

1. copy rm-cfg.c to $K3IG_DIR/soc/am64x/evm/

2. copy `icssg1_eth` section of DTS file to my DTS file

2. build tiboot3.bin and DTS

3. copy tiboot3.bin and DTB to flash device

4. reboot device

But I still get this issue:

cat /sys/kernel/debug/remoteproc/remoteproc1/trace0
[r5f0-0] 0.004921s : ==========================
[r5f0-0] 0.005192s : MULTIPORT TEST
[r5f0-0] 0.006893s : ==========================
[r5f0-0] 0.009344s :
[r5f0-0] 0.009402s : Init all peripheral clocks
[r5f0-0] 0.011842s : ----------------------------------------------
[r5f0-0] 0.015997s : Enabling clocks!
[r5f0-0] 0.017669s :
[r5f0-0] 0.017690s : Open all peripherals
[r5f0-0] 0.019553s : ----------------------------------------------
[r5f0-0] 0.024392s :
[r5f0-0] 0.024421s : Init configs EnetType:2, InstId :1
[r5f0-0] 0.027009s : ----------------------------------------------
[r5f0-0] 0.033992s : EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xffffffff
EnetUdma_openRxCh: [Enet UDMA] UDMA RX Channel open failed: 0xffffffff
EnetHostPortDma_open: Failed to open Enet DMA RX channel: -1
Icssg_openDma: icssg1: failed to open ICSSG Host Port RX
Icssg_open: icssg1: failed to open DMA: -1
EnetPer_open: icssg1: Failed to open: -1
Enet_open: icssg1: Failed to open: -1
Enet_open failed64954s :
[r5f0-0] 0.066623s : Assertion @ Line: 335 in syscfg/ti_enet_open_close.c: hEnet != NULL_PTR : failed !!!

0 Nitika Verma 7 months ago in reply to Artur Toews

TI__Expert 4540 points

Hi Artur,

Artur Toews said:
copy `icssg1_eth` section of DTS file to my DTS file

Can you pull in all the changes from my DTS file and try.

While disabling icssg1_eth node

icssg1_eth: icssg1-eth {
		compatible = "ti,am642-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&icssg1_rgmii1_pins_default>;

		sram = <&oc_sram>;
		ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";

		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
				      <2>,
				      <2>,
				      <2>,	/* MII mode */
				      <2>,
				      <2>;

		mii-g-rt = <&icssg1_mii_g_rt>;
		mii-rt = <&icssg1_mii_rt>;
		iep = <&icssg1_iep0>,  <&icssg1_iep1>;

		interrupt-parent = <&icssg1_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0", "tx_ts1";

		dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
		       <&main_pktdma 0xc201 15>, /* egress slice 0 */
		       <&main_pktdma 0xc202 15>, /* egress slice 0 */
		       <&main_pktdma 0xc203 15>, /* egress slice 0 */
		       <&main_pktdma 0xc204 15>, /* egress slice 1 */
		       <&main_pktdma 0xc205 15>, /* egress slice 1 */
		       <&main_pktdma 0xc206 15>, /* egress slice 1 */
		       <&main_pktdma 0xc207 15>, /* egress slice 1 */
		       <&main_pktdma 0x4200 15>, /* ingress slice 0 */
		       <&main_pktdma 0x4201 15>, /* ingress slice 1 */
		       <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
		       <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			    "rx0", "rx1",
			    "rxmgm0", "rxmgm1";

		icssg1_emac0: ethernet-mii0 {
			phy-handle = <&icssg1_phy1>;
			phy-mode = "rgmii-rxid";
			syscon-rgmii-delay = <&main_conf 0x4110>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		icssg1_emac1: ethernet-mii1 {
			syscon-rgmii-delay = <&main_conf 0x4114>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			status = "disabled";
		};
	};

We delete the above code and set the status to disabled:

icssg1_eth: icssg1-eth {
	status = "disabled";
};

In doing so, we removed pinctrl-0 = <&icssg1_rgmii1_pins_default>; from the node.

That means Linux will not apply these pinmux settings. Since R5F core is using the peripheral, the pinmux settings are handled in the R5F project's SysConfig. So, we delete the icssg1_rgmii1_pins_default pinmux settings from the DTS.

icssg1_rgmii1_pins_default: icssg1-rgmii1-pins-default {
	pinctrl-single,pins = <
		AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
		AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
		AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
		AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
		AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
		AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
		AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
		AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
		AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
		AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
		AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
		AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
	>;
};

Similarly, for all nodes from which pinctrl-0 is removed, the respective pinmux settings need to be removed from the DTS.

Regards,

Nitika

+1 Artur Toews 7 months ago in reply to Nitika Verma

Prodigy 120 points

Hi Nitika,

it seems that I found the issue.

I made the effort and did all the steps you metioned and finially I got the example running. Hey!!!

Then I copied just the tiboot3.bin to my setup and: voila, it also runs the application.

Therefore I digged in the changes of tiboot3.bin and figured out the meta-ti I'm using is downloading the firmware-binaries from https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/commit/?h=ti-linux-firmware in revision 7875237b357ecf27300658e65e9927cef7e299ed whereby the PSDK contains the binaries of revision 17cc30de6c1ce7ab6010f2391986241f3bffd8cb.

That's why I have now changed to 17cc30de6c1ce7ab6010f2391986241f3bffd8cb in my yocto project and now it works.

Can you try to get the application running with the firmware binaries of revision 7875237b357ecf27300658e65e9927cef7e299ed?

Regards,

Artur

0 Nitika Verma 7 months ago in reply to Artur Toews

TI__Expert 4540 points

Hi Artur,

Glad to know that the example is running. Thank you for confirming that.

Yes, the revision 17cc30de6c1ce7ab6010f2391986241f3bffd8cb corresponds to version 8.5 firmware binaries as you can see here.

If you want to continue with firmware binaries of revision 7875237b357ecf27300658e65e9927cef7e299ed, I would suggest you to open a new thread with that requirement since the issue for this one is resolved.

Regards,

Nitika

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AM6442: Running enet_icssg_layer2 example on R5F in combination with linux