AM6422: Alternate IBIS model for better RGMII drive strength

Hello Parthan

Thank you for the query.

Can you try with 1.8V IO levels.

I am checking internally with the expert.

Regards,

Sreenivasa

Hello Parthan

sprm730d.

An updated version of the model is available on TI.com.   sprm730d. 

Please use the updated model.

Here are some additional inputs from the simulation expert:

We don’t support any other drive strength besides the nom value for LVCMOS buffers as that is the only one at which chip-level STA has been closed. I believe this corresponds to a 40-ohm driver. The IBIS model has been updated to contain only those drive strengths where we have closed timing internally. The customer should check the impedance of the board traces and ensure there are appropriate termination resistors near the sink, where the waveforms appear to be captured. The absence of proper termination nearby will degrade signal integrity at the sink.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for your inputs...

Can I get the SI analysis reports for the TI AM64B starter kit for reference?

https://www.ti.com/tool/SK-AM64B

Regards,

Parthan

Hello Parthan

Thank you.

Please note that the board level simulations are performed by different simulation teams. Board level simulations have been performed for this EVM.

I do not have a test report to share.

You will have to reach out to the TI sales you are working with to get access to any simulation information that may be available since these are classified as NDA documents.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for your inputs...

We have tried the SI analysis test with the 2 new models available with TI (sprm730d & sprm810)

But we could able to achieve a rise and fall time around 1ns.

Refer below images for reference.

We have 3 RGMII interface on board with routing length approx. 2 inches, 1.6inch and 1 inch and also termination resistors available in the RGMII TX lines. 

We have tried multiple termination values of 0E,10E,22E and 33E, but still couldn't able to achieve rise and fall times below 0.75ns

One more workaround we have done is we have used a different IBIS model from a different SOC family design where same PHY IC was used and with that we could able achieve rise and fall time targets.

Refer below image for reference.

With this observation we feel that the issue might be with the IBIS model only

Based on this we need few clarifications on below:

1) What is the drive strength value currently being used in the IBIS models?

2) Is there any way to increase the drive strength at software side if we require it in board bring up or design validation phase?

3) Is there any other workaround or IBIS models to be tried out in our SI analysis?

Regards,

Parthan

Hello Parthan

Thank you.

Please use the below model for all your simulations 

AM64x SR2.0 IBIS Model