DRA829V: FIFO status

Hello Hasan,

Many of our engineers are OoO for regional holidays at the beginning of next week so please expect delays in response.

Regards,

Josue

Hello,

Sorry for the delay.

Hasan Aarzoo said:

If TXFFE is empty I am sending 64 bytes to TX FIFO (using TX register, 16 sets of 4 bytes). How will I get to know that 64 bytes have been sent to TX FIFO? Which Flag do I have to check for this case?

Expected Used case:

When TXFEE is empty, I want to transmit 64 bytes of data to TX FIFO  (using TX register, 16 sets of 4 bytes) continuously in a while loop and want to exit the function. In the meantime,  shift registers  will transmit
the data from TX FIFO to the slave connected. If I want to transmit the data again to TX FIFO if TXFEE is not empty, I want to see device is busy (or shift registers are busy).

Issue faced:

The data received from TX FIFO to the connected slave is corrupted. I can only see the 1 data byte and last data byte (64th byte) to the slave connected. 

How to make sure the data from the TX FIFO is correctly received at the connected slave. Which flags to check to make sure the uncorrupted transmission of the data ? 

Typically Transmit FIFO Empty (TXFFE) is set, it suggests that at least one of the transmit FIFOs in the system is empty and ready to accept new data.I believe you can use TX0_EMPTY etc..  as this flag/register is set, means that the transmit FIFO 0 is empty and ready to accept new data.

Hasan Aarzoo said:

What does EOT signifies in CH_STAT register? Is it 1 when the TX register unload the 4Bytes data at TX FIFO or When the next set of data id loaded on TX register ?

EOT stands for End of Transmission this is set to 1 automatically at the end of an MCSPI transfer.

Hasan Aarzoo said:

In MCSPI_IRQSTATUS register filed TX0_EMPTY, the description says Transmit register empty. Also in  MCSPI_CHSTAT_0 Register field TXS, the description says channel transmit register. What is he difference between these transmit register ? Which flag is raised when ?

1. TX0_EMPTY : When this flag/register is set, it means that the transmit FIFO 0 is empty and ready to accept new data. It helps in determining whether the FIFO can receive new data for transmission.

2. TXS Register: The TXS register holds the data that is currently being shifted out for transmission. It may contain the data that is being sent out serially from the transmit FIFO to the communication line. 

3. TX_FFE (Transmit FIFO Empty): The Transmit FIFO Empty is a broader indicator that tells the status of all transmit FIFOs within the system. It indicates whether any of the transmit FIFOs in the system, not limited to a specific FIFO like FIFO 0, are empty. When TX_FFE is set, it suggests that at least one of the transmit FIFOs in the system is empty and ready to accept new data.

I hope i have cleared your doubts, please let me know if you have further ?

Regards

Tarun Mukesh

Hi Tarun,

Thank you for the response.

I do have some other question, which are as follows:


1. I tried using TX_EMPTY_0 flag. I checked whether TX_EMPTY is set before before new set of data. Even it that case I didn't see complete data on the connected slave. What might be the reason ? Is there any necessary delay required before the transmission of new data ?  Is there a way to acknowledge whether the data transmitted to TX FIFO or not ?

2. I am using automatic chip select generation feature of Jacinto (TDA4VM). The chip select is de-asserted between MCSPI words transfer. Is there a way to keep chip select asserted between MCSPI word transfers for automatic chip select generation? 
 




Looking forward to hearing back from you.

Best regards,
Hasan

Hello Hasan,

Hasan Aarzoo said:

Thank you for the response.

Thank you.

The FIFO is an automatic buffer. As long as there is data which is currently being sent, the data will be appended to the FIFO for transmission in the order it was written. After the current data is finished transmitting, the next data will automatically be copied into the shift register and start its transmission. The only thing you need to be careful of is that you do not write more data than the FIFO can hold.

The TX_EMPTY_0 flag typically indicates that the transmit FIFO (First-In-First-Out buffer) for a specific channel (in this case, channel 0) is empty and ready to accept new data. However, just relying on the TX_EMPTY_0 flag might not be sufficient to ensure that the data has been completely transmitted and received by the slave.

Hasan Aarzoo said:

• MOA enabled
• master mode
• Single channel enabled for communication
• FORCE: 1
• TURBO: 1
• FIFO enabled for TX only
• TRM: Transmit Mode only
• WL: 7
• SPI Frequency: 50MHz
• Clock divisor: 4096

Transmission Speed vs. Slave Readiness: Even if the FIFO is empty and ready to accept new data (TX_EMPTY_0), the slave device might not be ready to receive the data due to its own processing speed or synchronization issues. There could be a need to ensure the slave is ready before sending new data.

Clock divisor is 4096 so the frequency is around ~12.2 kHz

Timing and Synchronization: Communication protocols often require a certain amount of time between consecutive transmissions to ensure proper synchronization. If new data is sent too quickly after the FIFO becomes empty, it might result in data loss or corruption.

Hardware Constraints: Some hardware might have limitations on how quickly data can be transmitted. Sending data at a rate faster than the hardware can handle might result in issues.

Lack of Acknowledgment: Without acknowledgment from the slave device or without a way to verify that the data has been successfully received, it's challenging to ensure complete transmission.

Hasan Aarzoo said:

I am using automatic chip select generation feature of Jacinto (TDA4VM). The chip select is de-asserted between MCSPI words transfer. Is there a way to keep chip select asserted between MCSPI word transfers for automatic chip select generation? 

The chip-select (CS) timing control is available only in master mode with automatic CS generation (the [0] SINGLE bit set to 0) to add a programmable delay between CS assertion and first clock edge, or CS removal and last clock edge. This option is available only in 4-pin mode when [1] PIN34 set to 0.

Assertion of the SPIEN[i] signals is programmable and can be done manually or automatically. The manual assertion mode is available in single master mode only. SPIEN[i] can be kept active between words with the /1/2/3[20] FORCE bit.

Regards

Tarun Mukesh

Hello Tarun,

first of all thank you for your support.

I'm working together with Hasan and currently he is on vacation. Since the topic is quite urgent for us, I would appreciate if you help me with clarification questions.

Our slave is MRAM and we can read/write without delays with the full speed of SPI interface (up to 40MHz).

The issue which Hasan faced is trying to feed FIFO with less than 64 bytes of data at the full CPU speed (copying data to FIFO without delays, but not more than 64 bytes, so FIFO overflow is impossible). At the same time he monitored the bus with logic analyzed and observed data corruption. This issue was solved by adding some delays before putting new data to FIFO, which is a bit unexpected for us.
So here is the first question: is there any limitation for feeding FIFO, required delays, polling flag etc.?

Another question, which is even more important is automatic CS control. We would like to implement a non-blocking write function for SPI driver which writes up to 64 bytes of data (FIFO size) and asserts CS automatically when the first data is put to FIFO and de-asserts it when FIFO gets empty. We were able to get a picture as above - CS asserts/de-asserts after each byte while FIFO is still not empty (as I mentioned above we feed FIFO without delays, up to 64 bytes of data).
So here is the second question: is it possible to configure McSPI module to have:

• CS automatically asserted as soon as first data is put into FIFO
• CS automatically de-asserted when FIFO gets empty

Manual CS control is not applicable for us cause it would mean that driver function becomes blocking, we would need to stay in the function and wait until transmission is done to de-assert CS.

In simple words we want to have some primitive analogue of DMA, but with a burst size up to 64 bytes.

Thank you in advance for your help.
Dmitry

Hello,

Even though your slave is capable for 40MHz but the SPI clock frequency you are using on master is around ~12.2KHz (Even though the master supports upto 50MHz).It is all about how speed you are transmitting out of FIFO versus the data you are writing into FIFO , you have to ensure there is no mismatch in that so i told to introduce some delay for new data.

For your second question, no it is not possible automatically to de assert after the one FIFO is empty, i believe that's not how it works.

Regards

Tarun Mukesh

Hello Tarun,

thank you for you prompt reply.

Hasan was using 12.2KHz for test purpose only to understand how FIFO is working (incl. feeding FIFO while transmission is ongoing). The desired frequency will be 40MHz.

About CS the news is very bad for us, but thank you for confirming. I just wonder what is the use case for such CS behavior (one byte assertion time), for which slaves was it designed?

I want to make some additional tests next days and if there are still some questions available, I'll create a new thread.

Regards,
Dmitry

Hello,

Sorry , i may have confused you here.

Tarun Mukesh Puvvada said:

For your second question, no it is not possible automatically to de assert after the one FIFO is empty, i believe that's not how it works.

One byte assertion and de assertion is not possible is what i wanted to say.

Let me explain here in detail,

Dmitry Tuykov said:

So here is the second question: is it possible to configure McSPI module to have:

• CS automatically asserted as soon as first data is put into FIFO
• CS automatically de-asserted when FIFO gets empty

As soon as you put data into FIFO then automatically then the CS automatically gets asserted and finally it shall get de asserted only if FIFO is empty but the catch here is the CS bit is also dependent on CLK as well.

If you read the statement from TRM as below ,

The chip-select (CS) timing control is available only in master mode with automatic CS generation (the [0]SINGLE bit set to 0) to add a programmable delay between CS assertion and first clock edge, or CS removal and last clock edge but this option is available only in 4-pin mode when [1] PIN34 set to 0.

This mode is programmable per channel through the /1/2/3[26-25] TCS0 bit field.

Based on number of the clock cycles when CS to get asserted and deasserted can be programmed.

Hope i am clear this time.

Regards

Tarun Mukesh

Hello Tarun,

I've checked other McSPI related threads and honestly think that CS can be automatically triggered only for each word within or without FIFO. If it has to be asserted during multiple words, it can be done only with FORCE.

But if you don't mind I have another question regarding FIFO managing and its statuses.

I've been 'playing' last days with AEL bits in MCSPI_XFERLEVEL register. I cannot explain it, but it works for me only for values below 16. So if I set it to 15, I can really see that TX0_EMPTY is set after ~16 words have been transmitted. But as soon as I set it to higher value (20, 31 etc.) TX0_EMPTY is never set. Preconditions:

• SINGLE = 1
• MOA = 1
• PIN34 = 0
• FFER = 0
• FFEW = 1
• TURBO = 1
• TRM = 2
• WL is 7
• WCNT is different, but let's suppose it is 128

Clock divider was used with different values (incl. 4096) to be sure that FIFO is not getting emptied faster than I filling it in. 

Do you see any ideas why AEL > 15 is not working for me?

Regards,
Dmitry

Hello,

I can share you few details from TRM as you have set MOA=1.

12.1.5.4.6.4 Multiple MCSPI Word Access
The processor has the ability to perform multiple MCSPI word access to the receive or transmit registers within a
single 32-bit interface access by setting the [7] MOA to 1 under specific conditions:
• The channel selected has the FIFO enable.
• Only FIFO sense enabled support the kind of access.
• [7] MOA is set to 1.
• Only 32-bit interface access and data width can be performed to receive or transmit registers, for other kind
of access the processor must de-assert [7] MOA bit.
• The level [7-0] AEL and [15-8] AFL must be 32-bit aligned, it means that AEL[0] = AEL[1] = 1 or AFL[0] =
AFL[1] = 1.
• If [31-16] WCNT is used it must be configured according to MCSPI word length.
• The word length of MCSPI words allows to perform multiple MCSPI access, that means that /1/2/3[11-7] WL
is <16.
The number of MCSPI word access depends on MCSPI word length:
• 3 ≤ WL ≤ 7, MCSPI word length smaller or equal to byte length, 4 MCSPI words accessed per 32-bit interface
read/write. If word count is used ([31-16] WCNT), set the bit field to WCNT[0] = WCNT[1] = 0.
• 8 ≤ WL ≤ 15, MCSPI word length greater than byte or equal to 16-bit length, 2 MCSPI words accessed per
32-bit interface read/write. If word count is used ([31-16] WCNT]), set the bit field to WCNT[0] = 0.

and also,

AEL + 1 must correspond to a multiple value of the WL bit field.

Please got through McSPI module in TRM to get clarity on configuration of Registers.

Regards

Tarun Mukesh

Regards

Tarun Mukesh

Hello Tarun,

I've read this TRM part as well as TRMs for other TI processors with the same McSPI IP and could not find answer on my questions.

Could you please point to a mistake in my configuration or give a hint?

Regards,
Dmitry

Hello ,

If you make MOA=1 , their are certain steps to follow:

The level [7-0] AEL and [15-8] AFL must be 32-bit aligned, it means that AEL[0] = AEL[1] = 1

For Example if you use AEL=20 it is not allowed as it doesn't have AEL[0] = AEL[1] = 1

and 

AEL + 1 must correspond to a multiple value of the WL bit field.

and

For your WL=7,the condition for WCNT need to be met.

3 ≤ WL ≤ 7, MCSPI word length smaller or equal to byte length, 4 MCSPI words accessed per 32-bit interface
read/write. If word count is used ([31-16] WCNT), set the bit field to WCNT[0] = WCNT[1] = 0.

Regards

Tarun Mukesh

Hello Tarun,

I've tried AEL 31, which fulfills 'AEL[0] = AEL[1] = 1'. I've tried 32 as well, just in case.

Tarun Mukesh Puvvada said:

AEL + 1 must correspond to a multiple value of the WL bit field.

This I do not really understand. WL in my case is 7 and of course AEL + 1 = 32 (in my case) is not multiple of 7. But I suppose 'AEL + 1' must be multiple of 'WL + 1', please correct me if I'm wrong.

Tarun Mukesh Puvvada said:

3 ≤ WL ≤ 7, MCSPI word length smaller or equal to byte length, 4 MCSPI words accessed per 32-bit interface
read/write. If word count is used ([31-16] WCNT), set the bit field to WCNT[0] = WCNT[1] = 0.

It is exactly the case, WCNT is 128 in my example above.

So all in all I still do not see an issue.

Hello,

For AEL=31 , it looks fine.

Dmitry Tuykov said:

This I do not really understand. WL in my case is 7 and of course AEL + 1 = 32 (in my case) is not multiple of 7. But I suppose 'AEL + 1' must be multiple of 'WL + 1', please correct me if I'm wrong.

yes .

Is this in DMA mode or non DMA mode ?

and also can you share me the register dump of SPI register when it is working for  AEL <15 and not working scenarion AEL >15

Regards

Tarun Mukesh

and also ,

Is it working if MOA=0 ? Can you please check and let me know ?

Regards

Tarun Mukesh