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How can DM816x VPSS Compositor blend images from 2 graphics pipelines ?

kaiyu zhang
Prodigy 230 points

  Currently we are working on your 816X evaluation board. We are attempting to blend two graphics pipeline outputs together and punch it to HDMI output.

  We are using your software release ti-ezsdk_c6a816x-evm_5_00_00_56, which contains a 2.6.34 kernel. The two graphics layers correspond to /dev/fb0 and /dev/fb1 respectively in linux

  What we encounter currently is : 

 1. /dev/fb1 can not be written to, not like /dev/fb0, unless we create a process that opens /dev/fb1 and keep it unclosed.

2. When we redirect /dev/fb1 output to HDMI through sysfs at  /sys/devices/platform/vpss/graphics1, the HDMI screen can only display contents on /dev/fb1. Whatever we write to /dev/fb0 can not be displayed on the screen.

Our question is how can we truly achieve the blend of /dev/fb0 and /dev/fb1 and make them both appear on HDMI?

Thank you in adavnce !

 

  • 0
    TI__Guru 66120 points

    First, you are using very very old release, I would suggest moving to the latest SDK since they are lots of fixes since 5.00.00.56.

    1. /dev/fb0 and /dev/fb1 are totally independently, none of they can ben written without open first. I do not think you can access /dev/fb0 without open it first, your system may open /dev/fb0 somewhere at the initialization time.

    2. if the image of the /dev/fb1 is the same size of the /dev/fb0, then you will only see one of each since they are totally overlapped.

    Regards,

    yihe

     

  • 0 in reply to yihe
    TI__Guru 66120 points

    Hi, Yihe

    Thank you for your advice. We switched to release 5.01.01.80.  Issue 1 was solved. And we can display images on both /dev/fb0 and /dev/fb1 simultaneously on HDMI.

    There’s still an extended issue though. Actually the feature we are trying to take advantage of  is like this.  We display an image on /dev/fb0. And on /dev/fb1, we display another one on a rectangle that is visually  overlapped against the one on /dev/fb0. On the overlapped region, can your HW/SW achieve some sort of alpha-blending, ie, can we still have a blurred visual of Region1(/dev/fb0) as the background and region2(/dev/fb1) as the foreground image?

    Could you please give us some insight to this issue?

    Thank you so much!

    |---------------------------------------------------|

    |                                                                    |

    |         Region 1(/dev/fb0)                        |

    |                                                                    |

    |                                                                    |

    |                                                                    |

    |                 -------------------------------          |

    |                 |                                         |       |           

    |                 |    Region 2(/dev/fb1)  |      |

    |                 |                                         |      |

    |                 |------------------------------         |

    |                                                                    |

    |-------------------------------------------------- |

  • 0 in reply to yihe
    TI__Guru 66120 points

    VPSS does support this feature to blending two GRPX pipelines into single display.

    1. please change the output destination of /dev/fb1to hdmi since by default /dev/fb1 is connected to the HD_COMP output.

    echo 1:hdmi > /sys/devices/platform/vpss/graphics1/nodes

    2. set the correct priority to choose which GRPX is on top.

    This can be done by set proper priority field inside of ti81xxfb_region_params structure. prioirty:0- lowest.

    3. set alpha blending information of the GRPX pipeline to blend. The blending is done by the following fomula:

    Result = (bottom layer color value)*(1- alpha) + (top layer color value)* alpha

    where alpha is the value of the top layer pixel

     

    VPSS Video user Guide has detail information about these. Please check VPSS Video user Guide

    Regards,

    yihe

  • 0 in reply to yihe
    Prodigy 230 points

    Thank you Yihe.

    We achieved what we need, thanks to your user guide. On the other hand, out of curiosity, does TI provide any user guide on how to talk to VPSS M3 core from the A8 side. Is there any protocol specification illustrating the ways for ARM Cortex A8 to control the VPSS M3?

     

  • 0 in reply to kaiyu zhang
    TI__Guru 66120 points

    TI is actively providing drivers to talk with M3 core from A8 side instead asking customer to this.

    Regards,

    yihe