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DRA829V: PCIe 64bit BAR Memory Access

Swapna yendrapalli
Intellectual 625 points

Part Number: DRA829V

Hi TI Team,

We are using PCIe to interface with FPGA and operating host PCIe in Root port mode.

We are accessing BAR memory and can read 32bit registers OK. 

 

root@dra829-a72:~# k3conf write 0x18114000 0x12341234abcdabcd 

Value at addr 0x18114000 = 0xabcdabcd

 

root@dra829-a72:~# k3conf read 0x18114000
Value at addr 0x18114000 = 0xabcdabcd

root@dra829-a72:~# lspci -v
0000:00:00.0 PCI bridge: Texas Instruments Device b00d (prog-if 00 [Normal decode])
    Flags: bus master, fast devsel, latency 0, IRQ 78
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: [disabled]
    Memory behind bridge: 10100000-101fffff [size=1M]
    Prefetchable memory behind bridge: [disabled]
    Capabilities: [80] Power Management version 3
    Capabilities: [90] MSI: Enable+ Count=1/1 Maskable+ 64bit+
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
    Capabilities: [c0] Express Root Port (Slot+), MSI 00
    Capabilities: [100] Advanced Error Reporting
    Capabilities: [150] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [300] Secondary PCI Express
    Capabilities: [4c0] Virtual Channel
    Capabilities: [5c0] Address Translation Service (ATS)
    Capabilities: [640] Page Request Interface (PRI)
    Capabilities: [900] L1 PM Substates
    Kernel driver in use: pcieport

 

0000:01:00.0 Memory controller: Xilinx Corporation Device 7022
    Subsystem: Xilinx Corporation Device 0007
    Flags: fast devsel, IRQ 255
    Memory at 10100000 (32-bit, non-prefetchable) [disabled] [size=1M]
    Capabilities: [40] Power Management version 3
    Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
    Capabilities: [60] Express Endpoint, MSI 00
    Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00

 

0001:00:00.0 PCI bridge: Texas Instruments Device b00d (prog-if 00 [Normal decode])
    Flags: bus master, fast devsel, latency 0, IRQ 81
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: [disabled]
    Memory behind bridge: 18100000-181fffff [size=1M]
    Prefetchable memory behind bridge: [disabled]
    Capabilities: [80] Power Management version 3
    Capabilities: [90] MSI: Enable+ Count=1/1 Maskable+ 64bit+
    Capabilities: [b0] MSI-X: Enable- Count=1 Masked-
    Capabilities: [c0] Express Root Port (Slot+), MSI 00
    Capabilities: [100] Advanced Error Reporting
    Capabilities: [150] Device Serial Number 00-00-00-00-00-00-00-00
    Capabilities: [300] Secondary PCI Express
    Capabilities: [4c0] Virtual Channel
    Capabilities: [5c0] Address Translation Service (ATS)
    Capabilities: [640] Page Request Interface (PRI)
    Capabilities: [900] L1 PM Substates
    Kernel driver in use: pcieport

AXI bus on FPGA side uses 64bit and we would like to read/write 64bit values. Could you please let us know the  procedure to enable  64bit PCIe read/write access  ?

Thanks,

Swapna

  • +1
    TI__Guru 60563 points

    Hi Swapna,

    I assume the goal of the question is to change below lspci output's "32-bit" to "64-bit":

    Swapna yendrapalli said:
        Memory at 10100000 (32-bit, non-prefetchable) [disabled] [size=1M]

    Can you make sure the Xilinx FPGA is not configured for 32-bit, and instead configured for 64-bit? For example, I found below on Xilinx's documentation for one of their device:

    https://docs.xilinx.com/r/en-US/pg302-qdma/PCIe-BARs-Tab

    Additionally. if it is easy to connect the FPGA to a different device, is it possible to quickly check if the FPGA gets detected by the different device as 64-bit? Mainly, I would like to make sure that this is an issue on TI EVM RC-side, and not an issue on the EP-side before delving deeper.

    Regards,

    Takuma