Other Parts Discussed in Thread: TDA4VH
Hi, TI:
I would like to port the ETHFW Server functionality of the J784S4 EVM to the TDA4VH board of the project. Now I need to configure SGMII1 and SGMII2 on Serdes1, I refer to the Board_CfgSgmii() function in the ti-processor-sdk-rtos-j784s4-evm-09_00_00_02/pdk_j784s4_09_00_00_45/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c. Here is my Serdes initialization function and I have some questions.
static Board_STATUS Board_CfgSgmii_1_2()
{
CSL_SerdesResult result;
CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
CSL_SerdesLaneEnableParams serdesLaneEnableParams1 = {0};
CSL_SerdesLaneEnableParams serdesLaneEnableParams2 = {0};
uint32_t laneNum1 = 2;
uint32_t laneNum2 = 3;
uint32_t IPSel = 0;
memset(&serdesLaneEnableParams1, 0, sizeof(serdesLaneEnableParams1));
memset(&serdesLaneEnableParams2, 0, sizeof(serdesLaneEnableParams2);
/* SGMII Config SerDes1 Lane2 IP1 SGMII1*/
serdesLaneEnableParams1.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
serdesLaneEnableParams1.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
serdesLaneEnableParams1.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLaneEnableParams1.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
serdesLaneEnableParams1.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLaneEnableParams1.numLanes = 1U; // not sure???
serdesLaneEnableParams1.laneMask = 1 << laneNum1; // not sure???
serdesLaneEnableParams1.SSC_mode = CSL_SERDES_NO_SSC;
serdesLaneEnableParams1.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLaneEnableParams1.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLaneEnableParams1.phyInstanceNum = IPSel;
serdesLaneEnableParams1.pcieGenType = CSL_SERDES_PCIE_GEN3;
serdesLaneEnableParams1.laneCtrlRate[2] = CSL_SERDES_LANE_FULL_RATE;
serdesLaneEnableParams1.loopbackMode[2] = CSL_SERDES_LOOPBACK_DISABLED;
/* SGMII Config SerDes1 Lane3 IP1 SGMII2*/
serdesLaneEnableParams2.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
serdesLaneEnableParams2.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
serdesLaneEnableParams2.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLaneEnableParams2.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
serdesLaneEnableParams2.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLaneEnableParams2.numLanes = 1U; // not sure???
serdesLaneEnableParams2.laneMask = 1 << laneNum2; // not sure???
serdesLaneEnableParams2.SSC_mode = CSL_SERDES_NO_SSC;
serdesLaneEnableParams2.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLaneEnableParams2.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLaneEnableParams2.phyInstanceNum = IPSel;
serdesLaneEnableParams2.pcieGenType = CSL_SERDES_PCIE_GEN3;
serdesLaneEnableParams2.laneCtrlRate[3] = CSL_SERDES_LANE_FULL_RATE;
serdesLaneEnableParams2.loopbackMode[3] = CSL_SERDES_LOOPBACK_DISABLED;
CSL_serdesPorReset(CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE); // 1. SerDes1 port reset
/* Select the IP type, IP instance num, Serdes Lane Number */ // 2. set CTRL_MMR_CFG0_SERDESx_LNx_CTRL[1:0],for IPx
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLaneEnableParams1.phyType,
serdesLaneEnableParams1.phyInstanceNum,
serdesLaneEnableParams1.serdesInstance,
laneNum1);
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLaneEnableParams2.phyType,
serdesLaneEnableParams2.phyInstanceNum,
serdesLaneEnableParams2.serdesInstance,
laneNum2);
result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE, // 3. clk
CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE,
CSL_SERDES_REF_CLOCK_100M,
CSL_SERDES_REF_CLOCK_INT0,
CSL_TORRENT_SERDES1,
CSL_SERDES_PHY_TYPE_SGMII);
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Assert PHY reset and disable all lanes */ // 4. Lane_x disable (necessary???)
CSL_serdesDisablePllAndLanes(serdesLaneEnableParams1.baseAddr,
serdesLaneEnableParams1.numLanes,
serdesLaneEnableParams1.laneMask);
CSL_serdesDisablePllAndLanes(serdesLaneEnableParams2.baseAddr,
serdesLaneEnableParams2.numLanes,
serdesLaneEnableParams2.laneMask);
/* Load the Serdes Config File */
result = CSL_serdesEthernetInit(&serdesLaneEnableParams1); // 5. check Params and init serdes
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
result = CSL_serdesEthernetInit(&serdesLaneEnableParams2);
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Common Lane Enable API for lane enable, pll enable etc */
laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams1); // 6. Lane_x enable
if (laneRetVal != 0)
{
return BOARD_FAIL;
}
laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams2);
if (laneRetVal != 0)
{
return BOARD_FAIL;
}
return BOARD_SOK;
}1. The numLanes parameter seems to be only called in CSL_serdesDisablePllAndLanes(). This function is not always used in the Serdes initialization, and the call in the Board_CfgSgmii() does not seem to take effect? Is it necessary in my code?
2. Does the [0-3] bit of the laneMask parameter mean that the current parameter only operates lane0-3. And will the initialization process of my different lanes interfere with each other?
3. If SGMII is connected to 1G and 100M PHY chips, which parameter should be adjusted?
If I have other issues with my initialization function, please point it out.
By the way, what is the function of the bridge initialized in EthFwBoard_configSerdesBridge()(ethfw/utils/board/src/j784s4/board_j784s4_evm.c), in which cases do I need to use it?
Kind Regards
