Hi,
I would like to ask a question on VPBE.
Question 1:
We have registers defining the output region, but there is a question, and I am asking only the horizontal part for simplicity:
1. HINT+1 defines the length of each line
2. In both figure 25 and 47, it is clearly seen that HSTART + HVALID < HINT+1. What is the region (shown in red hatch)
(1) After HVALID
(2) Before next HSYNC
called? Is it something like a "back porch"?
Question 2:
How long does HSYNC need to be? For HSYNC signal, is it that only its rising edge matter, or the entire duration when it is high matter, or it is its falling edge that matter?
What happens if HSYNC>HSTART? This means that before the falling edge of HSYNC, LCD_OE already becomes 1 and effective data are being output right now despite high VSYNC signal. Would the video output data be effective at this time, or video output would only become effective after HSYNC's falling edge?
Zheng
