TDA4VH-Q1: C71 MAIR register attribute definition

li quan

Part Number: TDA4VH-Q1

Hi experts:

Is the MAIR register definition in C71 MMU the same as the definition in ARMv8? The value of the Mmu_MAIR4 variable in pdk_j784s4_08_06_00_31/packages/ti/csl/arch/c7x/src/mmu.c is initialized to 0x44, which corresponds to the no cache attribute( Normal memory, Inner &Outer Non-cacheable) if parsed according to ARMv8.

However, if you follow the MAR register analysis in the TI manual, it is the device memory(0x44 , 01000100b), which cannot correspond to the actual firmware configuration attributes.

MAIR initialize code:

Mmu_setMAIRAsm(4, Mmu_MAIR4);

-->

Mmu_setMAIRAsm
; .asmfunc

shld.l1 a4, 3, a4
shld.l1 a5, a4, a5
mvk64.l1 0xff, a6
mvc.s1 MAR_S, a7
shld.l1 a6, a4, a6
andnd.l1 a6, a7, a4
ord.l1 a4, a5, a4
mvc.s1 a4, MAR_S
mvc.s1 a4, MAR
|| ret.b1

over 1 year ago

0 Praveen Rao over 1 year ago

TI__Mastermind 47983 points

Hello,

li quan said:
Is the MAIR register definition in C71 MMU the same as the definition in ARMv8?

Both use the arm large descriptor format for MMU, but bit description are not the same.

Regarding your second query on why the value is 0x44 for MAIR4, I'll have to check internally and get back to you.

Thanks.

0 li quan over 1 year ago in reply to Praveen Rao

Intellectual 955 points

Thanks for your reply. Looking forward to your further information.

+1 Praveen Rao over 1 year ago in reply to li quan

TI__Mastermind 47983 points

Hello Li,

As per the response that we received from Dev team, the software is placing the IPC VRing buffers in the region 4, which is why this region needs to be non-cacheable, and hence the MAIR of 0x44.

Also, as per the TI manual, when sharing page table entry b/n ARM and C7x, the CMMU MAR register must match the ARM's MAIR.

Hope this clarifies.

Thanks.

Processors

Processors forum

TDA4VH-Q1: C71 MAIR register attribute definition