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EDMA use in mpeg4 encoder

Geoff
Prodigy 195 points
Other Parts Discussed in Thread: TMS320DM647

We are using mpeg4 encoder

Id:MP4VENC_TI Ver:1.21.005 Released by:DEV_100_V_MPEG4_E_1_21_005 Built:Feb 24 2009 05:36:04

In the supplied app/Client/Test/Src/TestAppEncoder.c there are the following comments

********************************************************************************
  @file     TestAppEncoder.c
  @brief    This is the top level client file that drives the MPEG4 Encoder
            (Baseline Profile) Video Encoder Call using XDM Interface
  @author   Multimedia Codecs TI India
  @version  0.0 - Jan 24,2006    initial version
********************************************************************************

    /* Sample Configuration of  QDMA properties                               */

    /* Associating the four QDMA channels (0,1,2,3,4,5) to Queues             */
    
    /*Note: The following code is Commented because, for this release, the    */
    /*queue assigment is done inside the algorithm library.                   */
    /*In this release following is the Q allocation used:                     */
    /* Q2/TC2: is used for write to DDR
    /* Q3/TC3: is used to read from DDR
    /* Q1/TC1: is used to write to DDR from sequencer (The codec traffic on   */
    /* this TC will be  very less, But it is required because we cannot use   */
    /* TC3 for  transfers from sequencer memory).                             */
    /* Q0/TC0 : DDR read to seq. memory                                       */

    /* Commented: see the commentes above **************************************
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 0)));
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 1)));
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 2)));
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 3)));
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 4)));
      *QDMAQNUM = ((*QDMAQNUM) | (0x1 << (4 * 5)));*/
    /*****************************************************************************
    /* Setting lowest priority to Queue 3 and equal priorities to other       */
    /* queues.                                                                */
    *QUEPRI   = (0x7 << 12) | (0x3 << 8) | (0x3 << 4) | (0x3);

Please confirm that this comment in the test app accurately matches the actual library usage.

We are trying to meet the requirements of SPRZ263F (TMS320DM647/DM648 Digital Media Processors Silicon Errata) to avoid deadlock in the following advisory...

Advisory 1.1.5 —SDMA/IDMA: When DSP Level 2 memory is configured as non-cache (RAM), unexpected blocking and
potential deadlock condition may occur

 

  • 0
    TI__Guru* 84110 points

    The best way to answer this question would be to run the code, then stop it using CCS and look at the QUEPRI register to see what is in it.

    If you have re-built the library, then it will use the QUEPRI line as shown. it would be an error in the library if the library did not match the source files provided. But there could also be other code you have written to initialize the EDMA3 module which overwrites this register.

    We will have this thread moved to the Embedded Software - Multimedia Software Codecs forum where the codec experts work.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 195 points

    Thanks for the reply Randy. It is my understanding of the requirement in the errata that writes to L2 and writes to DDR2 are not performed by the same TC. Can I determine that from CCS? I think that would have to be determined from the code? Even after seeing the state of the QUEPRI we would need to know the priority used for the transfers triggered by the encoder to work our which TC was being used.

    Geoff

  • 0 in reply to Geoff
    TI__Guru* 84110 points

    No, I misunderstood the question. I understand the EDMA3 hardware and saw immediately above your bold-font question there was a comment on QUEPRI.

    This codec forum is where to find support for the software. If there is anyone who can document the fact that the documentation is correct, they would be here.

    Sorry for the confusion on my part.

    Regards,
    RandyP

  • 0
    TI__Prodigy 220 points

    Hi Geoff,

    Looks like the comments are not up to date. Following is what is used by the codec version 1_21_005:

    TC0 : is used for any traffic(writes) TO  GEM (traffic from DDR to GEM and DDR to seq memory)

    TC1: is used for any traffic(writes) TO DDR(traffic from GEM to DDR and sequencer memory to DDR)

    (The other two TC's are not used by codec).

    And the QUEPRI register need to be programmed by the app (to set the que priorities, example is the uncommented code in the testapp for *QUEPRI)

    Regards,

    Keshav