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C6474 Timer Interrupt gets delayed

Suchita Sahu
Prodigy 30 points


 

Hi,

I am running C6474 on a custom board. I have noticed that when three large ethernet packets (1500 bytes each) are sent to the DSP, the timer interrupt gets delayed by approximately 300usec. This is consistent and reproducible. The timer interrupt has higher priority than the Rx and Tx interrupts and is configured using BIOS. The application code is disabled for this test.

One explanation of this behavior would be that the timer interrupt gets disabled while the ethernet interrupt is being serviced but I cannot find the code where that is being done. I have tried looking at the ndk 2.0 source files but do not see any place where interrupts are being disabled. Also, there are no exceptions, so the DSP is not interrupted by the NMI. The interrupts which have the higher priority than the timer are Reset, NMI and RTDX_poll.

Any suggestions on why this might happen? Does the EMAC DMA engine disable the interrupts like the EDMA?

I am using CCS 3.3.82.13 and BIOS version 5.41.10.36. Please let me know if more information is needed.

Thanks,

Suchita.

 

  • 0
    TI__Guru* 84110 points

    Suchita,

    In the TI Wiki Pages, you can click on the Training link and find online training materials for the C6000 with BIOS. The online materials include the information provided to BIOS through the GUI to configure interrupts. One part of the configuration is the Mask parameter which determines which other interrupts will be allowed to interrupt the one being configured.

    Also, in the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review some or all of the modules. You can find the complete video set at http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=OLT110002

    It is our recommended practice to only execute a minimum amount of code in any HWI ISR, but to post a SWI or SEM to continue the algorithm initiated by the interrupt. This is explained in the online training material from the Wiki.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Prodigy 30 points

    Hi Randy,

    Thanks for your reply. I have already verified if the interrupts are setup correctly and also tried using the bitmask to mask all the interrupts except the NMI and reset.

    I have tried another approach. I started a continuous ping to the DSP with packet size of 1500 bytes and I noticed that after a few seconds the timer interrupt gets delayed by around 300usec, this does not happen with normal sized (64 bytes) ping to the DSP.

    Suchita.

  • 0 in reply to Suchita Sahu
    TI__Guru* 84110 points

    Suchita,

    What are you executing in your ISRs? Have you followed the "minimum code in ISR" recommendation above?

    I am not clear about the two interrupts, but for the lower priority interrupt (not the timer interrupt) you should mask all the interrupts except the NMI and reset and timer interrupt. This will allow the timer interrupt to run while the other interrupt is also running.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 30 points

     

    Randy,

    The ISR code is very simple, a few if statements for counters and a SEM_POST to Timer Task.

    I have tried playing with the interrupt masks and interrupt bitmasks for lower priority interrupts but it does not seem to make a difference, the timer interrupt still gets delayed.

    Thanks,

    Suchita.

  • 0 in reply to Suchita Sahu
    TI__Guru* 84110 points

    Suchita,

    What do you execute in the Rx and Tx interrupts?

    Your original question was how the timer interrupt may be disabled. Do you understand how that occurs now? And do you understand how to enable it during the Rx and Tx interrupts?

    Regards,
    RandyP