C6455 SRIO endianess.

wish_best said:

both the dsp and fpga are working on [little] endian.

This is a very common method. SRIO works well in this configuration.

wish_best said:

The data 0x01020304 05060708 which is in the fpga becomes 0x08070605 04030201 in the dsp.

Why do you mention this? Have you built the system and observed this, or are you speculating on this? My experience has been that the data sent is the same as the data received when going from LE to LE machines. I do not have hardware to test this on, but that is the result we documented many years ago.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

I think the FPGA is causing the problem by converting the data to solve a problem that does not exist. If the FPGA does not convert the data, then the data would land correctly on the DSP.

If the data being sent is not a multiple of 4 bytes in length or if the source or destination address is not a multiple of 4 bytes, then the SRIO's endianness could have an effect on the results. But that effect would be predictable.

Here are test results transferring data over SRIO between 2 C6455s with both configured for the same endianness:

DSP1 LE-to-DSP2 LE

node1 (source, LE), Data stored in node1

0x00810000: 0x11223344
0x00810004: 0x55667788
0x00810008: 0x99AABBCC

node2 (dst addr 0x00800000, LE), Data stored in node2 for 3 bytes transfer

0x00800000: 0xxx223344
0x00800004: 0xxxxxxxxx
0x00800008: 0xxxxxxxxx

node2 (dst addr 0x00800102, LE), Data stored in node2 for 8 bytes transfer

0x00800100: 0x3344xxxx
0x00800104: 0x77881122
0x00800108: 0xxxxx5566

or if viewed as LE starting at an offset of 2

0x00800102: 0x11223344
0x00800106: 0x55667788
0x0080010A: 0xxxxxxxxx

DSP1 BE-to-DSP2 BE:

node1 (source, BE), Data stored in node1

0x00810000: 0x11223344
0x00810004: 0x55667788
0x00810008: 0x99AABBCC

node2 (dst addr 0x00800000, BE), Data stored in node2 for 3 bytes transfer

0x00800000: 0x112233xx
0x00800004: 0xxxxxxxxx
0x00800008: 0xxxxxxxxx

node2 (dst addr 0x00800102, BE), Data stored in node2 for 8 bytes transfer

0x00800100: 0xxxxx1122
0x00800104: 0x33445566
0x00800108: 0x7788xxxx

or if viewed as BE starting at an offset of 2

0x00800102: 0x11223344
0x00800106: 0x55667788
0x0080010A: 0xxxxxxxxx

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

In my case,I need to transfer the video data from fpga to dsp in 50HZ.So I need to convert the data in the dsp as quickly as possible.Then I can deal with it.If the hardware of the dsp can't do it as I want.Is there any other good ways to solve this problem?And it should be in high efficient.

Yes. Do not convert the data in the FPGA. Then the DSP will not have to do anything. That is maximum efficiency.

You do not want the DSP to have to do work to counteract the wrong correction / conversion being done in the FPGA. Simply change the FPGA so it does not do the conversion.

Is this an acceptable solution?

Regards,
RandyP

Hi RandyP:

I have consider it before.But the convert in the FPGA is done through the hardware.And I can't change it as i want.As the result of it,I need to convert it in the dsp.But I find that the normal c language will take a lot of time to do it.Is there any other method that will be higher efficient?

The FPGA is the right place to fix this or to un-break this. The efficiency is 0 MIPS required by the DSP.

How much time does the normal C language take?
How much data do you need to convert?
How fast do you need it to be?

Do you always transfer data in multiples of 64-bits with double-word big endianness?
Do you want to convert that to double-word little endianness?

Regards,
RandyP

Now it costs 4ms to convert it in the dsp.I think it will meet my requirement.But I think that,if I don't need to convert it by software.It will be better.

Do you always transfer data in multiples of 64-bits with double-word big endianness?
Do you want to convert that to double-word little endianness?

Yes,the fpga always transfer data in multiples of 64-bits with double-word.

I want to convert it to double-word little endianness.

Regards,

Wish.

Wish,

It is good that you will meet your requirement. For your purposes, I am sorry that you are unable to change the FPGA's logic.

What size is the frame of data that you convert? 4ms = 4,000,000 CPU cycles on a 1GHz C6455, and that is a lot of CPU cycles.

Regards,
RandyP

Hi RandyP:

I'm very sorry for replying you until now.I have been very busy before.

Now I place the data in the L2 RAM of the C6455 dsp.And it takes 0.22ms each time.And I the size of data that I convert is 640KByte each time.But when I put the data in the ddr2,it costs 7.8ms.I consider that my ddr2 doesn't work well.But I connot find the reason.

The clk2 is 25MHZ.According to the documents of C645X DDR2.The clk2output of ddr2 is 250MHZ.And I configure the data rate 500MHZ.

Is there any thing that I have missing?

Wish,

wish_best said:

Now I place the data in the L2 RAM of the C6455 dsp.And it takes 0.22ms each time.And I the size of data that I convert is 640KByte each time.

This is very good speed for that much data. How do you do the conversion that fast?

wish_best said:

But when I put the data in the ddr2,it costs 7.8ms.I consider that my ddr2 doesn't work well.But I connot find the reason.

Do you have cache enabled and the MAR bits set to 1? DDR2 is slower than L2.

It is faster to use QDMA to move blocks of data into L2, use the CPU to process the data, then use QDMA to move the results back to DDR2. The best technique is to have the QDMA copying to/from ping/pong buffers while the DSP is processing the opposite buffers.

Regards,
RandyP

I put the data in the L2,and use the C64x+ little endian library.There is a function in this lib for me to convert the data in 64bits.

Not only the convert in the ddr2 is very slow.But other process which is done in the ddr2 is the same.I know the ddr2 is slower than L2.But I think it should not be so slowly.It costs about 30 multiple times than L2.

RandyP said:

Do you have cache enabled and the MAR bits set to 1?

What are your cache settings?

wish_best said:

It costs about 30 multiple times than L2.

This may not be as far from reality as you think. The CPU is not very efficient when accessing external memory. This is why the EDMA3 is such a powerful tool for you.

Regards,
RandyP

I just use the DSP/BIOS.And there are two L1 caches for data or code.

Is there anything others that I shoud do?

Hi RandyP:

Thanks for your help.I have solve the problem.As you said,it is the problem of the cache.

Regards,

Wish

I have met some problems about srio transfer.Can you take some time to see my question in another thread?

Question about C6455 Srio transfer.

Thank you very much.