TDA4VM: When the MCU establishes IPC communication with A72, the code execution time of the MCU will become longer.

Hello,

On which core are you running the SPI and IPC tasks ? Are you using AUTOSAR OS ? 

one reason can be the task Priority of IPC might be higher than that of SPI and R5 -IPC is blocked at receiving fn.

Regards

Tarun Mukesh

Hello,

KONG XIANGXU said:

I tested the code execution time of the Spi_ AsycTransmit has been extended from 70us to 80us when I run the IPC communication

What does this exactly mean ? the execution time means to start the transmission of data it changed form 70 to 80us ?

KONG XIANGXU said:

. I test that SPI tasks will not be interrupted by IPC tasks

Interrupt Handling: IPC involve interrupts driven mechanisms. When the MCU communicates with the A72 core, it could be handling interrupts more frequently or dealing with interrupt prioritization, which could impact the timing and execution of its code.

Resource Sharing: IPC might require sharing resources like memory between the MCU and the A72 core. This sharing can lead to contention or delays as both cores access these shared resources.

Context Switching Overheads: When switching between tasks or handling IPC-related operations, there could be additional overhead associated with context switching. This involves saving and restoring the state of the processor, which takes time.

Regards

Tarun Mukesh

Hi, TI

1、I mean code execution time。

2、IPC in MCU 1_ 0 and A72 share the same DDR memory. Can you tell me why this sharing can lead to contention or delays as both cores access these shared resource？

3、Will it occupy DDR bandwidth during IPC communication, resulting in longer MCU code execution time？

Hello,

If there is data transfer happening between MCU1_0 and A72 DDR shared memory will be used , one core has to write data into common space and after that i triggers an interrupt on another core (which will be waiting ) then it fetches the data from shared memory of DDR. 

Yes DDR bandwidth is also in the picture , as you are using DMA and also IPC using DDR for shared memory then it can cause latency.

Regards

Tarun Mukesh 

Hi, TI

May I ask if there is any way to reduce this delay？

Hello Kong Xiangxu,

As i said in another E2E thread as well, we have only few options to reduce this delay by some number to avoid DDR latency

1.Is to ensure the code in DDR is cacheable ? 

2.Shift the .textsection to internal memory of MCU_SRAM or MAIN_SRAM based on the size of the code.

Regards

Tarun Mukesh