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TDA4VM: Interrupt Aggregators and Ring Accelerators Sysconfig Setting

Kevin Peng
Expert 3772 points
Part Number: TDA4VM
Other Parts Discussed in Thread: SYSCONFIG

Hi TI Experts,

Customer is working on TDA4VM SDK8.6.

The reason for posing this thread is that when we implement the PDMA of SPI on MCU1_1 with the default sysconfig setting, we found there is some problem.

After some debugging, we found the reason is that the MCU NAVSS interrupt aggregator virtual interrupts count is just 4 in the default sysconfig setting. When we increase this setting to 24, the MCU1_1 could run SPI PDMA successfully.

Based on this experiment result, we have done some research about the interrupt aggregator, and there is a very helpful introduction in the below link.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/931985/faq-tda4vm-routing-interrupts-via-the-interrupt-router

Apart from this, we also see there is default setting of MAIN NAVSS interrupt aggregator for a MCU core shown below.

As we can see that the default Main NAVSS UDMA Interrupt aggregator virtual interrupts count is 0, the Main NAVSS UDMA Interrupt aggregator global event count is 32 for MCU1_0 sysconfig default setting. I know this setting does not affect our current applications so far, but just to prepare for the future applications, we may need to make sure if the default values here is sufficient or not.

We are not very clear about the functions of Main NAVSS UDMA Interrupt aggregator virtual interrupts count & Main NAVSS UDMA Interrupt aggregator global event count respectively for a MCU core. May I know in which scenario, we may need these settings for a MCU core please?

The second question is that, we see there is also default sysconfig setting of MCU NAVSS ring accelerator below.

We also find there is some explanation of ring accelerator in the below link.

https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_ra.html

However, we are still confused about the values of the ring accelerator setting. If there is any guide on how to set these values would be very appreciated!

Kind Regards,

Kevin

  • 0
    TI__Mastermind 42135 points

    Hi Kevin,

    The assigned engineer is OoO till Nov-21, please expect a delay in response.

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    TI__Guru* 77774 points

    Hi Kevin

    I also need to run this by the team, I will check and respond back tomorrow.

    Regards

    Karan

  • 0 in reply to Karan Saxena
    TI__Guru* 77774 points

    Kevin

    Kevin Peng said:
    After some debugging, we found the reason is that the MCU NAVSS interrupt aggregator virtual interrupts count is just 4 in the default sysconfig setting. When we increase this setting to 24, the MCU1_1 could run SPI PDMA successfully.

    I checked this with the team, increase in the number of virtual interrupts is needed only when you are not using shared events by setting eventPrms.eventMode = UDMA_EVENT_MODE_SHARED;

    The default SDK has this configuration, was this changed by your customer? If there are any modifications, can you please share them?

    Regards

    Karan

  • 0 in reply to Karan Saxena
    TI__Expert 3772 points

    Hi Karan,

    Thanks for the reply!

    We have checked customer's code that eventPrms.eventMode = UDMA_EVENT_MODE_SHARED is not changed shown below.

    We have not done code by code difference checking, but customers are completely following the default PDK for their applications. Let me describe more details below.

    During the initialization stage of MCU1_1 SPI PDMA, the experiment result shows that there will be 3 calls for VINTR allocations. And by default the VINTR count is 4, for the first 2 calls of VINTR allocations there will be no problem as shown from the below log. But for the third time VINTR allocation, it will have VINTR allocation failed log.

    After changing the default VINTR count from 4 to 24, this problem can be resolved.

    May I know ideally, when UDMA_EVENT_MODE_SHARED is enabled, MCU1_1 could use the resources from other cores right? I am not sure if anything else gets wrong so in my customer's case this still not working with UDMA_EVENT_MODE_SHARED enabled.

    Increasing VINTR count could be a reference for other customers to have a try if they have similar problems. 

    We currently could use it as a workaround for my customer's case, and we have another two questions which have been described in this thread, and hope to have a more clear theoretical understanding.

    1: We are not very clear about the functions of Main NAVSS UDMA Interrupt aggregator virtual interrupts count & Main NAVSS UDMA Interrupt aggregator global event count respectively for a MCU core. May I know in which scenario, we may need these settings for a MCU core please?

    2: We are confused about the values of the NAVSS ring accelerator setting. If there is any guide on how to set these values would be very appreciated!

    Thanks a lot,

    Kevin

  • 0 in reply to Kevin Peng
    TI__Guru* 77774 points

    Kevin

    As I understand you had this discussion with Brijesh as well. Let me discuss with him and then respond back here.

    Regards

    Karan