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Viewable in IE: How to sync between VPFE and VPBE’s different video frame rates?

Anonymous
Anonymous

 

Hi,

 

I would like to ask a question on synchronization between VPBE and VPFE.

 

What if the input frame rate of VPFE input and output frame of VPBE are different? For example, it is very common that an image sensor has frame of 30 frame/sec, but for VPBE interfacing with LCD the typical frame rate could be 60 frame/sec. Therefore, within every 1/30 second there is one frame in, but two frames needs to be output to LCD.

 

If VPBE.OSD has a video window, say video 0, whose source is VPFE input, then how is video 0 updated? Should it be updated every 1/30 second according to input frame rate, or every 1/60 second according to output rate?

 

Further, what if the ratio between output and input frame rate are not whole integers? It is also common for image sensor to have 25fps input rate while LCD has 60fps rate, between which the ratio is 60:25=2.4, how does the synchronization work in this case?

 

 

There are two pieces of information I notice that might have relation to this synchronization problem:

1.    For VPFE, there are interrupts indicating end-of-frame events.

2.    For VPBE, there are as many as four clock sources for VPBE.VENC, including PCLK which is VPFE's input clock.

 

So should VPFE.PCLK be used here? If it is used, although at the first glance there seems to be an apparently simple synchronization mechanism PCLK affords, if we think in more detail the case might not be as simple as expected. Because:

1.    VPFE.PCLK is pixel level sync clock, not frame level clock. Frame sync signal VSYNC is either separately provided or embedded in video signal if the input stream if ITU/BT.656.

2.    Interrupt events VDINT0 and VDINT1, perhaps also some others, are already capable effectively communicating the end-of-frame information.

 

Therefore, I am very curious in knowing the purpose of allowing PCLK to be VPBE.VENC's clock input. What is the purpose of this design? And how could it address the frame synchronization between arose due to different input/output frame for video stream?

 

Besides VPFE.PCLK, does other three clock sources (PLLC1, PLL2, VPBECLK) of VPBE help? In detail, how?

 

 

 

 

Thanks,

Zheng

 

  • 0
    TI__Genius 14405 points

    Zheng,

    1. 30fps in, 60 fps out, you can simply display each input frame twice.

    2. regarding 24fps in, 60 fps out, consider "pulldown", explained here http://www.zerocut.com/tech/pulldown.html

    The EOF events are definitely helpful here, and should be used.

    Do the input clock and output clock have the same frequency? PCLK is only useful when you want to synchronize the pixel of input and output, and that they have the same rate. I don't think this is what you are doing. My impression is that you are only trying to synchronize the input and output video stream.

  • Anonymous
    0 Anonymous in reply to Paul.Yin

    Paul,

    Thanks for the link. I found this topic is also discussed in http://en.wikipedia.org/wiki/Telecine.

    My question now goes to the implementation of pulling-down on TI devices. The basic idea of pulling-down are simple, and can be easily modified to accommodate frame rates other than NTSC/PAL.

    However, a key characteristic of pulling-down method is:

     

    Format

    Input (cinema films)

    Progressive

    Output

    Interlaced

    Video on parallel RGB LCD are usually not interlaced. Therefore, there are two questions follows:

    1. How to adapt pull-down technique to parallel RGB LCD output? Is it the preferred technique for displaying video on LCD screen, or there are better alternative methods?
    2. Does DM6437/OMAP L138 provide hardware support for pulling-down or related techniques?



    Zheng