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AM69: please details on memory available for each DSP

Colombo Carlo
Mastermind 24120 points
Part Number: AM69

Hi everybody , 

I  need some clarification on memory availble to DSP .

I see in TRM   SPRUJ52C document there is a drawing on page 419 :   figure 6.1    in section 6.1.1 Compute Cluster Overview   

there is a mention for 3MB  sram  :  coudl you a little elaborate if it is out of the total 8MB ?  is it for DSPx  ?

So there is 3MB of SRAM, but I didn’t find any information about what we can do with it, it is only SRAM accessible by the DSP? A part of it can be configured as cache? It is 3MB for each DSP not 3MB shared by all DSP?

There is also a MSMC2  : 

For this one I didn’t find any information what is its function, it just manages the coherence of DSP caches?

thank you 

BR

Carlo

  • 0
    TI__Guru**** 163280 points

    Hi Carlo,

    I am looping in expert on this. We will get back to you on this.

    Best Regards,

    Keerthy 

  • +1
    TI__Guru* 85196 points

    Hi Colombo,

    Colombo Carlo said:
    there is a mention for 3MB  sram  :  coudl you a little elaborate if it is out of the total 8MB ?  is it for DSPx  ?

    There is a local MSMC for each C7x core in AM69. The 3 MB MSMC1 corresponds to that.

    The 8MB Common MSMC3 corresponds to a common MSMC region across the cores.

    Colombo Carlo said:

    There is also a MSMC2  : 

    For this one I didn’t find any information what is its function, it just manages the coherence of DSP caches?

    The MSMC2 is not a physical memory, but it is an interconnect from MSMC1 to MSMC3 and also across the MSMC1 among the C7x cores.

    Regards,

    Nikhil