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TDA4VM: I would like to know how MSMC Interconnect checks for errors.

yanggc
Intellectual 470 points
Part Number: TDA4VM

Hello,

I would like to ask a question about MSMC:

The document  "SPRUIR1-DRA829_TDA4VM_Safety_ManualF5_draft_Auto.pdf" states that the MSMC3.INT4- Error codes for invalid transactions feature is already enabled by default, so:

1. How can I proactively insert invalid bus transactions to trigger an error?

2. How can I obtain the error message after triggering it? Are there registers with storage errors available for reading and writing? Will it still trigger certain interrupts?

  • +1
    TI__Mastermind 41636 points

    Hi,

    A bus error will occur if a transaction fails on the interconnect. The way this error is dealt with on the originating core depends on the core itself. For instance, the A72 QNX core would probably produce a SIGBUS signal. To test this, you could try reading a module that is not clocked or powered.

    The application being run, will define what type of traffic is flowing through MSMC interconnect. For the MSMC3.INT4, recovery mechanisms could be made available to report this to CPU and retry that particular transaction.

    Regards,

    Josiitaa