I am using AM3359 Sitara Processor in the design. DDR3L of 1GB density with data lines of x16 is interfaced. It has two I2C, UART and SPI interface and GPMC is used to communicate with NAND Flash, NOR Flash and FPGA (16-bit). It has 1Gbps RGMII Ethernet interface as well. Kindly verify the Power Estimation Excel for the following configuration. As the VDDS_DDR is less than 10mA. Is there any settings, am I missing?
Is it okay to use independent Switching Regulators instead of PMIC? Is it okay to combine VDDS_RTC and VDD_CORE?
Is there any voltage restrictions for the particular operating speed, Like 1Gbps Ethernet shall operate in 1V8 voltage mode not in 3V3 mode?