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TDA4VM: Enable MCU1_0 and MCU3_0 base on vision_apps demo

Part Number: TDA4VM

Hi,experts

       we want to add application on MCU1_0 to make TDA4 work on MCU-only mode base on vision apps demo. Now we try to enable MCU1_0 and MCU3_0 in vision_apps.

1. ../ti-processor-sdk-rtos-j721e-evm-08_06_00_12/vision_apps/platform/j721e/rtos/common/app_cfg.h

 - //#define ENABLE_IPC_MCU1_0

#define ENABLE_IPC_MCU1_0

 - //#define ENABLE_IPC_MCU3_0

#define ENABLE_IPC_MCU3_0

 - //#define ENABLE_IPC_MCU3_1

#define ENABLE_IPC_MCU3_1

2. ../ti-processor-sdk-rtos-j721e-evm-08_06_00_12/vision_apps/vision_apps_build_flags.mak
- BUILD_CPU_MCU1_0?=no
- BUILD_CPU_MCU3_0?=no
- BUILD_CPU_MCU3_1?=no

+ BUILD_CPU_MCU1_0?=yes
+ BUILD_CPU_MCU3_0?=yes
+ BUILD_CPU_MCU3_1?=yes

3. rebulid PDK and vision_apps

4.make linux_fs_install_sd

In this step need copy  tispl.bin and u-boot.ing from  ../ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/u-boot-2021.01+gitAUTOINC+62a9e51344-g62a9e51344/ j721e-arm64-linux. We didn't perform the operation,whether this makes a difference?

5.source /opt/vision_apps,the log as follows:

root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]      9.633340 s: CIO: Init ... Done !!!
[MCU2_0]      9.633402 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      9.633449 s: CPU is running FreeRTOS
[MCU2_0]      9.633476 s: APP: Init ... !!!
[MCU2_0]      9.633502 s: SCICLIENT: Init ... !!!
[MCU2_0]      9.633757 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]      9.633805 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]      9.633839 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      9.633878 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      9.633906 s: UDMA: Init ... !!!
[MCU2_0]      9.635198 s: UDMA: Init ... Done !!!
[MCU2_0]      9.635262 s: MEM: Init ... !!!
[MCU2_0]      9.635311 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
[MCU2_0]      9.635393 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]      9.635458 s: MEM: Init ... Done !!!
[MCU2_0]      9.635485 s: IPC: Init ... !!!
[MCU2_0]      9.635551 s: IPC: 9 CPUs participating in IPC !!!
[MCU2_0]      9.635610 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     20.075784 s: IPC: HLOS is ready !!!
[MCU2_0]     20.099479 s: IPC: Init ... Done !!!
[MCU2_0]     20.099546 s: APP: Syncing with 8 CPUs ... !!!
[MCU2_1]      9.577609 s: CIO: Init ... Done !!!
[MCU2_1]      9.577670 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      9.577714 s: CPU is running FreeRTOS
[MCU2_1]      9.577742 s: APP: Init ... !!!
[MCU2_1]      9.577767 s: SCICLIENT: Init ... !!!
[MCU2_1]      9.578015 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      9.578086 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      9.578131 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      9.578172 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      9.578202 s: UDMA: Init ... !!!
[MCU2_1]      9.579661 s: UDMA: Init ... Done !!!
[MCU2_1]      9.579727 s: MEM: Init ... !!!
[MCU2_1]      9.579772 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      9.579844 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      9.579906 s: MEM: Init ... Done !!!
[MCU2_1]      9.579934 s: IPC: Init ... !!!
[MCU2_1]      9.580000 s: IPC: 9 CPUs participating in IPC !!!
[MCU2_1]      9.580054 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     20.186956 s: IPC: HLOS is ready !!!
[MCU2_1]     20.210420 s: IPC: Init ... Done !!!
[MCU2_1]     20.210487 s: APP: Syncing with 8 CPUs ... !!!
[MCU3_0]      9.608650 s: CIO: Init ... Done !!!
[MCU3_0]      9.608726 s: ### CPU Frequency = 1000000000 Hz
[MCU3_0]      9.608771 s: CPU is running FreeRTOS
[MCU3_0]      9.608799 s: APP: Init ... !!!
[MCU3_0]      9.608825 s: SCICLIENT: Init ... !!!
[MCU3_0]      9.609100 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_0]      9.609174 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_0]      9.609213 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_0]      9.609254 s: SCICLIENT: Init ... Done !!!
[MCU3_0]      9.609284 s: MEM: Init ... !!!
[MCU3_0]      9.609324 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db000000 of size 8388608 bytes !!!
[MCU3_0]      9.609394 s: MEM: Init ... Done !!!
[MCU3_0]      9.609422 s: IPC: Init ... !!!
[MCU3_0]      9.609483 s: IPC: 9 CPUs participating in IPC !!!
[MCU3_0]      9.609538 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_0]     20.384417 s: IPC: HLOS is ready !!!
[MCU3_0]     20.408050 s: IPC: Init ... Done !!!
[MCU3_0]     20.408134 s: APP: Syncing with 8 CPUs ... !!!
[MCU3_1]      9.641889 s: CIO: Init ... Done !!!
[MCU3_1]      9.641960 s: ### CPU Frequency = 1000000000 Hz
[MCU3_1]      9.642007 s: CPU is running FreeRTOS
[MCU3_1]      9.642036 s: APP: Init ... !!!
[MCU3_1]      9.642062 s: SCICLIENT: Init ... !!!
[MCU3_1]      9.642315 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU3_1]      9.642367 s: SCICLIENT: DMSC FW revision 0x8  
[MCU3_1]      9.642417 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU3_1]      9.642461 s: SCICLIENT: Init ... Done !!!
[MCU3_1]      9.642491 s: MEM: Init ... !!!
[MCU3_1]      9.642531 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db800000 of size 8388608 bytes !!!
[MCU3_1]      9.642599 s: MEM: Init ... Done !!!
[MCU3_1]      9.642629 s: IPC: Init ... !!!
[MCU3_1]      9.642690 s: IPC: 9 CPUs participating in IPC !!!
[MCU3_1]      9.642742 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU3_1]     20.785545 s: IPC: HLOS is ready !!!
[MCU3_1]     20.809314 s: IPC: Init ... Done !!!
[MCU3_1]     20.809385 s: APP: Syncing with 8 CPUs ... !!!
[C6x_1 ]      9.683887 s: CIO: Init ... Done !!!
[C6x_1 ]      9.683913 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      9.683924 s: CPU is running FreeRTOS
[C6x_1 ]      9.683931 s: APP: Init ... !!!
[C6x_1 ]      9.683939 s: SCICLIENT: Init ... !!!
[C6x_1 ]      9.684136 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      9.684148 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      9.684157 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      9.684167 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      9.684176 s: UDMA: Init ... !!!
[C6x_1 ]      9.685656 s: UDMA: Init ... Done !!!
[C6x_1 ]      9.685674 s: MEM: Init ... !!!
[C6x_1 ]      9.685687 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      9.685704 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      9.685720 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      9.685736 s: MEM: Init ... Done !!!
[C6x_1 ]      9.685744 s: IPC: Init ... !!!
[C6x_1 ]      9.685763 s: IPC: 9 CPUs participating in IPC !!!
[C6x_1 ]      9.685777 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     18.757771 s: IPC: HLOS is ready !!!
[C6x_1 ]     18.762433 s: IPC: Init ... Done !!!
[C6x_1 ]     18.762464 s: APP: Syncing with 8 CPUs ... !!!
[C6x_2 ]      9.765428 s: CIO: Init ... Done !!!
[C6x_2 ]      9.765454 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      9.765465 s: CPU is running FreeRTOS
[C6x_2 ]      9.765473 s: APP: Init ... !!!
[C6x_2 ]      9.765481 s: SCICLIENT: Init ... !!!
[C6x_2 ]      9.765695 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      9.765707 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      9.765717 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      9.765727 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      9.765736 s: UDMA: Init ... !!!
[C6x_2 ]      9.767249 s: UDMA: Init ... Done !!!
[C6x_2 ]      9.767268 s: MEM: Init ... !!!
[C6x_2 ]      9.767281 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      9.767299 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      9.767315 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      9.767331 s: MEM: Init ... Done !!!
[C6x_2 ]      9.767339 s: IPC: Init ... !!!
[C6x_2 ]      9.767361 s: IPC: 9 CPUs participating in IPC !!!
[C6x_2 ]      9.767375 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     19.223635 s: IPC: HLOS is ready !!!
[C6x_2 ]     19.227846 s: IPC: Init ... Done !!!
[C6x_2 ]     19.227874 s: APP: Syncing with 8 CPUs ... !!!
[C7x_1 ]      9.988690 s: CIO: Init ... Done !!!
[C7x_1 ]      9.988705 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      9.988718 s: CPU is running FreeRTOS
[C7x_1 ]      9.988726 s: APP: Init ... !!!
[C7x_1 ]      9.988734 s: SCICLIENT: Init ... !!!
[C7x_1 ]      9.988941 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      9.988954 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      9.988964 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      9.988975 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      9.988984 s: UDMA: Init ... !!!
[C7x_1 ]      9.990148 s: UDMA: Init ... Done !!!
[C7x_1 ]      9.990160 s: MEM: Init ... !!!
[C7x_1 ]      9.990172 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      9.990191 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      9.990209 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      9.990226 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      9.990243 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      9.990261 s: MEM: Init ... Done !!!
[C7x_1 ]      9.990270 s: IPC: Init ... !!!
[C7x_1 ]      9.990284 s: IPC: 9 CPUs participating in IPC !!!
[C7x_1 ]      9.990297 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     19.951721 s: IPC: HLOS is ready !!!
[C7x_1 ]     19.954098 s: IPC: Init ... Done !!!
[C7x_1 ]     19.954112 s: APP: Syncing with 8 CPUs ... !!!

Now we see two problems:1.MCU1_0 don't echo.  2.we get "APP: Syncing with 8 CPUs ... !!!", but no "APP: Syncing with 8 CPUs ...Done  !!!"

we test on TDA4VM EVM, and the SDK version is 08.06.0012.

Regards
Zhang

  • Hi,

    In this step need copy  tispl.bin and u-boot.ing from  ../ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/u-boot-2021.01+gitAUTOINC+62a9e51344-g62a9e51344/ j721e-arm64-linux. We didn't perform the operation,whether this makes a difference?

    u-boot would be built again when the MCU1_0 is enabled on vision_apps. Hence it is required to copy these 2 images as well.

    After that you should see the MCU1_0 logs.

    Before that I hope you have set the PSDK_LINUX_PATH correctly to your PSDKLA path in vision_apps/vision_apps_tools_path.mak

    Regards,

    Nikhil

  • HI,Nikhil

         Thanks for you support. Now  we can run it successfully. We have a doubt that Why do we need to use MCU1_0 firmware twice? 

    1.The MCU1_0  alreadly run mcu1_0 firmware in spl.bin by using tiboot3.bin when TDA4 start.  Why  it need  to run /lib/firmware/j7-mcu-r5f0_0-fw?

    2.How can MCU1_0  be executed a second time with /lib/firmware/j7-mcu-r5f0_0-fw when it is already running?

    Regards,

    Zhang