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TDA4VM: CPU:Periodic software readback of static configuration registers

yang zhang
Prodigy 30 points

Part Number: TDA4VM

hello,

These four are a type of safety mechanism that is necessary to achieve 90% diagnostic coverage. However, there are many static configuration registers in each CPU, and the specific information of these static configuration registers is not clearly described in the safety manual or TRM. So in the current software implementation process, software engineers do not know which static configuration registers to monitor.
May I ask which static registers in the CPU should we monitor for this safety mechanism? Does TI require monitoring of static configuration registers or suggest monitoring of which static registers?
thank you in advance
 
  • 0
    TI__Guru 58501 points

    Hi,

    Could you provide details on which safety mechanism you are referring to?

    Regards,

    Josiitaa

  • 0 in reply to Josiitaa RL
    Prodigy 30 points
    The following four safety mechanisms or diagnostics mechanisms are mentioned in the Arm Cortex-A72 Subsystem, C66x DSP Subsystem and C71x DSP Subsystem and Dual-R5F MCU - Pulsar Subsystem sections of the safety manual:
    A72SS.CPU6 - Periodic software readback of static configuration registers
    C66X.CPU6 - Periodic software readback of static configuration registers
    C7X.CPU6 - Periodic software readback of static configuration registers
    R5F.CPU6 - Periodic software readback of static configuration registers
  • 0 in reply to yang zhang
    TI__Guru 58501 points

    Hi,

    Only the static registers should be readback. Registers are considered static if they are only changed by a CPU write and non-static if they are changed by the device logic as a result of normal operation of the device. An easy register to identify as non-static would be an interrupt flag register where you have interrupts enabled for a given feature or a Tx or Rx register for a serial protocol peripheral.

    This read is to insure that the static registers haven't been inadvertently changed by either the software, by transient events, or by some permanent failure of the bits in the register.

    TI does not provide a list of registers that are categorized as safety relevant/critical. The expected value is either the default value or the value you have programmed to the registers. The list will vary depending on customer usage.  The TI safety manual provides the below guidance:

    The same applies to R5F.CPU6 as well.

    You could refer to these links additionally apart from the A72 TRM:

    Links to ARM A72 documentation are available on the ARM website as shown below

    Regards,

    Josiitaa