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AM625: Changing MDIO Interface Clock Frequency on Am625 Processor

Murali Chikkanna
Prodigy 145 points
Part Number: AM625
Other Parts Discussed in Thread: DP83620,

Hi TI,

I am working on a AM625 based custom Board, In the design we have Connected ethernet PHY(DP83620). In one of our DVT Test case,we need to capture the clock frequency of MDIO 

Interface(MDC Signal).

We tried capturing the signal while reading ethernet PHY status register at U-boot console.

mdio read 0x03 0x02

0x03 => PHY ID

0x02 => Register address

 We observed that the frequency is 700KHZ. But as per the ETH PHY (DP83620) datasheet it supports MDC clock frequency between 2.5 MHZ to 25 MHZ.

So is there any way to set the MDIO frequency to maximum Speed using U-Boot or Linux Commands or by changing the Driver Code.

Kindly guide me to solve this issue.

Thanks & Regards,

Murali Chikkanna 

  • 0
    TI__Mastermind 38130 points

    Hi, 

    I have returned from being out of the office. I will need to research your question, I will respond by Monday.

    Best Regards,

    Schuyler

  • 0
    Prodigy 50 points

    Hi Schuyler Patton,

    Will you please provide update on our query.

    Regards,

    Palanikumar E

  • 0 in reply to Palanikumar E
    Mastermind 6685 points

    Please note that I'm not TI, but I guess I can help you here:

    The AM625 is affected by errata i2329 - MDIO: MDIO interface corruption (CPSW and PRU-ICSS). The work around is bit-banging the MDIO pins via software running on the A53. The frequency that you achieve via bit-banging is most likely not constant, and what you actually achieve depends on many factors. Not sure what the U-Boot code that does the bit-banging looks like (and please note that it will be different code in Linux), but they most likely make sure that it's not faster than 2.5 MHz, and don't care exactly what frequency it is.

    The datasheet value that you're referencing is "typical to maximum", i.e. 2.5 to 25 MHz. There is no minimum specified. This is also in accordance with the 802.3 specification that says: "MDC is an aperiodic signal that has no maximum high or low times."

    Best Regards,

    Dominic

  • 0 in reply to Dominic Rath
    TI__Mastermind 38130 points

    Hi,

    First, Thank you Dominic for posting, your answer is correct and very helpful.

    As Dominic has pointed out there is a silicon errata that requires using the kernel mdio/mdio-gpio.c and mdio/mdio-bitbang.c code. Looking through the mdio-bitbang.c I see some hard coded values that appear to be delayed based bit shaping that seems to setting tx at 2MHz and read is 1.5MHz. This is community code that is being used by TI and to my knowledge it is not modified. 

    Best Regards,

    Schuyler