J784S4XEVM: Figuring out GPIO pin number with I/O PAD configuration & Pin mux

Divya Chowdary

Part Number: J784S4XEVM
Other Parts Discussed in Thread: TCAN1043

Hello Team,

I'm trying to figure out the pin number of MCAN0_Rx (GPIO pin), from the schematics (PROC141E2(001)_SCH.pdf)

But in mcuss_demo software in Dio module, there is no exact pin definition.

Also, when I observed the STB pin (TCAN1042 CAN transceiver), how its used to enable the transceiver in CanApp_EnableTransceivers()

Only the Dio channel 69 matches with the STB pin number. Could you please help with CSL_WKUP_GPIO0_BASE and why the value 0x60 is used here?

Similarly, I assume, that the Rx pin number or channel has to be extracted from

Could you let me know how to extract it?

Best Regards,

Divya.

over 1 year ago

0 Tarun Mukesh Puvvada over 1 year ago

TI__Mastermind 49696 points

Hello Divya,

Thanks for raising another E2E thread.

For MCU_MCAN0

You can look in the details of data manual for this.

To Enable transceiver we have take care of STB and EN pins based on TCAN1042 or TCAN1043 used as per schematics.

As you can see in the screenshot of schematics you attached WKUP_GPIO0_69 is used for MCU_CAN0_STBz.

Divya Chowdary said:
Only the Dio channel 69 matches with the STB pin number. Could you please help with CSL_WKUP_GPIO0_BASE and why the value 0x60 is used here?

We have banks for set of every 16 GPIO pins,total 9 banks for 144 pins.so based on GPIO pin you are using , need to select the respective bank and need to enable the respective pin in the bank.

In this case the Pin is 69 so it falls under GPIO_DIR45 Register so the Offset = 60h and 5th pin after bank starting pin number 64.You have to look into respective GPIO register for offset value in TRM.

Regards

Tarun Mukesh

0 Divya Chowdary over 1 year ago in reply to Tarun Mukesh Puvvada

Prodigy 30 points

Thank you Tarun for the response.

But I still have the below questions. Could you kindly clarify?

Aim to configure MCU_MCAN0_Rx as input pin
& poll it periodically

/* Pin mux cfg of MCU_MCAN0_Rx pin */
/* CSL_WKUP_CTRL_MMR0_CFG0_BASE = 0x43000000 */
/* CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG47 = 0x01C0BC */

regVal = 0x08050007;
CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG47, regVal);

/* Set Pin direction to input */
/* CSL_WKUP_GPIO0_BASE = 0x42110000 */

regVal = CSL_REG32_RD(CSL_WKUP_GPIO0_BASE + 0x48U);
/* guessing that the Rx pin belongs to the bank GPIO_IN_DATA23 = 48h */
Since there is no GPIO register bank doku in TRM of J784s4.

I'm referring to https://www.ti.com/document-viewer/lit/html/SPRUJ52C/GUID-D6904E60-EA2C-4358-940E-EA088B4AC524#TITLE-SPRUIJ7CHAPTER_GPIO

But I found this below image for J217e (from another E2E ticket,, searched for TRM of j721e, but unfortunately could not find it) and could not still get more info. Or could you also share the TRM of J721e? didn't find in this page : https://www.ti.com/tool/J721EXCPXEVM?utm_source=google&utm_medium=cpc&utm_campaign=epd-null-null-44700045336317905_prodfolderdynamic-cpc-pf-google-wwe_int&utm_content=prodfolddynamic&ds_k=DYNAMIC+SEARCH+ADS&DCM=yes&gad_source=1&gclid=EAIaIQobChMIi4m82JvaggMVwgaLCh11BQTKEAAYASAAEgJvUvD_BwE&gclsrc=aw.ds#design-files

regVal &= (~(1U << 0x05U)); // not sure what value to be used here to set pin to input ??

Regards,

Divya

0 Tarun Mukesh Puvvada over 1 year ago in reply to Divya Chowdary

TI__Mastermind 49696 points

Hello Divya,

Divya Chowdary said:
Since there is no GPIO register bank doku in TRM of J784s4.

I'm referring to https://www.ti.com/document-viewer/lit/html/SPRUJ52C/GUID-D6904E60-EA2C-4358-940E-EA088B4AC524#TITLE-SPRUIJ7CHAPTER_GPIO

But I found this below image for J217e (from another E2E ticket,, searched for TRM of j721e, but unfortunately could not find it) and could not still get more info. Or could you also share the TRM of J721e? didn't find in this page : https://www.ti.com/tool/J721EXCPXEVM?utm_source=google&utm_medium=cpc&utm_campaign=epd-null-null-44700045336317905_prodfolderdynamic-cpc-pf-google-wwe_int&utm_content=prodfolddynamic&ds_k=DYNAMIC+SEARCH+ADS&DCM=yes&gad_source=1&gclid=EAIaIQobChMIi4m82JvaggMVwgaLCh11BQTKEAAYASAAEgJvUvD_BwE&gclsrc=aw.ds#design-files

If you go to URL www.ti.com/.../TDA4VH-Q1 then you can see TRM of J784S4 In that .zip file you can see an excel sheet with register details.

Divya Chowdary said:
Aim to configure MCU_MCAN0_Rx as input pin
& poll it periodically

/* Pin mux cfg of MCU_MCAN0_Rx pin */
/* CSL_WKUP_CTRL_MMR0_CFG0_BASE = 0x43000000 */
/* CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG47 = 0x01C0BC */

regVal = 0x08050007;
CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_PADCONFIG47, regVal);

/* Set Pin direction to input */
/* CSL_WKUP_GPIO0_BASE = 0x42110000 */

Enabling Transceivers are different to Pinmuxing of Tx and Rx pins.

The procedure earlier i pointed out is to have fixed data on STB and EN pins to enable the respective transceivers for CAN.whereas CAN Tx and CAN Rx requires pin muxing and data on the pin will be fetched as required so we have,

 /* MCU MCAN 0 Tx PAD configuration */
    regVal = 0x60000U;
    LLD_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0A8U, regVal);
    /* MCU MCAN 0 Rx PAD configuration */
    regVal = 0x60000U;
    LLD_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C0ACU, regVal);

Regards

Tarun Mukesh

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J784S4XEVM: Figuring out GPIO pin number with I/O PAD configuration & Pin mux