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Dear TI,
Can MCU 2-0 call the I2C interface before appIpcInit? Because IPC requires 6 seconds for waiting, we think it's too long.
Hi qin,
Yes, it can call. I2C has no dependency on IPC.
Regards,
Brijesh
Hi Brijesh，
Linux will stuck when MCU 2-0 call the I2C interface before appIpcInit
code：
--- a/vision_apps/platform/j721s2/rtos/common/app_init.c
+++ b/vision_apps/platform/j721s2/rtos/common/app_init.c
@@ -457,6 +457,45 @@ int32_t appInit()
status = appMemInit(&mem_init_prm);
APP_ASSERT_SUCCESS(status);
+#ifdef CPU_mcu2_0
+ #ifdef ENABLE_FVID2
+ status = appFvid2Init();
+ APP_ASSERT_SUCCESS(status);
+ #endif
+
+ #ifdef ENABLE_I2C
+ appI2cInit();
+ #endif
+
+ #ifdef ENABLE_GPIO
+ appGpioInit();
+ #endif
+
+
+#include <iss_sensors.h>
+#define ISS_SENSORS_MAX_NAME (32U)
+extern int32_t ImageSensor_RemoteServiceHandler(char *service_name, uint32_t cmd, void *prm, uint32_t prm_size, uint32_t flags);
+static uint8_t g_cmdPrm[100];
+static uint32_t channel_mask = 0xf;
+static uint32_t featuresEnabled = 0x100;
+appLogPrintf("CONFIGURE CAMERA .............. ");
+
+#if 1
+memset(g_cmdPrm, 0, 100);
+memcpy(g_cmdPrm, "IMX623_UYVY", ISS_SENSORS_MAX_NAME);
+memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME, &featuresEnabled, sizeof(uint32_t));
+memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME+sizeof(uint32_t), &channel_mask, sizeof(uint32_t));
+ImageSensor_RemoteServiceHandler(NULL, IM_SENSOR_CMD_CONFIG, g_cmdPrm, 0, 0);
+#endif
+
+appLogPrintf("STREAM ON CAMERA ................");
+
+memset(g_cmdPrm, 0, 100);
+memcpy(g_cmdPrm, "IMX623_UYVY", ISS_SENSORS_MAX_NAME);
+memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME, &channel_mask, sizeof(uint32_t));
+ImageSensor_RemoteServiceHandler(NULL, IM_SENSOR_CMD_STREAM_ON, g_cmdPrm, 0, 0);
+#endif
+
#ifdef ENABLE_IPC
status = appIpcInit(&ipc_init_prm);
APP_ASSERT_SUCCESS(status);
@@ -508,6 +547,8 @@ int32_t appInit()
}
#endif
+
+#ifndef CPU_mcu2_0
#ifdef ENABLE_FVID2
status = appFvid2Init();
APP_ASSERT_SUCCESS(status);
@@ -520,6 +561,7 @@ int32_t appInit()
#ifdef ENABLE_GPIO
appGpioInit();
#endif
+#endif
/*
*
* Copyright (c) 2018 Texas Instruments Incorporated
*
* All rights reserved not granted herein.
*
* Limited License.
*
* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
* license under copyrights and patents it now or hereafter owns or controls to make,
* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
* terms herein. With respect to the foregoing patent license, such license is granted
* solely to the extent that any such patent is necessary to Utilize the software alone.
* The patent license shall not apply to any combinations which include this software,
* other than combinations with devices manufactured by or for TI ("TI Devices").
* No hardware patent is licensed hereunder.
*
* Redistributions must preserve existing copyright notices and reproduce this license
* (including the above copyright notice and the disclaimer and (if applicable) source
* code license limitations below) in the documentation and/or other materials provided
* with the distribution
*
* Redistribution and use in binary form, without modification, are permitted provided
* that the following conditions are met:
*
* * No reverse engineering, decompilation, or disassembly of this software is
* permitted with respect to any software provided in binary form.
*
* * any redistribution and use are licensed by TI for use only with TI Devices.
*
* * Nothing shall obligate TI to provide you with source code for the software
* licensed and provided to you in object code.
*
* If software source code is provided to you, modification and redistribution of the
* source code are permitted provided that the following conditions are met:
*
* * any redistribution and use of the source code, including any resulting derivative
* works, are licensed by TI for use only with TI Devices.
*
* * any redistribution and use of any object code compiled from the source code
* and any resulting derivative works, are licensed by TI for use only with TI Devices.
*
* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
*
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* DISCLAIMER.
*
* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <app_mem_map.h>
#include APP_CFG_FILE
#include <app.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_types.h>
/* Vision_apps utils header files */
#include <utils/mem/include/app_mem.h>
#include <utils/ipc/include/app_ipc.h>
#include <utils/remote_service/include/app_remote_service.h>
#include <utils/console_io/include/app_log.h>
#include <utils/console_io/include/app_cli.h>
#include <utils/misc/include/app_misc.h>
#include <utils/hwa/include/app_hwa.h>
#include <utils/iss/include/app_iss.h>
#include <utils/udma/include/app_udma.h>
#include <utils/dss/include/app_dss_defaults.h>
#include <utils/perf_stats/include/app_perf_stats.h>
#include <utils/sciclient/include/app_sciclient.h>
#include <utils/sciserver/include/app_sciserver.h>
#include <utils/sensors/include/app_sensors.h>
/* TIOVX header files */
#include <TI/tivx.h>
/* Vision_apps custom kernel header files */
#include <TI/tivx_img_proc.h>
#include <TI/tivx_fileio.h>
#include <TI/tivx_srv.h>
#include <TI/tivx_stereo.h>
/* Imaging header files */
#include <TI/j7_imaging_aewb.h>
/* PDK header files */
#include <ti/board/board.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
app_log_shared_mem_t g_app_log_shared_mem
__attribute__ ((section(".bss:app_log_mem")))
__attribute__ ((aligned(4096)))
;
uint8_t g_tiovx_obj_desc_mem[TIOVX_OBJ_DESC_MEM_SIZE]
__attribute__ ((section(".bss:tiovx_obj_desc_mem")))
__attribute__ ((aligned(4096)))
;
uint8_t g_ipc_vring_mem[IPC_VRING_MEM_SIZE]
__attribute__ ((section(".bss:ipc_vring_mem")))
__attribute__ ((aligned(4096)))
;
uint8_t g_ddr_local_mem[DDR_HEAP_MEM_SIZE]
__attribute__ ((section(".bss:ddr_local_mem")))
__attribute__ ((aligned(4096)))
;
#ifdef L1_MEM_SIZE
uint8_t g_l1_mem[L1_MEM_SIZE]
__attribute__ ((section(".bss:l1mem")))
__attribute__ ((aligned(4096)))
;
#endif
#ifdef L2_MEM_SIZE
uint8_t g_l2_mem[L2_MEM_SIZE]
__attribute__ ((section(".bss:l2mem")))
__attribute__ ((aligned(4096)))
;
#endif
#ifdef L3_MEM_SIZE
uint8_t g_l3_mem[L3_MEM_SIZE]
__attribute__ ((section(".bss:l3mem")))
__attribute__ ((aligned(4096)))
;
#endif
#ifdef DDR_SCRATCH_SIZE
uint8_t g_ddr_scratch_mem[DDR_SCRATCH_SIZE]
__attribute__ ((section(".bss:ddr_scratch_mem")))
__attribute__ ((aligned(4096)))
;
#endif
#ifdef DDR_HEAP_NON_CACHE_MEM_SIZE
uint8_t g_ddr_non_cache_mem[DDR_HEAP_NON_CACHE_MEM_SIZE]
__attribute__ ((section(".bss:ddr_non_cache_mem")))
__attribute__ ((aligned(4096)))
;
#endif
static void appRegisterOpenVXTargetKernels();
static void appUnRegisterOpenVXTargetKernels();
void appRtosTestRegister();
void appRtosTestUnRegister();
#ifdef ENABLE_UART
void appLogDeviceWrite(char *string, uint32_t max_size)
{
UART_puts(string, max_size);
}
#endif
int32_t appInit()
{
int32_t status = 0;
app_mem_init_prm_t mem_init_prm;
app_log_init_prm_t log_init_prm;
app_ipc_init_prm_t ipc_init_prm;
app_mem_heap_prm_t *heap_prm;
#if defined(CPU_mcu2_0) || defined(CPU_mcu2_1)
app_mem_rat_prm_t mem_rat_prm;
#endif
#ifdef ENABLE_IPC
uint32_t host_os_type;
void *ipc_resource_table = NULL;
#endif
/* Init and start GTC timer */
status = appLogGlobalTimeInit();
APP_ASSERT_SUCCESS(status);
#ifdef ENABLE_IPC
/* appGetIpcResourceTable() returns NULL in RTOS only mode and returns a valid resource table
* in Linux+RTOS mode
*/
ipc_resource_table = appGetIpcResourceTable();
host_os_type = appGetHostOSType();
#endif
appMemInitPrmSetDefault(&mem_init_prm);
appLogInitPrmSetDefault(&log_init_prm);
appIpcInitPrmSetDefault(&ipc_init_prm);
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_DDR];
heap_prm->base = g_ddr_local_mem;
strncpy(heap_prm->name, "DDR_LOCAL_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = DDR_HEAP_MEM_SIZE;
heap_prm->flags = APP_MEM_HEAP_FLAGS_IS_SHARED;
#ifdef L1_MEM_SIZE
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_L1];
heap_prm->base = g_l1_mem;
strncpy(heap_prm->name, "L1_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = L1_MEM_SIZE;
heap_prm->flags = APP_MEM_HEAP_FLAGS_TYPE_LINEAR_ALLOCATE;
#endif
#ifdef L2_MEM_SIZE
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_L2];
heap_prm->base = g_l2_mem;
strncpy(heap_prm->name, "L2_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = L2_MEM_SIZE;
heap_prm->flags = APP_MEM_HEAP_FLAGS_TYPE_LINEAR_ALLOCATE;
#endif
#ifdef L3_MEM_SIZE
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_L3];
heap_prm->base = g_l3_mem;
strncpy(heap_prm->name, "L3_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = L3_MEM_SIZE;
#ifdef CPU_mcu2_0
heap_prm->flags = 0; /* when CPU is mcu2-0 use it as normal heap */
#else
heap_prm->flags = APP_MEM_HEAP_FLAGS_TYPE_LINEAR_ALLOCATE;
#endif
#endif
#ifdef DDR_SCRATCH_SIZE
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_DDR_SCRATCH];
heap_prm->base = g_ddr_scratch_mem;
strncpy(heap_prm->name, "DDR_SCRATCH_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = DDR_SCRATCH_SIZE;
heap_prm->flags = APP_MEM_HEAP_FLAGS_TYPE_LINEAR_ALLOCATE;
#endif
#ifdef DDR_HEAP_NON_CACHE_MEM_SIZE
heap_prm = &mem_init_prm.heap_info[APP_MEM_HEAP_DDR_NON_CACHE];
heap_prm->base = g_ddr_non_cache_mem;
strncpy(heap_prm->name, "DDR_NON_CACHE_MEM", APP_MEM_HEAP_NAME_MAX);
heap_prm->size = DDR_HEAP_NON_CACHE_MEM_SIZE;
heap_prm->flags = 0;
#endif
#ifdef ENABLE_IPC
/* appGetIpcResourceTable() returns NULL in RTOS only mode and returns a valid resource table
* in Linux+RTOS mode
*/
ipc_init_prm.ipc_resource_tbl = ipc_resource_table;
if((host_os_type == APP_HOST_TYPE_LINUX))
{
ipc_init_prm.enable_tiovx_ipc_announce = 1;
}
else
{
ipc_init_prm.enable_tiovx_ipc_announce = 0;
}
ipc_init_prm.num_cpus = 0;
#ifdef ENABLE_IPC_MPU1_0
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MPU1_0;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MPU1_0] = 1;
#endif
#ifdef ENABLE_IPC_MCU1_0
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MCU1_0;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MCU1_0] = 1;
#endif
#ifdef ENABLE_IPC_MCU2_0
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MCU2_0;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MCU2_0] = 1;
#endif
#ifdef ENABLE_IPC_MCU2_1
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MCU2_1;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MCU2_1] = 1;
#endif
#ifdef ENABLE_IPC_MCU3_0
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MCU3_0;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MCU3_0] = 1;
#endif
#ifdef ENABLE_IPC_MCU3_1
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_MCU3_1;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_MCU3_1] = 1;
#endif
#ifdef ENABLE_IPC_C7x_1
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_C7x_1;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_C7x_1] = 1;
#endif
#ifdef ENABLE_IPC_C7x_2
ipc_init_prm.enabled_cpu_id_list[ipc_init_prm.num_cpus] = APP_IPC_CPU_C7x_2;
ipc_init_prm.num_cpus++;
log_init_prm.log_rd_cpu_enable[APP_IPC_CPU_C7x_2] = 1;
#endif
ipc_init_prm.tiovx_obj_desc_mem = (void*)g_tiovx_obj_desc_mem;
ipc_init_prm.tiovx_obj_desc_mem_size = TIOVX_OBJ_DESC_MEM_SIZE;
ipc_init_prm.tiovx_log_rt_mem = (void*)TIOVX_LOG_RT_MEM_ADDR;
ipc_init_prm.tiovx_log_rt_mem_size = TIOVX_LOG_RT_MEM_SIZE;
ipc_init_prm.ipc_vring_mem = g_ipc_vring_mem;
ipc_init_prm.ipc_vring_mem_size = IPC_VRING_MEM_SIZE;
#ifdef CPU_mpu1
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MPU1_0;
#endif
#ifdef CPU_mcu1_0
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MCU1_0;
#endif
#ifdef CPU_mcu2_0
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MCU2_0;
#endif
#ifdef CPU_mcu2_1
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MCU2_1;
#endif
#ifdef CPU_mcu3_0
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MCU3_0;
#endif
#ifdef CPU_mcu3_1
ipc_init_prm.self_cpu_id = APP_IPC_CPU_MCU3_1;
#endif
#ifdef CPU_c7x_1
ipc_init_prm.self_cpu_id = APP_IPC_CPU_C7x_1;
#endif
#ifdef CPU_c7x_2
ipc_init_prm.self_cpu_id = APP_IPC_CPU_C7x_2;
#endif
#endif
log_init_prm.shared_mem = &g_app_log_shared_mem;
log_init_prm.self_cpu_index = ipc_init_prm.self_cpu_id;
#ifdef CPU_mpu1
strncpy(log_init_prm.self_cpu_name, "MPU1" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_mcu1_0
strncpy(log_init_prm.self_cpu_name, "MCU1_0" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_mcu2_0
strncpy(log_init_prm.self_cpu_name, "MCU2_0" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_mcu2_1
strncpy(log_init_prm.self_cpu_name, "MCU2_1" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_mcu3_0
strncpy(log_init_prm.self_cpu_name, "MCU3_0" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_mcu3_1
strncpy(log_init_prm.self_cpu_name, "MCU3_1" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_c7x_1
strncpy(log_init_prm.self_cpu_name, "C7x_1" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef CPU_c7x_2
strncpy(log_init_prm.self_cpu_name, "C7x_2" , APP_LOG_MAX_CPU_NAME);
#endif
#ifdef ENABLE_UART
log_init_prm.log_rd_max_cpus = APP_IPC_CPU_MAX;
log_init_prm.device_write = appLogDeviceWrite;
#endif
appPerfStatsInit();
#ifdef ENABLE_BOARD
{
app_pinmux_cfg_t pinmux_cfg;
appPinMuxCfgSetDefault(&pinmux_cfg);
#if defined(ENABLE_DSS_SINGLE)
pinmux_cfg.enable_i2c = TRUE; /* i2c is needed for on board HDMI mux config, eDP to HDMI adapter config */
#ifdef ENABLE_DSS_HDMI
pinmux_cfg.enable_hdmi = TRUE;
#endif
#endif
#if defined(ENABLE_DSS_DUAL)
pinmux_cfg.enable_hdmi = TRUE; /* enable HDMI unconditionally for dual display */
pinmux_cfg.enable_i2c = TRUE; /* i2c is needed for on board HDMI mux config, eDP to HDMI adapter config */
#endif
appSetPinmux(&pinmux_cfg);
}
#endif
#ifdef ENABLE_UART
status = appLogRdInit(&log_init_prm);
APP_ASSERT_SUCCESS(status);
#endif
status = appLogWrInit(&log_init_prm);
APP_ASSERT_SUCCESS(status);
#ifdef ENABLE_PRINTF_REDIRECT
status = appLogCioInit();
APP_ASSERT_SUCCESS(status);
#endif
appUtilsPrintCpuHz();
#if defined(FREERTOS)
appLogPrintf("CPU is running FreeRTOS\n");
#elif defined(SAFERTOS)
appLogPrintf("CPU is running SafeRTOS\n");
#endif
appLogPrintf("APP: Init ... !!!\n");
#ifdef ENABLE_UART
{
app_cli_init_prm_t cli_init_prm;
appCliInitPrmSetDefault(&cli_init_prm);
status = appCliInit(&cli_init_prm);
APP_ASSERT_SUCCESS(status);
}
#endif
#ifdef ENABLE_SCICLIENT
status = appSciclientInit();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_UDMA
status = appUdmaInit();
APP_ASSERT_SUCCESS(status);
#ifdef CPU_mcu2_0
status = appUdmaCsirxCsitxInit();
APP_ASSERT_SUCCESS(status);
#endif
#endif
#if defined(CPU_mcu2_0) || defined(CPU_mcu2_1)
#ifdef L3_MEM_SIZE
mem_rat_prm.size = L3_MEM_SIZE;
#if defined(CPU_mcu2_0)
mem_rat_prm.baseAddress = MAIN_OCRAM_MCU2_0_ADDR;
mem_rat_prm.translatedAddress = MAIN_OCRAM_MCU2_0_PHYS_ADDR;
#elif defined(CPU_mcu2_1)
mem_rat_prm.baseAddress = MAIN_OCRAM_MCU2_1_ADDR;
mem_rat_prm.translatedAddress = MAIN_OCRAM_MCU2_1_PHYS_ADDR;
#endif
status = appMemAddrTranslate(&mem_rat_prm);
APP_ASSERT_SUCCESS(status);
#endif
#endif
status = appMemInit(&mem_init_prm);
APP_ASSERT_SUCCESS(status);
#ifdef CPU_mcu2_0
#ifdef ENABLE_FVID2
status = appFvid2Init();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_I2C
appI2cInit();
#endif
#ifdef ENABLE_GPIO
appGpioInit();
#endif
#include <iss_sensors.h>
#define ISS_SENSORS_MAX_NAME (32U)
extern int32_t ImageSensor_RemoteServiceHandler(char *service_name, uint32_t cmd, void *prm, uint32_t prm_size, uint32_t flags);
static uint8_t g_cmdPrm[100];
static uint32_t channel_mask = 0xf;
static uint32_t featuresEnabled = 0x100;
appLogPrintf("CONFIGURE CAMERA .............. ");
#if 1
memset(g_cmdPrm, 0, 100);
memcpy(g_cmdPrm, "IMX623_UYVY", ISS_SENSORS_MAX_NAME);
memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME, &featuresEnabled, sizeof(uint32_t));
memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME+sizeof(uint32_t), &channel_mask, sizeof(uint32_t));
ImageSensor_RemoteServiceHandler(NULL, IM_SENSOR_CMD_CONFIG, g_cmdPrm, 0, 0);
#endif
appLogPrintf("STREAM ON CAMERA ................");
memset(g_cmdPrm, 0, 100);
memcpy(g_cmdPrm, "IMX623_UYVY", ISS_SENSORS_MAX_NAME);
memcpy(g_cmdPrm+ISS_SENSORS_MAX_NAME, &channel_mask, sizeof(uint32_t));
ImageSensor_RemoteServiceHandler(NULL, IM_SENSOR_CMD_STREAM_ON, g_cmdPrm, 0, 0);
#endif
#ifdef ENABLE_IPC
status = appIpcInit(&ipc_init_prm);
APP_ASSERT_SUCCESS(status);
{
uint32_t sync_cpu_id_list[APP_LOG_MAX_CPUS];
uint32_t i, self_cpu_id, master_cpu_id, num_sync_cpus;
if((host_os_type == APP_HOST_TYPE_LINUX) || (host_os_type == APP_HOST_TYPE_QNX))
{
master_cpu_id = APP_IPC_CPU_MCU2_0;
}
else
{
master_cpu_id = APP_IPC_CPU_MPU1_0;
}
self_cpu_id = ipc_init_prm.self_cpu_id;
num_sync_cpus = 0;
for(i=0; i<ipc_init_prm.num_cpus; i++)
{
if(i<APP_LOG_MAX_CPUS)
{
if((host_os_type == APP_HOST_TYPE_LINUX) || (host_os_type == APP_HOST_TYPE_QNX))
{
/* dont sync with MPU1 running linux/qnx since that is taken care by the kernel */
if(ipc_init_prm.enabled_cpu_id_list[i]!=APP_IPC_CPU_MPU1_0)
{
sync_cpu_id_list[num_sync_cpus] = ipc_init_prm.enabled_cpu_id_list[i];
num_sync_cpus++;
}
}
else
{
sync_cpu_id_list[num_sync_cpus] = ipc_init_prm.enabled_cpu_id_list[i];
num_sync_cpus++;
}
}
}
appLogPrintf("APP: Syncing with %d CPUs ... !!!\n", num_sync_cpus);
appLogCpuSyncInit(master_cpu_id, self_cpu_id, sync_cpu_id_list, num_sync_cpus);
appLogPrintf("APP: Syncing with %d CPUs ... Done !!!\n", num_sync_cpus);
}
{
app_remote_service_init_prms_t init_prms;
appRemoteServiceInitSetDefault(&init_prms);
appRemoteServiceInit(&init_prms);
appRtosTestRegister();
appPerfStatsRemoteServiceInit();
}
#endif
#ifndef CPU_mcu2_0
#ifdef ENABLE_FVID2
status = appFvid2Init();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_I2C
appI2cInit();
#endif
#ifdef ENABLE_GPIO
appGpioInit();
#endif
#endif
#ifdef ENABLE_DSS_SINGLE
{
//if(APP_IPC_CPU_MCU2_0 != ipc_init_prm.self_cpu_id){
app_dss_default_prm_t prm;
appDssDefaultSetDefaultPrm(&prm);
#ifdef ENABLE_DSS_HDMI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DPI_HDMI;
#endif
#ifdef ENABLE_DSS_EDP
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_EDP;
#endif
prm.enableM2m = true;
/* Do not rely on "init". Always provide known good tmings */
prm.timings.width = 1920U;
prm.timings.height = 1080U;
prm.timings.hFrontPorch = 88U;
prm.timings.hBackPorch = 148U;
prm.timings.hSyncLen = 44U;
prm.timings.vFrontPorch = 4U;
prm.timings.vBackPorch = 36U;
prm.timings.vSyncLen = 5U;
prm.timings.pixelClock = 148500000ULL;
#ifdef ENABLE_DSS_DSI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
prm.timings.width = 1280U;
prm.timings.height = 800U;
prm.timings.hFrontPorch = 110U;
prm.timings.hBackPorch = 220U;
prm.timings.hSyncLen = 40U;
prm.timings.vFrontPorch = 5U;
prm.timings.vBackPorch = 20U;
prm.timings.vSyncLen = 5U;
prm.timings.pixelClock = 74250000ULL;
#endif
status = appDssDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
//}
}
#endif
#ifdef ENABLE_DSS_DUAL
{
app_dss_dual_display_default_prm_t prm;
uint32_t i;
/* default parameters are enough to enable both EDP and HDMI */
appDssDualDisplayDefaultSetDefaultPrm(&prm);
prm.enableM2m = true;
/* Do not rely on "init". Always provide known good tmings */
for(i=0; i<2; i++)
{
prm.display[i].timings.width = 1920U;
prm.display[i].timings.height = 1080U;
prm.display[i].timings.hFrontPorch = 88U;
prm.display[i].timings.hBackPorch = 148U;
prm.display[i].timings.hSyncLen = 44U;
prm.display[i].timings.vFrontPorch = 4U;
prm.display[i].timings.vBackPorch = 36U;
prm.display[i].timings.vSyncLen = 5U;
prm.display[i].timings.pixelClock = 148500000ULL;
}
status = appDssDualDisplayDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
}
#endif
#ifdef ENABLE_VHWA_VPAC
status = appVhwaVpacInit(0u);
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_VHWA_DMPAC
status = appVhwaDmpacInit();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_TIOVX
tivxInit();
#ifdef ENABLE_TIOVX_HOST
tivxHostInit();
#endif
#endif
appRegisterOpenVXTargetKernels();
#ifdef ENABLE_CSI2RX
status = appCsi2RxInit();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_CSI2TX
status = appCsi2TxInit();
APP_ASSERT_SUCCESS(status);
#endif
#if defined(ENABLE_I2C) && defined(ENABLE_CSI2RX)
status = appIssInit();
APP_ASSERT_SUCCESS(status);
status = appRemoteServiceSensorInit();
APP_ASSERT_SUCCESS(status);
#endif
#if defined(ENABLE_VHWA_VPAC)
status = appVissRemoteServiceInit();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef ENABLE_UDMA_COPY
status = appUdmaCopyInit();
APP_ASSERT_SUCCESS(status);
#endif
/* Register remote service for SL2 reallocation
* Can add more conditions if needed.
*/
#ifdef ENABLE_VHWA_DMPAC
status = appVhwaRemoteServiceInit();
APP_ASSERT_SUCCESS(status);
#endif
#ifdef CPU_mcu2_0
#if defined(FREERTOS)
status = appIpcCreateTraceBufFlushTask();
#endif
#endif
appLogPrintf("APP: Init ... Done !!!\n");
return status;
}
void appDeInit()
{
appLogPrintf("APP: Deinit ... !!!\n");
appUnRegisterOpenVXTargetKernels();
#ifdef ENABLE_UDMA_COPY
appUdmaCopyDeinit();
#endif
#ifdef ENABLE_TIOVX
#ifdef ENABLE_TIOVX_HOST
tivxHostDeInit();
#endif
tivxDeInit();
#endif
#ifdef ENABLE_VHWA_VPAC
appVhwaVpacDeInit();
#endif
#ifdef ENABLE_VHWA_DMPAC
appVhwaDmpacDeInit();
#endif
#ifdef ENABLE_DSS_SINGLE
appDssDefaultDeInit();
#endif
#ifdef ENABLE_DSS_DUAL
appDssDualDisplayDefaultDeInit();
#endif
#ifdef ENABLE_CSI2RX
appCsi2RxDeInit();
#endif
#ifdef ENABLE_CSI2TX
appCsi2TxDeInit();
#endif
#ifdef ENABLE_FVID2
appFvid2DeInit();
#endif
#ifdef ENABLE_IPC
appPerfStatsDeInit();
appRtosTestUnRegister();
appRemoteServiceDeInit();
appIpcDeInit();
#endif
appMemDeInit();
#ifdef ENABLE_PRINTF_REDIRECT
appLogCioDeInit();
#endif
appLogWrDeInit();
#ifdef ENABLE_UART
appLogRdDeInit();
appCliDeInit();
#endif
#ifdef ENABLE_UDMA
appUdmaDeInit();
#endif
#ifdef ENABLE_SCICLIENT
appSciclientDeInit();
#endif
#ifdef ENABLE_I2C
appI2cDeInit();
#endif
#ifdef ENABLE_GPIO
appGpioDeInit();
#endif
#if defined(ENABLE_VHWA_VPAC0)
appVissRemoteServiceDeInit();
#endif
#if defined(ENABLE_I2C) && defined(ENABLE_CSI2RX)
appIssDeInit();
appRemoteServiceSensorDeInit();
#endif
/* De-init GTC timer */
appLogGlobalTimeDeInit();
/* Unregister remote service for SL2 reallocation.
* Can add more conditions if needed.
*/
#ifdef ENABLE_VHWA_DMPAC
appVhwaRemoteServiceDeInit();
#endif
appLogPrintf("APP: Deinit ... Done !!!\n");
}
static void appRegisterOpenVXTargetKernels()
{
#ifdef ENABLE_TIOVX
appLogPrintf("APP: OpenVX Target kernel init ... !!!\n");
#ifdef ENABLE_VHWA_VPAC
tivxRegisterHwaTargetVpacMscKernels();
tivxRegisterHwaTargetVpacLdcKernels();
tivxRegisterHwaTargetVpacVissKernels();
tivxRegisterHwaTargetVpacNfKernels();
tivxRegisterHwaTargetArmKernels();
#endif
#ifdef ENABLE_VHWA_DMPAC
tivxRegisterHwaTargetDmpacSdeKernels();
tivxRegisterHwaTargetDmpacDofKernels();
#endif
#ifdef ENABLE_CSI2RX
tivxRegisterHwaTargetCaptureKernels();
#endif
#ifdef ENABLE_CSI2TX
tivxRegisterHwaTargetCsitxKernels();
#endif
#if defined(ENABLE_DSS_SINGLE) || defined(ENABLE_DSS_DUAL)
tivxRegisterHwaTargetDisplayKernels();
tivxRegisterHwaTargetDisplayM2MKernels();
#endif
#ifdef C7120
#ifdef CPU_c7x_1
{
void app_c7x_target_kernel_img_add_register(void);
app_c7x_target_kernel_img_add_register();
}
tivxRegisterTIDLTargetKernels();
tivxRegisterTVMTargetKernels();
tivxRegisterImgProcTargetC71Kernels();
#endif
#ifdef CPU_c7x_2
tivxRegisterStereoTargetKernels();
tivxRegisterSrvTargetC66Kernels();
tivxRegisterHwaTargetArmKernels();
tivxRegisterImgProcTargetC66Kernels();
#endif
#endif
#ifdef ENABLE_VHWA_VPAC
tivxRegisterImgProcTargetR5FKernels();
tivxRegisterImagingTargetAewbKernels();
#endif
appLogPrintf("APP: OpenVX Target kernel init ... Done !!!\n");
#endif
}
static void appUnRegisterOpenVXTargetKernels()
{
#ifdef ENABLE_TIOVX
appLogPrintf("APP: OpenVX Target kernel deinit ... !!!\n");
#ifdef ENABLE_VHWA_VPAC
tivxUnRegisterHwaTargetVpacMscKernels();
tivxUnRegisterHwaTargetVpacLdcKernels();
tivxUnRegisterHwaTargetVpacNfKernels();
tivxUnRegisterHwaTargetVpacVissKernels();
tivxUnRegisterHwaTargetArmKernels();
#endif
#ifdef ENABLE_VHWA_DMPAC
tivxUnRegisterHwaTargetDmpacSdeKernels();
tivxUnRegisterHwaTargetDmpacDofKernels();
#endif
#if defined(ENABLE_DSS_SINGLE) || defined(ENABLE_DSS_DUAL)
tivxUnRegisterHwaTargetDisplayKernels();
tivxUnRegisterHwaTargetDisplayM2MKernels();
#endif
#ifdef ENABLE_CSI2RX
tivxUnRegisterHwaTargetCaptureKernels();
#endif
#ifdef ENABLE_CSI2TX
tivxUnRegisterHwaTargetCsitxKernels();
#endif
#ifdef C7120
#ifdef CPU_c7x_1
{
void app_c7x_target_kernel_img_add_unregister(void);
app_c7x_target_kernel_img_add_unregister();
}
tivxUnRegisterTIDLTargetKernels();
tivxUnRegisterTVMTargetKernels();
tivxUnRegisterImgProcTargetC71Kernels();
#endif
#ifdef CPU_c7x_2
tivxUnRegisterStereoTargetKernels();
tivxUnRegisterSrvTargetC66Kernels();
tivxUnRegisterHwaTargetArmKernels();
tivxUnRegisterImgProcTargetC66Kernels();
#endif
#endif
#ifdef ENABLE_VHWA_VPAC
tivxUnRegisterImgProcTargetR5FKernels();
tivxUnRegisterImagingTargetAewbKernels();
#endif
appLogPrintf("APP: OpenVX Target kernel deinit ... Done !!!\n");
#endif
}
void appIdleLoop(void)
{
#if defined(__C7120__)
__asm(" IDLE");
#endif
}
Linux will stuck here：
[ 1.692827] debugfs: Directory 'pd:154' with parent 'pm_genpd' already present!
[ 1.707035] ALSA device list:
[ 1.710007] No soundcards found.
[ 1.713758] Waiting for root device /dev/mmcblk1p2...
[ 31.820676] tlv71033: disabling
LOG：
NOTICE: BL31: v2.8(release):7953b4f
NOTICE: BL31: Built : 10:56:05, May 29 2023
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC:
I/TC: OP-TEE version: 97dc684 (gcc version 9.4.0 (Ubuntu 9.4.0-1ubuntu1~20.04.1)) #1 Mon May 29 02:56:44 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] Linux version 5.10.162-g76b3e88d56 (bric@bric) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Fri Nov 17 06:47:29 UTC 2023
[ 0.000000] Machine model: Texas Instruments J721S2 EVM
[ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a2000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a2100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a6000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a6100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 32 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-rtos-ipc-memory-region@a8000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 96 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@aa000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b0000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b0000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b0100000, size 95 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-c71_0-memory@b0100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b6000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-c71_1-dma-memory@b6000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b6100000, size 31 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-c71_1-memory@b6100000, compatible id shared-dma-pool
[ 0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 64 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo@d8000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 704 MiB
[ 0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x00000008ac000000, size 896 MiB
[ 0.000000] OF: reserved mem: initialized node linux-cma-buffers@8ac000000, compatible id shared-dma-pool
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff]
[ 0.000000] node 0: [mem 0x000000009e800000-0x00000000b7ffffff]
[ 0.000000] node 0: [mem 0x00000000b8000000-0x00000000d7ffffff]
[ 0.000000] node 0: [mem 0x00000000d8000000-0x00000000dbffffff]
[ 0.000000] node 0: [mem 0x00000000dc000000-0x00000000ffffffff]
[ 0.000000] node 0: [mem 0x0000000880000000-0x00000008abffffff]
[ 0.000000] node 0: [mem 0x00000008ac000000-0x00000008ffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: Trusted OS migration not required
[ 0.000000] psci: SMC Calling Convention v1.2
[ 0.000000] percpu: Embedded 22 pages/cpu s50392 r8192 d31528 u90112
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: EL2 vector hardening
[ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[ 0.000000] CPU features: detected: Spectre-BHB
[ 0.000000] CPU features: detected: ARM erratum 1742098
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1032192
[ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2800000 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[ 0.000000] Memory: 1383912K/4194304K available (11712K kernel code, 1192K rwdata, 4468K rodata, 1984K init, 456K bss, 1892888K reserved, 917504K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv3: 960 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 0.000000] GICv3: Distributor has no Range Selector support
[ 0.000000] GICv3: 16 PPIs implemented
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[ 0.000000] ITS [mem 0x01820000-0x0182ffff]
[ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8e4800000 (flat, esz 8, psz 64K, shr 0)
[ 0.000000] ITS: using cache flushing for cmd queue
[ 0.000000] GICv3: using LPI property table @0x00000008e4030000
[ 0.000000] GIC: using cache flushing for LPI property table
[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008e4040000
[ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[ 0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[ 0.008396] Console: colour dummy device 80x25
[ 0.012966] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[ 0.023637] pid_max: default: 32768 minimum: 301
[ 0.028400] LSM: Security Framework initializing
[ 0.033163] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.040749] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.049730] rcu: Hierarchical SRCU implementation.
[ 0.054832] Platform MSI: msi-controller@1820000 domain created
[ 0.061059] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[ 0.070367] EFI services will not be available.
[ 0.075115] smp: Bringing up secondary CPUs ...
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
[ 0.094150] Detected PIPT I-cache on CPU1
[ 0.094176] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[ 0.094189] GICv3: CPU1: using allocated LPI pending table @0x00000008e4050000
[ 0.094230] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[ 0.094296] smp: Brought up 1 node, 2 CPUs
[ 0.123645] SMP: Total of 2 processors activated.
[ 0.128451] CPU features: detected: 32-bit EL0 Support
[ 0.133706] CPU features: detected: CRC32 instructions
[ 0.149006] CPU: All CPU(s) started at EL2
[ 0.153213] alternatives: patching kernel code
[ 0.158378] devtmpfs: initialized
[ 0.166636] KASLR disabled due to lack of seed
[ 0.171311] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.181279] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[ 0.203688] pinctrl core: initialized pinctrl subsystem
[ 0.209419] DMI not present or invalid.
[ 0.213723] NET: Registered protocol family 16
[ 0.219213] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[ 0.226531] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[ 0.234543] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[ 0.242685] ramoops: using module parameters
[ 0.247118] ramoops ramoops: no room for dmesg mem region (0xffffffffffffe000@0xdd000000) in (0x40000@0xdd000000)
[ 0.257618] ramoops: probe of ramoops failed with error -12
[ 0.263527] thermal_sys: Registered thermal governor 'step_wise'
[ 0.263531] thermal_sys: Registered thermal governor 'power_allocator'
[ 0.270199] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.283852] ASID allocator initialised with 32768 entries
[ 0.290076] printk: console [ramoops-1] enabled
[ 0.294711] pstore: Registered ramoops as persistent store backend
[ 0.301025] ramoops: using 0x40000@0xdd000000, ecc: 0
[ 0.319694] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.326564] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.333413] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.340260] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[ 0.347849] cryptd: max_cpu_qlen set to 1000
[ 0.354178] k3-chipinfo 43000014.chipid: Family:J721S2 rev:SR1.0 JTAGID[0x0bb7502f] Detected
[ 0.363304] vsys_3v3: supplied by evm_12v0
[ 0.367702] vsys_5v0: supplied by evm_12v0
[ 0.372569] iommu: Default domain type: Translated
[ 0.377741] SCSI subsystem initialized
[ 0.381673] usbcore: registered new interface driver usbfs
[ 0.387298] usbcore: registered new interface driver hub
[ 0.392740] usbcore: registered new device driver usb
[ 0.398151] mc: Linux media interface: v0.10
[ 0.402527] videodev: Linux video capture interface: v2.00
[ 0.408160] pps_core: LinuxPPS API ver. 1 registered
[ 0.413231] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.422570] PTP clock support registered
[ 0.426592] EDAC MC: Ver: 3.0.0
[ 0.430445] FPGA manager framework
[ 0.433975] Advanced Linux Sound Architecture Driver Initialized.
[ 0.440655] clocksource: Switched to clocksource arch_sys_counter
[ 0.447028] VFS: Disk quotas dquot_6.6.0
[ 0.451072] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.460945] Carveout Heap: Exported 512 MiB at 0x00000000b8000000
[ 0.467248] NET: Registered protocol family 2
[ 0.472047] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.480708] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[ 0.489481] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 0.497687] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear)
[ 0.505488] TCP: Hash tables configured (established 32768 bind 32768)
[ 0.512348] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[ 0.519249] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[ 0.526676] NET: Registered protocol family 1
[ 0.531478] RPC: Registered named UNIX socket transport module.
[ 0.537542] RPC: Registered udp transport module.
[ 0.542362] RPC: Registered tcp transport module.
[ 0.547168] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.553751] NET: Registered protocol family 44
[ 0.558305] PCI: CLS 0 bytes, default 64
[ 0.562760] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[ 0.573512] Initialise system trusted keyrings
[ 0.578165] workingset: timestamp_bits=46 max_order=20 bucket_order=0
[ 0.586428] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.592796] NFS: Registering the id_resolver key type
[ 0.597982] Key type id_resolver registered
[ 0.602255] Key type id_legacy registered
[ 0.606384] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 0.613235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[ 0.620895] 9p: Installing v9fs 9p2000 file system support
[ 0.646428] Key type asymmetric registered
[ 0.650618] Asymmetric key parser 'x509' registered
[ 0.655624] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[ 0.663184] io scheduler mq-deadline registered
[ 0.667811] io scheduler kyber registered
[ 0.673343] pinctrl-single 4301c000.pinctrl: 101 pins, size 404
[ 0.679572] pinctrl-single 11c000.pinctrl: 72 pins, size 288
[ 0.690110] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[ 0.703111] brd: module loaded
[ 0.710420] loop: module loaded
[ 0.714376] megasas: 07.714.04.00-rc1
[ 0.720067] tun: Universal TUN/TAP device driver, 1.6
[ 0.725577] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[ 0.731987] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 0.738069] sky2: driver version 1.30
[ 0.742454] VFIO - User Level meta-driver version: 0.3
[ 0.748349] i2c /dev entries driver
[ 0.752756] sdhci: Secure Digital Host Controller Interface driver
[ 0.759076] sdhci: Copyright(c) Pierre Ossman
[ 0.763827] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.770174] ledtrig-cpu: registered to indicate activity on CPUs
[ 0.776529] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[ 0.783435] ashmem: initialized
[ 0.787499] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[ 0.792071] optee: revision 3.20 (97dc6845)
[ 0.808472] optee: dynamic shared memory is enabled
[ 0.817962] optee: initialized driver
[ 0.823176] NET: Registered protocol family 17
[ 0.827824] 9pnet: Installing 9P2000 support
[ 0.832228] Key type dns_resolver registered
[ 0.836702] Loading compiled-in X.509 certificates
[ 0.842867] pstore: Invalid compression size for deflate: 0
[ 0.855403] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0008 '8.6.3--v08.06.03 (Chill Capybar')
[ 0.891371] omap_i2c 42120000.i2c: bus 0 rev0.12 at 100 kHz
[ 0.897621] omap_i2c 40b00000.i2c: bus 1 rev0.12 at 100 kHz
[ 0.903732] omap_i2c 40b10000.i2c: bus 2 rev0.12 at 100 kHz
[ 0.910211] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created
[ 0.918790] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain created
[ 0.928166] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 227 domain created
[ 0.936891] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 265 created
[ 0.947045] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 0.954763] j721e-pcie 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 0.963045] j721e-pcie 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 0.971324] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 0.980474] ti-udma 311a0000.dma-controller: Number of rings: 48
[ 0.987375] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
[ 0.996843] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272
[ 1.006723] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[ 1.013484] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[ 1.022549] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:259
[ 1.032733] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[ 1.039495] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[ 1.047297] omap8250 40a00000.serial: failed to get alias
[ 1.053538] printk: console [ttyS2] disabled
[ 1.057960] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 21, base_baud = 3000000) is a 8250
[ 1.066715] printk: console [ttyS2] enabled
[ 1.066715] printk: console [ttyS2] enabled
[ 1.075158] printk: bootconsole [ns16550a0] disabled
[ 1.075158] printk: bootconsole [ns16550a0] disabled
[ 1.089411] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[ 1.132668] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 1.141142] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[ 1.149195] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.162065] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.169274] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.175684] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
[ 1.186244] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:200000000, add_val:4 pps:0
[ 1.296235] mmc0: CQHCI version 5.10
[ 1.299882] davinci_gpio 42110000.gpio: IRQ index 0 not found
[ 1.305631] davinci_gpio 42110000.gpio: error -ENXIO: IRQ not populated
[ 1.315150] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
[ 1.322029] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[ 1.328896] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
[ 1.335744] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[ 1.337224] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[ 1.349831] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 1.357326] j721e-pcie 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 1.365408] j721e-pcie 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 1.373493] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 1.382814] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[ 1.393075] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16)
[ 1.403987] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode
[ 1.448668] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 1.457186] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver unknown
[ 1.465254] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 1.478112] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 1.485322] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 1.491698] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:0
[ 1.500850] mmc0: Command Queue Engine enabled
[ 1.505304] mmc0: new DDR MMC card at address 0001
[ 1.510433] mmcblk0: mmc0:0001 8GUF4R 7.28 GiB
[ 1.515064] mmcblk0boot0: mmc0:0001 8GUF4R partition 1 31.9 MiB
[ 1.521077] mmcblk0boot1: mmc0:0001 8GUF4R partition 2 31.9 MiB
[ 1.527088] mmcblk0rpmb: mmc0:0001 8GUF4R partition 3 4.00 MiB, chardev (236:0)
[ 1.534488] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[ 1.536760] GPT:Primary header thinks Alt. header is not at the end of the disk.
[ 1.548323] GPT:14680063 != 15269887
[ 1.551896] GPT:Alternate GPT header not at the end of the disk.
[ 1.557894] GPT:14680063 != 15269887
[ 1.561474] GPT: Use GNU Parted to correct GPT errors.
[ 1.566624] mmcblk0: p1 p2 p3 p4 p5 p6
[ 1.570610] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 1.578133] j721e-pcie 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 1.586224] j721e-pcie 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 1.594307] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 1.603988] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 1.611486] j721e-pcie 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 1.619566] j721e-pcie 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 1.627647] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 1.637539] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[ 1.645075] j721e-pcie 2910000.pcie: IO 0x0018001000..0x0018010fff -> 0x0018001000
[ 1.653165] j721e-pcie 2910000.pcie: MEM 0x0018011000..0x001fffffff -> 0x0018011000
[ 1.661262] j721e-pcie 2910000.pcie: IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[ 1.669798] debugfs: Directory 'pd:39' with parent 'pm_genpd' already present!
[ 1.677111] debugfs: Directory 'pd:38' with parent 'pm_genpd' already present!
[ 1.684911] debugfs: Directory 'pd:276' with parent 'pm_genpd' already present!
[ 1.692827] debugfs: Directory 'pd:154' with parent 'pm_genpd' already present!
[ 1.707035] ALSA device list:
[ 1.710007] No soundcards found.
[ 1.713758] Waiting for root device /dev/mmcblk1p2...
[ 31.820676] tlv71033: disabling
Hi Brijesh，
Sorry
Linux will stuck when MCU 2-0 call the appGpioInit() before appIpcInit
void appInitGpio(void)
{
GPIO_v0_HwAttrs gpio_cfg;
GPIO_socGetInitCfg(0, &gpio_cfg);
gpio_cfg.baseAddr = CSL_WKUP_GPIO0_BASE;
//FCAM_96716_PWDN
gpio_cfg.intCfg[6].eventId = 0;
gpio_cfg.intCfg[6].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[6].intcMuxInEvent = 0;
gpio_cfg.intCfg[6].intcMuxOutEvent = 0;
//For RTL9068 RST
/* gpio_cfg.intCfg[7].eventId = 0;
gpio_cfg.intCfg[7].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[7].intcMuxInEvent = 0;
gpio_cfg.intCfg[7].intcMuxOutEvent = 0;
*/
//SCAM_96717A_PWDNB
gpio_cfg.intCfg[20].eventId = 0;
gpio_cfg.intCfg[20].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[20].intcMuxInEvent = 0;
gpio_cfg.intCfg[20].intcMuxOutEvent = 0;
//MAX20087_EN
gpio_cfg.intCfg[26].eventId = 0;
gpio_cfg.intCfg[26].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[26].intcMuxInEvent = 0;
gpio_cfg.intCfg[26].intcMuxOutEvent = 0;
//ADAS_VDD_1V2_EN
gpio_cfg.intCfg[30].eventId = 0;
gpio_cfg.intCfg[30].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[30].intcMuxInEvent = 0;
gpio_cfg.intCfg[30].intcMuxOutEvent = 0;
//FCAM_96717_PWDNB
gpio_cfg.intCfg[32].eventId = 0;
gpio_cfg.intCfg[32].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[32].intcMuxInEvent = 0;
gpio_cfg.intCfg[32].intcMuxOutEvent = 0;
//MAX20089_EN
gpio_cfg.intCfg[33].eventId = 0;
gpio_cfg.intCfg[33].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[33].intcMuxInEvent = 0;
gpio_cfg.intCfg[33].intcMuxOutEvent = 0;
//SCAM_96712_PWDN
gpio_cfg.intCfg[35].eventId = 0;
gpio_cfg.intCfg[35].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[35].intcMuxInEvent = 0;
gpio_cfg.intCfg[35].intcMuxOutEvent = 0;
gpio_cfg.intCfg[53].eventId = 0;
gpio_cfg.intCfg[53].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[53].intcMuxInEvent = 0;
gpio_cfg.intCfg[53].intcMuxOutEvent = 0;
gpio_cfg.intCfg[57].eventId = 0;
gpio_cfg.intCfg[57].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[57].intcMuxInEvent = 0;
gpio_cfg.intCfg[57].intcMuxOutEvent = 0;
GPIO_socSetInitCfg(0, &gpio_cfg);
GPIO_init();
GPIO_enableInt(0);
GPIO_enableInt(1);
GPIO_enableInt(2);
GPIO_enableInt(3);
GPIO_enableInt(4);
GPIO_enableInt(5);
GPIO_enableInt(6);
GPIO_enableInt(7);
GPIO_enableInt(8);
}
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
int32_t appGpioInit(void)
{
appInitGpio();
GPIO_write(0, GPIO_PIN_HIGH);
appLogPrintf(
" appGpioInit Done!!!\n");
return 0;
}
Hi Brijesh，
Please help me check, Why does MCU2-0 stuck in appGpioInit() when MCU 2-0 call the appGpioInit() before appIpcInit ?
Hi qin,
I am not sure about appGpioInit. What is this API doing? I dont see this API in the standard SDK release?
Can you please share the code of GPIO_enableInt ?
Also why do you want to move GPIO to below IPC initialization?
It should have worked, but maybe there is some conflict with Linux.
Regards,
Brijesh
Hi, Brijesh,
What is this API doing?
---> We need to have GPIO output a high-level enabling power supply to power DES. The PWDN pin of DES also needs to be set to high level
Can you please share the code of GPIO_enableInt ?
pdk_j721s2/packages/ti/drv/gpio/src/GPIO_drv.c
static void GPIO_write_v0(uint32_t idx, uint32_t value)
{
uintptr_t key;
uint32_t pinConfig;
uint32_t pinNum;
uint32_t portNum;
/* Input parameter validation */
if (((bool)true == initCalled) &&
(idx < GPIO_v0_config.numberOfPinConfigs))
{
pinConfig = GPIO_v0_config.pinConfigs[idx];
portNum = GPIO_GET_PORT_NUM(pinConfig);
pinNum = GPIO_GET_PIN_NUM(pinConfig);
if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
(pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
{
key = GPIO_osalHardwareIntDisable();
/* Clear output from pinConfig */
GPIO_v0_config.pinConfigs[idx] &= ~GPIO_CFG_OUT_HIGH;
if (value != 0U)
{
/* Set the pinConfig output bit to high */
GPIO_v0_config.pinConfigs[idx] |= GPIO_CFG_OUT_HIGH;
}
GPIOPinWrite_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, value);
GPIO_osalHardwareIntRestore(key);
}
}
}
/* GPIO function table for GPIO_v0 implementation */
const GPIO_FxnTable GPIO_FxnTable_v0 = {
&GPIO_init_v0,
&GPIO_read_v0,
&GPIO_write_v0,
&GPIO_clearInt_v0,
&GPIO_disableInt_v0,
&GPIO_enableInt_v0,
&GPIO_setCallback_v0,
&GPIO_setConfig_v0,
&GPIO_toggle_v0,
};
[ 1.713758] Waiting for root device /dev/mmcblk1p2...
But this seems to be waiting to mount the rootfs. Are you sure this was working fine below moving appGpioInit?
Also if it was, are any of the GPIOs, that you are enabling, affecting MMC interface?
Regards,
Brijesh
Are you sure this was working fine below moving appGpioInit?
--> yes
are any of the GPIOs, that you are enabling, affecting MMC interface?
--> No
Hi, Brijesh,
MCU2-0 will stuck in appGpioInit() when MCU 2-0 call the appGpioInit() before appIpcInit.
Please help me fix MCU2-0 stuck in appGpioInit() when MCU 2-0 call the appGpioInit() before appIpcInit.
We don't care if Linux can boot properly. Thank you very much
Hi,
Are any of these GPIOS enabled on Linux?
According to above, is mcu2_0 also getting stuck?
Also can you please check and confirm that GPIO module is powered on using sciclient interface?
Regards,
Brijesh
Hi Brijesh,
Are any of these GPIOS enabled on Linux?
--> How to check these GPIOS enabled on Linux ? Thank you very much
According to above, is mcu2_0 also getting stuck?
--> yes, getting stuck in appGpioInit()
Also can you please check and confirm that GPIO module is powered on using sciclient interface?
-->How to check ? Thank you very much
Hi qin,
Can you please add below code appGpioInit, before doing anything?
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO0);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO1);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO2);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO3);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO4);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO5);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO6);
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO7);
Regards,
Brijesh
Hi, Brijesh,
This will some err:
diff --git a/vision_apps/platform/j721s2/rtos/common/app_init.c b/vision_apps/platform/j721s2/rtos/common/app_init.c
index 4189dcc0d..ab2d2eeb7 100755
--- a/vision_apps/platform/j721s2/rtos/common/app_init.c
+++ b/vision_apps/platform/j721s2/rtos/common/app_init.c
@@ -101,6 +101,10 @@
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/sciclient/soc/sysfw/include/j721s2/tisci_devices.h>
+#include <utils/sciclient/include/app_sciclient_wrapper_api.h>
+#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
@@ -457,6 +461,60 @@ int32_t appInit()
status = appMemInit(&mem_init_prm);
APP_ASSERT_SUCCESS(status);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO0);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO1);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO2);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO3);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO4);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO5);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO6);
+ SET_DEVICE_STATE_ON(TISCI_DEV_GPIO7);
[TIARM] Compiling C app_init.c
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:476:22: error: use of undeclared identifier 'TISCI_DEV_GPIO1'
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO1);
^
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:476:22: error: use of undeclared identifier 'TISCI_DEV_GPIO1'
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:478:22: error: use of undeclared identifier 'TISCI_DEV_GPIO3'
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO3);
^
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:478:22: error: use of undeclared identifier 'TISCI_DEV_GPIO3'
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:480:22: error: use of undeclared identifier 'TISCI_DEV_GPIO5'
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO5);
^
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:480:22: error: use of undeclared identifier 'TISCI_DEV_GPIO5'
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:482:22: error: use of undeclared identifier 'TISCI_DEV_GPIO7'
SET_DEVICE_STATE_ON(TISCI_DEV_GPIO7);
^
/hdd/bric/P55-T_AUTOSAR_DEV/rtos-sdk/vision_apps/platform/j721s2/rtos/common/app_init.c:482:22: error: use of undeclared identifier 'TISCI_DEV_GPIO7'
Hi Brijesh,
We use gpio list:
WKUP_GPIO0_20,
WKUP_GPIO0_26,
WKUP_GPIO0_30,
WKUP_GPIO0_35,
Hi Qin,
In that case, can you please replace device with TISCI_DEV_WKUP_GPIO0 & TISCI_DEV_WKUP_GPIO1?
Essentially please refer to file soc/sysfw/include/j721s2/tisci_devices.h and power on the GPIO modules that you are using.
Regards,
Brijesh
Hi, Brijesh,
MCU2-0 is getting stuck still:
diff --git a/vision_apps/platform/j721s2/rtos/common/app_init.c b/vision_apps/platform/j721s2/rtos/common/app_init.c
index 4189dcc0d..35546a443 100755
--- a/vision_apps/platform/j721s2/rtos/common/app_init.c
+++ b/vision_apps/platform/j721s2/rtos/common/app_init.c
@@ -101,6 +101,10 @@
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/sciclient/soc/sysfw/include/j721s2/tisci_devices.h>
+#include <utils/sciclient/include/app_sciclient_wrapper_api.h>
+#include <ti/drv/sciclient/soc/sysfw/include/j721s2/tisci_devices.h>
+
app_log_shared_mem_t g_app_log_shared_mem
__attribute__ ((section(".bss:app_log_mem")))
__attribute__ ((aligned(4096)))
@@ -457,6 +461,53 @@ int32_t appInit()
status = appMemInit(&mem_init_prm);
APP_ASSERT_SUCCESS(status);
+#ifdef CPU_mcu2_0
+ #ifdef ENABLE_FVID2
+ status = appFvid2Init();
+ APP_ASSERT_SUCCESS(status);
+ #endif
+
+ #ifdef ENABLE_I2C
+ appI2cInit();
+ #endif
+
+
+ SET_DEVICE_STATE_ON(TISCI_DEV_WKUP_GPIO0);
+ SET_DEVICE_STATE_ON(TISCI_DEV_WKUP_GPIO1);
+
+ #ifdef ENABLE_GPIO
+ appGpioInit();
+ #endif
Hi Brijesh,
when add WKUP_GPIO0_20 and WKUP_GPIO0_26, then MCU2-0 is getting stuck
GPIO_PinConfig gpioPinConfigs[] =
{
GPIO_DEVICE_CONFIG(0, 20) | GPIO_CFG_IN_INT_BOTH_EDGES | GPIO_CFG_OUT_HIGH , //SCAM_96717A_PWDNB
GPIO_DEVICE_CONFIG(0, 26) | GPIO_CFG_IN_INT_BOTH_EDGES | GPIO_CFG_OUT_HIGH , //MAX20087_EN
ok, let me check with the team to figure out if these GPIOs are used for anything else.
Can you confirm that if you dont use these GPIOs, it works fine?
Also does it work fine with these GPIOs are enabled, when Linux is not running? Lets say if you stop booting at uboot, does mcu2_0 complete initialization ?
Regards,
Brijesh
Hi, Brijesh,
Can you confirm that if you dont use these GPIOs, it works fine?
---> if I do not use these GPIOs, MCU2-0 can work fine, But DES can not work fine
sensor->ser->des->display
Lets say if you stop booting at uboot, does mcu2_0 complete initialization ?
--> How to stop booting at uboot ?
Hi qin,
I think uboot has environment variable to wait for few seconds, if i remember correctly, it is set to 3 in the default sdk, so when it is waiting, if you press enter, it should go to uboot prompt and then you can check if mcu2_0 completed the initialization.
Regards,
Brijesh