PROCESSOR-SDK-J721S2: How do we need to adapt the two rank DDR? Nanya LPDDR4 NT6AN1024F32AC-J2H

zhangjun1

We replaced the DDR on the J721S2 board with Nanya LPDDR4 NT6AN1024F32AC-J2H (2 pieces 4GB) ，The log is shown in the following figure。

We have already sought confirmation from the DDR supplier regarding the parameters, but they have replied that the rank is different. How do we need to adapt the two rank DDR?

over 1 year ago

0 zhangjun1 over 1 year ago

Intellectual 260 points

How to debug one-rank to two-ranks LPDDR4 in TDA4V platform？

0 Parth Nagpal over 1 year ago in reply to zhangjun1

TI__Mastermind 42135 points

Hi,

Currently a large portion of our team is out-of-office due to Thanksgiving holiday. Please expect a delay in response time as questions will be addressed as the team returns throughout the week.

Apologies for the inconvenience and thank you for your patience.

Regards,
Parth

0 zhangjun1 over 1 year ago in reply to Parth Nagpal

Intellectual 260 points

Hi,

May I ask when Ti can reply to my question?

0 zhangjun1 over 1 year ago in reply to Parth Nagpal

Intellectual 260 points

May I ask when TI can reply?

0 zhangjun1 over 1 year ago in reply to Parth Nagpal

Intellectual 260 points

Look forward to your soonest reply.

0 Kevin S over 1 year ago in reply to zhangjun1

TI__Mastermind 32725 points

Hi,

Can you please make sure that F0 CA ODT is enabled in your configuration?

Can you also please attach the filled-in register configuration tool used to generate the settings for this device?

After the error occurs, can you please run the attached binary from the R5 (loads over JTAG through CCS) and provide the output from the CCS console window?

0677.tda4x_lp4_debug2.zip

Regards,
Kevin