DDR3 0.75V supply generation

maril

Hi All ,

In the DDR3 design guide document for keystone devices(sprabia.pdf) it is mentioned that the 0.75v supply( for terminating address and control signals) should be derived from 1.5v supply(See Fig2. Section 1.12,Pg 7). However , in the TMS320C6678L EVM the supply (0.75v) is generated from a seperate source and does not follow 1.5v .

What is the reason for this deviation ? Is it mandatory to follow the rule that 0.75v should be derived from 1.5v ?

-Anil

over 14 years ago

0 haopeng han over 14 years ago

Expert 1120 points

In a DDRx design, Vtt & Vttref should follow Vdd. Vtt here means Vtrack-termination, needs the supply can both source and sink current, you can refer to the SSTL specification for more details. In the 6678 EVM 0.75v is generated from a LDO with current sink capability----TPS51200. You can check the LDO's datasheet, the EVM design uses a REFIN and VOSNS pin to make sure that the VO is following the 1.5V Vdd.

Han

0 maril over 14 years ago in reply to haopeng han

Intellectual 560 points

Hi Han ,

Thanks for the info.

-Anil

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DDR3 0.75V supply generation