Part Number: AM6442
We have verified Wake on Lan (WOL) with following 2 patches. It is not working, there is no GPIO assertion with the magic packets.
Is there any additional PHY register setting needed to enable WOL? Similar to following link e2e.ti.com/.../linux-dp83867irpap-evm-wake-on-lan-wol-implements-on-dp83867
From 9d62c5ebb921de3f3823be6a65e3507de39fc90a Mon Sep 17 00:00:00 2001
From: Jason Reeder <jreeder@ti.com>
Date: Fri, 8 Sep 2023 14:24:12 -0600
Subject: [PATCH 1/2] net: phy: dp83867: Add DT configuration for GPIO pins
Signed-off-by: Jason Reeder <jreeder@ti.com>
---
drivers/net/phy/dp83867.c | 57 ++++++++++++++++++++++++++++
include/dt-bindings/net/ti-dp83867.h | 13 +++++++
2 files changed, 70 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 14990f846..b1bdb5777 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -51,6 +51,7 @@
#define DP83867_RXFSOP2 0x013A
#define DP83867_RXFSOP3 0x013B
#define DP83867_IO_MUX_CFG 0x0170
+#define DP83867_GPIO_MUX_CTRL 0x0172
#define DP83867_SGMIICTL 0x00D3
#define DP83867_10M_SGMII_CFG 0x016F
#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
@@ -122,6 +123,12 @@
#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
+/* GPIO_MUX_CTRL bits */
+#define DP83867_GPIO_MUX_CTRL_GPIO_1_CTRL_MASK (0xf << 4)
+#define DP83867_GPIO_MUX_CTRL_GPIO_1_CTRL_SHIFT 4
+#define DP83867_GPIO_MUX_CTRL_GPIO_0_CTRL_MASK (0xf << 0)
+#define DP83867_GPIO_MUX_CTRL_GPIO_0_CTRL_SHIFT 0
+
/* PHY STS bits */
#define DP83867_PHYSTS_1000 BIT(15)
#define DP83867_PHYSTS_100 BIT(14)
@@ -167,6 +174,10 @@ struct dp83867_private {
bool rxctrl_strap_quirk;
bool set_clk_output;
u32 clk_output_sel;
+ bool set_gpio0_output;
+ u32 gpio_0_ctrl;
+ bool set_gpio1_output;
+ u32 gpio_1_ctrl;
bool sgmii_ref_clk_en;
};
@@ -659,6 +670,40 @@ static int dp83867_of_init(struct phy_device *phydev)
return -EINVAL;
}
+ /* Optional configuration */
+ ret = of_property_read_u32(of_node, "ti,gpio-0-ctrl",
+ &dp83867->gpio_0_ctrl);
+ /* If not set, keep default */
+ if (!ret) {
+ dp83867->set_gpio0_output = true;
+ /* Valid values are 0 to DP83867_GPIO_CTRL_CONSTANT_1
+ * excluding DP83867_GPIO_CTRL_RESERVED.
+ * */
+ if (dp83867->gpio_0_ctrl > DP83867_GPIO_CTRL_CONSTANT_1 ||
+ dp83867->gpio_0_ctrl == DP83867_GPIO_CTRL_RESERVED) {
+ phydev_err(phydev, "ti,gpio-0-ctrl value %u out of range/reserved\n",
+ dp83867->gpio_0_ctrl);
+ return -EINVAL;
+ }
+ }
+
+ /* Optional configuration */
+ ret = of_property_read_u32(of_node, "ti,gpio-1-ctrl",
+ &dp83867->gpio_1_ctrl);
+ /* If not set, keep default */
+ if (!ret) {
+ dp83867->set_gpio1_output = true;
+ /* Valid values are 0 to DP83867_GPIO_CTRL_CONSTANT_1
+ * excluding DP83867_GPIO_CTRL_RESERVED.
+ * */
+ if (dp83867->gpio_1_ctrl > DP83867_GPIO_CTRL_CONSTANT_1 ||
+ dp83867->gpio_1_ctrl == DP83867_GPIO_CTRL_RESERVED) {
+ phydev_err(phydev, "ti,gpio-1-ctrl value %u out of range/reserved\n",
+ dp83867->gpio_1_ctrl);
+ return -EINVAL;
+ }
+ }
+
return 0;
}
#else
@@ -898,6 +943,18 @@ static int dp83867_config_init(struct phy_device *phydev)
mask, val);
}
+ /* GPIO output selection if GPIO muxing property is set */
+ if (dp83867->set_gpio0_output || dp83867->set_gpio1_output) {
+ u16 mask = DP83867_GPIO_MUX_CTRL_GPIO_0_CTRL_MASK;
+ mask |= DP83867_GPIO_MUX_CTRL_GPIO_1_CTRL_MASK;
+
+ val = dp83867->gpio_0_ctrl << DP83867_GPIO_MUX_CTRL_GPIO_0_CTRL_SHIFT;
+ val |= dp83867->gpio_1_ctrl << DP83867_GPIO_MUX_CTRL_GPIO_1_CTRL_SHIFT;
+
+ phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_GPIO_MUX_CTRL,
+ mask, val);
+ }
+
return 0;
}
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index 6fc4b445d..f725bfa56 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -50,4 +50,17 @@
#define DP83867_CLK_O_SEL_REF_CLK 0xC
/* Special flag to indicate clock should be off */
#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF
+
+/* GPIO_MUX_CTRL - GPIO output selection for RGZ devices */
+#define DP83867_GPIO_CTRL_RX_ER 0x0
+#define DP83867_GPIO_CTRL_COL 0x0
+#define DP83867_GPIO_CTRL_1588_TX_SFD 0x1
+#define DP83867_GPIO_CTRL_1588_RX_SFD 0x2
+#define DP83867_GPIO_CTRL_WOL 0x3
+#define DP83867_GPIO_CTRL_ENERGY_DETECT 0x4
+#define DP83867_GPIO_CTRL_RESERVED 0x5
+#define DP83867_GPIO_CTRL_LED_3 0x6
+#define DP83867_GPIO_CTRL_PRBS_ERRS_LOS 0x7
+#define DP83867_GPIO_CTRL_CONSTANT_0 0x8
+#define DP83867_GPIO_CTRL_CONSTANT_1 0x9
#endif
--
2.34.1From 42da810a5bc99f4fe9978799a5d627216cae64e2 Mon Sep 17 00:00:00 2001
From: Jason Reeder <jreeder@ti.com>
Date: Fri, 8 Sep 2023 15:18:19 -0600
Subject: [PATCH 2/2] net: phy: dp83867: Configure Wake On Lan by default
Signed-off-by: Jason Reeder <jreeder@ti.com>
---
drivers/net/phy/dp83867.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index b1bdb5777..93ad669b0 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -758,6 +758,10 @@ static int dp83867_config_init(struct phy_device *phydev)
struct dp83867_private *dp83867 = phydev->priv;
int ret, val, bs;
u16 delay;
+ struct ethtool_wolinfo wol = {
+ .wolopts = WAKE_UCAST | WAKE_BCAST | WAKE_MAGICSECURE,
+ .sopass = {0xDE, 0xAD, 0xBE, 0xEF, 0x01, 0x02},
+ };
/* Force speed optimization for the PHY even if it strapped */
ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
@@ -955,6 +959,11 @@ static int dp83867_config_init(struct phy_device *phydev)
mask, val);
}
+ /* Configure Wake On Lan by default */
+ ret = dp83867_set_wol(phydev, &wol);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.34.1
