TDA4VL-Q1: Questions about the mdio clock of main_cpsw

bing zhu

Part Number: TDA4VL-Q1

Hi, experts

According to the davinci_mdio_init_clk function, mido_clk = bus_freq,the value of bus_freq can be configured under the main_cpsw_mdio node of the device tree.

drivers/net/ethernet/ti/davinci_mdio.c

arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

So mdio_clk=1MHz, but the actual measurement is 400+KHz. Moreover, mdio_clk does not change when the value of bus_freq is modified, and the duty cycle is not 50%.

I checked the reference clock DEV_CPSW1_CPPI_CLK_CLK of mdio_clk and the clock printed out is 320MHz

What is the reason for this phenomenon? Please help analyze and answer it. Thank you.

Best Regards,

Bing

over 2 years ago

0 bing zhu over 2 years ago

Intellectual 360 points

I'm using custom boards，sdk version is 0806

0 Doredla Sudheer Kumar over 2 years ago in reply to bing zhu

TI__Guru* 79680 points

Hi,

Will be checking the same on our end, Will update you soon.

Best Regards,
Sudheer

+1 Doredla Sudheer Kumar over 2 years ago in reply to Doredla Sudheer Kumar

TI__Guru* 79680 points

Hi,

Sorry for delayed response.

MDIO is configured by default in Manual Mode due to MDIO Errata I2329. It is like controlling MDIO Pins as GPIOs and toggling as per data.
Please refer to below, by default Manual Mode is enabled. (below will be used during Probe.

Callbacks registered for Manual Mode will be bitbang APIs. Finally read will be from "mdiobb_read"

Please refer to "mdiobb_read" from Linux bitbang frame work. Which calls "mdiobb_get_bit", where we are toggling clock and reading the MDIO Data line.
There it used constant delay "MDIO_DELAY".

So, Finally as per above MDIO clock frequency can't be configurable. Also, it will not use the value configured from device tree.

Best Regards,
Sudheer

0 bing zhu over 2 years ago in reply to Doredla Sudheer Kumar

Intellectual 360 points

Hi,

MDIO_DELAY is only called twice in the mdiobb_send_bit function. Why is there three delays measured in one cycle?

Where does the third delay come from? I see that there is no delay in the ops->set_mdio_datat and mdiobb_send_num functions.

0 Doredla Sudheer Kumar over 2 years ago in reply to bing zhu

TI__Guru* 79680 points

Hi,

Above might have transaction delay of MDIO data & MDC lanes which might be causing for such trace.
Also, we may not guaranty that will always get same delay it can extend if any interrupt occurs on the processor while executing this.

Best Regards,
Sudheer

0 bing zhu over 2 years ago in reply to Doredla Sudheer Kumar

Intellectual 360 points

Hi,Sudheer

I understand now, thank you

Best Regards,

Bing

Processors

Processors forum

TDA4VL-Q1: Questions about the mdio clock of main_cpsw