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GPMC with SRAM

Michi Yamamoto
Intellectual 610 points
Other Parts Discussed in Thread: AM3505, AM3517

Hi,

I have a quesion regarding SRAM connection using GPMC of AM3505.


According to the AM35x Technical Reference manual, the external memory interfaces support only limited address(2Kbytes) with no-mux mode.
If user would like to use a larger size SRAM, user can use an external latch to get the address un-muxed from the GPMC same as non-mux NOR flash, doesn't it?

  • 0
    Prodigy 175 points

    Michi Yamamoto said:
    If user would like to use a larger size SRAM, user can use an external latch to get the address un-muxed from the GPMC same as non-mux NOR flash, doesn't it?

    I see no immediate reason why you could not use an external logic device to make an unmuxed SRAM look like a muxed SRAM to the GPMC (though I also do not know of any example implementations), a relatively small CPLD should be able to do this easily, or a FPGA if you have one on board. 

  • 0 in reply to Bernie Thompson
    Intellectual 380 points

    Hello Bernie Thompson,

     

    Even I have similar kind of doubt regarding GPMC with external SRAM.

     

    When using external SRAM, is it true that the processor supports only 2 kB memory?

    and external latch may be used for more than 2KB?

     

    The below wiki page says that  in SRAM 

    "the address and data buses are directly accessible rather than multiplexed"

    http://en.wikipedia.org/wiki/Static_random-access_memory#Hobbyists

     

    Regards.

  • 0 in reply to mudigere
    Prodigy 175 points

    mudigere said:

    When using external SRAM, is it true that the processor supports only 2 kB memory?

    and external latch may be used for more than 2KB?

    That is right, there are just not enough separate address lines available for larger memories, so if your memory has separate address and data signals with no multiplexing only a small portion can be addressed directly, the rest would have to be accessed through some other means such as GPIO based paging (i.e. connect the upper address bits of the SRAM to GPIO and control them with software) or using a multiplexed mode with external logic (i.e. latches) to generate the separate address bus. 

  • 0
    Prodigy 190 points

    Hi all,

    I have other question for regarding SRAM connection using GPMC of AM3505 with mux mode.

    I need  regarding SRAM (512KB) using GPMC, but i have no idea for programming to AM3505,

    I has study wiki and AM35x Technical documents, but  it is for NAND.

    Has anyone experience to programming or setting SRAM for AM3505 or AM3517?

    thanks