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AM623: eMMC clock output

Amílcar Barca
Prodigy 70 points

Part Number: AM623

Hi,

I would like to know if, once the eMMC interface is configured, the CLK signal is generated continuously or only when performing accesses to the eMMC memory. The eMMC memory autorefresh requires that the CLK signal be generated continuously.

  • 0
    TI__Guru 64295 points

    The eMMC standard allows the host to stop the clock during read operations. The host controller implemented in AM62x uses this feature when the internal buffer is full. In these circumstances, the host controller will stop the clock in order to avoid buffer overrun condition.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 70 points

    Hi,

    If I would need the eMMC to do all the housekeeping tasks, the CLK of the eMMC interface needs to remain active. It would be necessary that it be generated even if no write or read accesses are made on the eMMC. Is it possible?

    Regards

  • 0 in reply to Amílcar Barca
    TI__Guru 64295 points

    I do not understand your question. 

    From my understanding, the clock will be present as long as the receive buffer in the host never fills, where it pauses read operations by stopping the clock.

    It is not clear how you would be able to manage that in an operating system that is servicing many peripheral cues.

    I'm not an expert on the eMMC protocol or the software driver. My experience is mostly limited to signal integrity and timing of the eMMC peripheral signals. Your questions appear to be heading down the path of understand how the eMMC software operates. If so, I will need to assign this thread to one of our software experts.

    What software is being used in your system?

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 70 points

    Hi,

    eMMCs have built-in mechanisms to maintain the memory cells that need to be refreshed at regular intervals to prevent them from losing their contents. This is an especially important thing to take into account when the board is required to operate at high temperatures and with critical data.
    For this to work properly, the eMMC must receive an uninterrupted CLK signal.
    We are currently in the hardware design phase of this board and will be using linux as the operating system.

    Regards.

  • 0 in reply to Amílcar Barca
    TI__Guru 64295 points

    What type of eMMC device you are using? It sounds like it implements dynamic memory rather than NAND memory. Most eMMC devices use NAND memory which do not require refresh cycles.

    I'm not aware of a way to eliminate the possibility of clock stopping. Stopping the clock to prevent buffer over run is fundamental to the standard mode operation for the eMMC peripheral.

    Regards,
    Paul