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TMS320C6655: GPIO INTERRUPT ACCESS

Thilak Ram
Intellectual 480 points
Part Number: TMS320C6655

Hi,

   I am using TMS320C6655 Custom Board.I am able to access Corepac primary interrupts and work on it.

If i need to use Gpio 16 to Gpio 31 as an Interrupt.I need to configure the Corepac secondary interrupt.

Is there any sample or reference for accessing the secondary interrupts and dma end interrupts configuration.

 

Please let know the code procedure.

Regards,

Thilak

  • 0
    TI__Mastermind 25535 points

    Thilak,

    Usually, we will not find any sample for the particular use case like this.

    However we have samples for CIC - Chip interrupt controller

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    For this, the CIC doc plays a vital role along with EDMA3 app note.

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    Please have a glance at these details. - page no 10 :- https://www.ti.com/lit/ug/sprugw4a/sprugw4a.pdf

    The KeyStone Architecture has many peripherals and a large number of event sources. The use of events is completely dependent on a user's specific application, which, therefore, drives a need for maximum flexibility in which event sources are used in the system. It is also completely up to software control as to how interrupts or events are serviced. Both the EDMA3 channel controllers (EDMA3CC) and the C66x CorePac are capable of receiving events directly. 

    A KeyStone device can have hundreds of events. Therefore, some of these events need to be aggregated at the chip level through the interrupt controller (the chip-level interrupt controller (CIC)— not the interrupt controller inside a C66x CorePac) before they are routed to the EDMA3CC and C66x CorePacs. To achieve the requirement, some new chip-level interrupt controllers are added to the SoC. The CIC takes chip-level events (system events) and generates event inputs to the EDMA3CC and C66x CorePac by combining and/or selecting those chip-level events.

    The C66x CorePac internal interrupt controller allows a large number of system events to be used by C66x CorePac and any of these system events to be routed to up to 12 maskable interrupts. It also lets any of these system events be grouped together for a single exception input to the CorePac and allows any of these system events to be an AEG trigger. The EDMA3CC supports up to 64 events and there is event detection logic that recognizes the EDMA3CC system events. 

    --

    Let me also look at....

    Regards

    Shankari G