PROCESSOR-SDK-J721E: J721e RGMII5 connect with a eth phy 88E1512

Hi,

RGMII is part of Main CPSW, To be defined in Main Domain not in MCU Domain.
Can you refer to TI FAQ, and below E2E thread, customer has enabled few ports of Main CPSW in Linux using FAQ [How to move to Native Linux driver for CPSWnG]
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1295099/tda4vm-cpsw0-is-unable-to-ping-to-the-external-network

Best Regards,
Sudheer

Hi Shawn,

If you have any queries, please post here.
Please don't post queries in other threads.
Above E2E thread, I have shared for your refence only.

Best Regards,
Sudheer

Hello Sudheer,

I followed steps in this FAQ [How to move to Native Linux Driver on SDK 8.4 for J7 and DRA8 Devices], I downloaded k3-j721e-gesi-exp-board.dtbo and placeed into /rootfs/boot/ folder in SD card, and modified uenv.txt with adding "name_overlays=k3-j721e-gesi-exp-board.dtbo".

Then boot with SD card, I got a ERROR message "ERROR: Did not find a cmdline Flattened Device Tree Could not find a valid device tree".

Could you please help me to solve this issue?

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
43 bytes read in 9 ms (3.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 807 ms (22.8 MiB/s)
98389 bytes read in 15 ms (6.3 MiB/s)
4531 bytes read in 12 ms (368.2 KiB/s)
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
=>

Thank you very much!

Best Regards,

Shawn

Hi, 

shawn lin said:

 I downloaded k3-j721e-gesi-exp-board.dtbo and placeed into /rootfs/boot/ folder in SD card, and modified uenv.txt with adding "name_overlays=k3-j721e-gesi-exp-board.dtbo".

May I know from where you have downloaded the dtbo file. The default gesi configuration is for ports 1,3,4,8 as per TI EVM connections. 

As your configuration is different, you have to modify accordingly. 

Please refer to dts file in the FAQ, for reference of cpsw nodes. Modify the dts as per your requirement and use it. 

If you have already updated dts as per your requirement, plz share with us for review once. 

Best Regards, 

Sudheer

Hi Sudheer,

Thank you for your reply.

In the begining, I used the dtbo which provided from you in FAQ, the log was shown in previous post.

Then, I downloaded the dts and modified for RGMII5,

// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
                ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
				ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
				ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
				ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default
		     &rgmii5_pins_default>;
};

&cpsw0_port1 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};

&cpsw0_port3 {
	status = "disabled";
};

&cpsw0_port4 {
	status = "disabled";
};

&cpsw0_port2 {
	status = "disabled";
};

&cpsw0_port5 {
	phy-handle = <&cpsw9g_phy0>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 5>;
};

&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};


&cpsw9g_mdio {
	bus_freq = <1000000>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw9g_virt_mac {
	status = "disabled";
};

&exp1 {
	p15-hog {
		/* P15 - EXP_MUX2 */
		gpio-hog;
		gpios = <13 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX2";
	};

	p16-hog {
		/* P16 - EXP_MUX3 */
		gpio-hog;
		gpios = <14 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX3";
	};
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio_pins_default: mdio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	rgmii5_pins_default: rgmii5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x184, PIN_INPUT, 0) /* (T23) RGMII5_RD0 */
			J721E_IOPAD(0x180, PIN_INPUT, 0) /* (R23) RGMII5_RD1 */
			J721E_IOPAD(0x17c, PIN_INPUT, 0) /* (U24) RGMII5_RD2 */
			J721E_IOPAD(0x178, PIN_INPUT, 0) /* (U27) RGMII5_RD3 */
			J721E_IOPAD(0x174, PIN_INPUT, 0) /* (U25) RGMII5_RXC */
			J721E_IOPAD(0x15c, PIN_INPUT, 0) /* (U26) RGMII5_RX_CTL */
			J721E_IOPAD(0x16c, PIN_OUTPUT, 0) /* (U28) RGMII5_TD0 */
			J721E_IOPAD(0x168, PIN_OUTPUT, 0) /* (V27) RGMII5_TD1 */
			J721E_IOPAD(0x164, PIN_OUTPUT, 0) /* (V29) RGMII5_TD2 */
			J721E_IOPAD(0x160, PIN_OUTPUT, 0) /* (V28) RGMII5_TD3 */
			J721E_IOPAD(0x170, PIN_OUTPUT, 0) /* (U29) RGMII5_TXC */
			J721E_IOPAD(0x158, PIN_OUTPUT, 0) /* (U23) RGMII5_TX_CTL */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};

&cpsw0_phy_gmii_sel {
    ti,qsgmii-main-ports = <2>, <4>;
};

Then the boot log also showed "ERROR: Did not find a cmdline Flattened Device Tree Could not find a valid device tree"

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
42 bytes read in 9 ms (3.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 815 ms (22.6 MiB/s)
98024 bytes read in 17 ms (5.5 MiB/s)
4288 bytes read in 14 ms (298.8 KiB/s)
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
=>

Could you please help me check if there are any errors in DTS?

Thank you very much!!

Best Regards,

Shawn

Hi Shawn,

From logs it seems u-boot itself not completed successfully.

Can you please check changes made in u-boot, against TI SDK offering.

Also, FAQ pointed above is for enabling Linux Native driver for CPSW9G, it was for accessing of CPSW9G from Linux not from u-boot.

Best Regards,
Sudheer

Hello Sudheer,

What I did is placed k3-j721e-gesi-exp-board.dtbo into /rootfs/boot/ folder in SD card, and modified uenv.txt(which is in boot partition of the SD Card) with adding "name_overlays=k3-j721e-gesi-exp-board.dtbo", did not change other settings.

Then, it boot failed.

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
42 bytes read in 9 ms (3.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 815 ms (22.6 MiB/s)
98024 bytes read in 17 ms (5.5 MiB/s)
4288 bytes read in 14 ms (298.8 KiB/s)
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
=>

Then, I tried to delete "name_overlays=k3-j721e-gesi-exp-board.dtbo" in uenv.txt (keep the file blank), and it could boot successfully.

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
0 bytes read in 3 ms (0 Bytes/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 818 ms (22.5 MiB/s)
98024 bytes read in 20 ms (4.7 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fee5000, end 000000008fffffff ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 5.10.100 (root@aep-COMPAL-SERVER) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Sun Dec 3 00:06:29 CST 2023
[    0.000000] Machine model: Texas Instruments K3 J721E SoC
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 2 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-queues@ac000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac200000, size 30 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-buffers@ac200000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a8ffffff]
[    0.000000]   node   0: [mem 0x00000000a9000000-0x00000000a9ffffff]
[    0.000000]   node   0: [mem 0x00000000aa000000-0x00000000abbfffff]
[    0.000000]   node   0: [mem 0x00000000abc00000-0x00000000abffffff]
[    0.000000]   node   0: [mem 0x00000000ac000000-0x00000000adffffff]
[    0.000000]   node   0: [mem 0x00000000ae000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] cma: Reserved 512 MiB at 0x00000000e0000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 2 pages/cpu s49880 r8192 d73000 u131072
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: EL2 vector hardening
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 65472
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs) root=PARTUUID=5a8abaf6-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 6, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 5, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x00000000dc000000-0x00000000e0000000] (64MB)
[    0.000000] Memory: 3339136K/4194304K available (10880K kernel code, 1290K rwdata, 4352K rodata, 1856K init, 748K bss, 330880K reserved, 524288K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: 16 PPIs implemented
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: allocated 1048576 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008800b0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008800c0000
[    0.000000] random: get_random_bytes called from start_kernel+0x31c/0x4c4 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008347] Console: colour dummy device 80x25
[    0.012907] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023577] pid_max: default: 32768 minimum: 301
[    0.028326] LSM: Security Framework initializing
[    0.033069] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.040636] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.049581] rcu: Hierarchical SRCU implementation.
[    0.054641] Platform MSI: msi-controller@1820000 domain created
[    0.060864] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.070156] EFI services will not be available.
[    0.074902] smp: Bringing up secondary CPUs ...
[    0.080141] Detected PIPT I-cache on CPU1
[    0.080165] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.080175] GICv3: CPU1: using allocated LPI pending table @0x00000008800d0000
[    0.080209] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.080264] smp: Brought up 1 node, 2 CPUs
[    0.109611] SMP: Total of 2 processors activated.
[    0.114416] CPU features: detected: 32-bit EL0 Support
[    0.119671] CPU features: detected: CRC32 instructions
[    0.133392] CPU: All CPU(s) started at EL2
[    0.137587] alternatives: patching kernel code
[    0.142593] devtmpfs: initialized
[    0.150754] KASLR disabled due to lack of seed
[    0.155404] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.165366] futex hash table entries: 512 (order: -1, 32768 bytes, linear)
[    0.173040] pinctrl core: initialized pinctrl subsystem
[    0.178611] DMI not present or invalid.
[    0.182833] NET: Registered protocol family 16
[    0.190265] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.197564] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.205566] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.213868] thermal_sys: Registered thermal governor 'step_wise'
[    0.213871] thermal_sys: Registered thermal governor 'power_allocator'
[    0.220274] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.233917] ASID allocator initialised with 65536 entries
[    0.254879] HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages
[    0.261734] HugeTLB registered 512 MiB page size, pre-allocated 0 pages
[    0.268492] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.276269] cryptd: max_cpu_qlen set to 1000
[    0.282283] k3-chipinfo 43000014.chipid: Family:J721E rev:SR2.0 JTAGID[0x1bb6402f] Detected
[    0.291077] vsys_3v3: supplied by evm_12v0
[    0.295437] vsys_5v0: supplied by evm_12v0
[    0.299747] vdd_mmc1: supplied by vsys_3v3
[    0.304428] iommu: Default domain type: Translated
[    0.309559] SCSI subsystem initialized
[    0.313671] mc: Linux media interface: v0.10
[    0.318047] videodev: Linux video capture interface: v2.00
[    0.323675] pps_core: LinuxPPS API ver. 1 registered
[    0.328746] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.338083] PTP clock support registered
[    0.342103] EDAC MC: Ver: 3.0.0
[    0.345831] FPGA manager framework
[    0.349341] Advanced Linux Sound Architecture Driver Initialized.
[    0.355928] clocksource: Switched to clocksource arch_sys_counter
[    0.362353] VFS: Disk quotas dquot_6.6.0
[    0.366398] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[    0.376103] NET: Registered protocol family 2
[    0.380688] IP idents hash table entries: 65536 (order: 3, 524288 bytes, linear)
[    0.389312] tcp_listen_portaddr_hash hash table entries: 4096 (order: 0, 65536 bytes, linear)
[    0.398081] TCP established hash table entries: 32768 (order: 2, 262144 bytes, linear)
[    0.406275] TCP bind hash table entries: 32768 (order: 3, 524288 bytes, linear)
[    0.414217] TCP: Hash tables configured (established 32768 bind 32768)
[    0.420971] UDP hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.427862] UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.435247] NET: Registered protocol family 1
[    0.439949] RPC: Registered named UNIX socket transport module.
[    0.446009] RPC: Registered udp transport module.
[    0.450813] RPC: Registered tcp transport module.
[    0.455615] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.462198] PCI: CLS 0 bytes, default 64
[    0.466529] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.476811] Initialise system trusted keyrings
[    0.481430] workingset: timestamp_bits=46 max_order=16 bucket_order=0
[    0.489672] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.495888] NFS: Registering the id_resolver key type
[    0.501109] Key type id_resolver registered
[    0.505382] Key type id_legacy registered
[    0.509500] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.516349] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.523987] 9p: Installing v9fs 9p2000 file system support
[    0.548409] Key type asymmetric registered
[    0.552595] Asymmetric key parser 'x509' registered
[    0.557592] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[    0.565151] io scheduler mq-deadline registered
[    0.569776] io scheduler kyber registered
[    0.575020] pinctrl-single 4301c000.pinctrl: 94 pins, size 376
[    0.581183] pinctrl-single 11c000.pinctrl: 173 pins, size 692
[    0.589552] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.595823] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.603618] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.611646] arm-smmu-v3 36600000.iommu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    0.620629] arm-smmu-v3 36600000.iommu: allocated 524288 entries for cmdq
[    0.629467] arm-smmu-v3 36600000.iommu: allocated 524288 entries for evtq
[    0.637191] arm-smmu-v3 36600000.iommu: msi_domain absent - falling back to wired irqs
[    0.650119] brd: module loaded
[    0.656044] loop: module loaded
[    0.659825] megasas: 07.714.04.00-rc1
[    0.665226] tun: Universal TUN/TAP device driver, 1.6
[    0.670649] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.677057] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.683128] sky2: driver version 1.30
[    0.687367] VFIO - User Level meta-driver version: 0.3
[    0.693012] i2c /dev entries driver
[    0.697167] sdhci: Secure Digital Host Controller Interface driver
[    0.703486] sdhci: Copyright(c) Pierre Ossman
[    0.708176] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.714486] ledtrig-cpu: registered to indicate activity on CPUs
[    0.720780] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.727885] optee: probing for conduit method.
[    0.732439] optee: revision 3.12 (3d47a131)
[    0.732676] optee: initialized driver
[    0.742075] NET: Registered protocol family 17
[    0.746683] 9pnet: Installing 9P2000 support
[    0.751067] Key type dns_resolver registered
[    0.755509] Loading compiled-in X.509 certificates
[    0.764377] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.770708] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.778960] ti-sci 44083000.dmsc: ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
[    0.808098] random: fast init done
[    0.838374] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    0.844715] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    0.852737] omap_i2c 40b00000.i2c: bus 0 rev0.12 at 100 kHz
[    0.858815] omap_i2c 40b10000.i2c: bus 1 rev0.12 at 100 kHz
[    0.864886] omap_i2c 42120000.i2c: bus 2 rev0.12 at 100 kHz
[    0.871123] pca953x 3-0020: supply vcc not found, using dummy regulator
[    0.877939] pca953x 3-0020: using no AI
[    0.903972] pca953x 3-0020: failed writing register
[    0.909005] pca953x: probe of 3-0020 failed with error -121
[    0.914906] pca953x 3-0022: supply vcc not found, using dummy regulator
[    0.921703] pca953x 3-0022: using AI
[    0.925405] pca953x 3-0022: failed writing register
[    0.930425] pca953x: probe of 3-0022 failed with error -121
[    0.936165] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz
[    0.942224] omap_i2c 2010000.i2c: bus 4 rev0.12 at 400 kHz
[    0.948214] omap_i2c 2020000.i2c: bus 5 rev0.12 at 100 kHz
[    0.954324] pca953x 6-0020: supply vcc not found, using dummy regulator
[    0.961135] pca953x 6-0020: using no AI
[    0.987973] pca953x 6-0020: failed writing register
[    0.993001] pca953x: probe of 6-0020 failed with error -121
[    0.999912] omap_i2c 2030000.i2c: bus 6 rev0.12 at 400 kHz
[    1.005987] omap_i2c 2040000.i2c: bus 7 rev0.12 at 100 kHz
[    1.011979] omap_i2c 2050000.i2c: bus 8 rev0.12 at 100 kHz
[    1.017941] omap_i2c 2060000.i2c: bus 9 rev0.12 at 100 kHz
[    1.024362] ti-sci-intr bus@100000:bus@28380000:interrupt-controller2: Interrupt Router 137 domain created
[    1.034399] ti-sci-intr bus@100000:interrupt-controller0: Interrupt Router 131 domain created
[    1.043208] ti-sci-intr bus@100000:main-navss:interrupt-controller1: Interrupt Router 213 domain created
[    1.053052] ti-sci-inta 33d00000.interrupt-controller: Interrupt Aggregator domain 209 created
[    1.072783] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    1.082664] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.089422] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.098301] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.108457] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.115216] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.123156] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 15, base_baud = 6000000) is a 8250
[    1.132523] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 28, base_baud = 3000000) is a 8250
[    1.141264] printk: console [ttyS2] enabled
[    1.141264] printk: console [ttyS2] enabled
[    1.149699] printk: bootconsole [ns16550a0] disabled
[    1.149699] printk: bootconsole [ns16550a0] disabled
[    1.160163] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 29, base_baud = 3000000) is a 8250
[    1.169090] 2840000.serial: ttyS6 at MMIO 0x2840000 (irq = 30, base_baud = 3000000) is a 8250
[    1.179444] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    1.189954] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    1.200107] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    1.210346] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[    1.221218] scsi host0: ufshcd
[    1.267937] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.276011] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.282736] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.296539] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    1.305385] mmc0: CQHCI version 5.10
[    1.305530] mmc1: CQHCI version 5.10
[    1.312731] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.318926] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    1.331535] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    1.338386] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    1.345224] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    1.347939] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    1.352050] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    1.366152] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    1.376611] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    1.387351] ti-udma 31150000.dma-controller: Channels: 122 (tchan: 61, rchan: 61, gp-rflow: 16)
[    1.401543] spi-nor spi2.0: mt35xu512aba (65536 Kbytes)
[    1.406779] 8 cmdlinepart partitions found on MTD device 47040000.spi.0
[    1.413385] Creating 8 MTD partitions on "47040000.spi.0":
[    1.418863] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    1.424858] 0x000000080000-0x000000280000 : "ospi.tispl"
[    1.430561] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    1.436352] 0x000000680000-0x0000006c0000 : "ospi.env"
[    1.441866] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    1.447516] 0x0000007c0000-0x000000800000 : "ospi.env.backup"
[    1.453660] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    1.459419] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
[    1.468015] spi-nor spi3.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
[    1.474884] spi-nor: probe of spi3.0 failed with error -2
[    1.488245] mmc0: Command Queue Engine enabled
[    1.492686] mmc0: new HS200 MMC card at address 0001
[    1.497934] mmcblk0: mmc0:0001 S0J56X 14.8 GiB
[    1.502565] mmcblk0boot0: mmc0:0001 S0J56X partition 1 31.5 MiB
[    1.508569] mmcblk0boot1: mmc0:0001 S0J56X partition 2 31.5 MiB
[    1.514551] mmcblk0rpmb: mmc0:0001 S0J56X partition 3 4.00 MiB, chardev (237:0)
[    1.519942] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.529957] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.536737] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.550390] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    1.557420] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.564630] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.570950] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:0
[    1.581154] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.595952] debugfs: Directory 'pd:27' with parent 'pm_genpd' already present!
[    1.603199] debugfs: Directory 'pd:26' with parent 'pm_genpd' already present!
[    1.611435] debugfs: Directory 'pd:242' with parent 'pm_genpd' already present!
[    1.618755] debugfs: Directory 'pd:241' with parent 'pm_genpd' already present!
[    1.626060] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present!
[    1.633368] debugfs: Directory 'pd:239' with parent 'pm_genpd' already present!
[    1.641699] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    1.661867] ALSA device list:
[    1.662972] cdns-ufshcd 4e84000.ufs: link startup failed 1
[    1.664839]   #0: j721e-cpb
[    1.670310] cdns-ufshcd 4e84000.ufs: UFS Host state=0
[    1.678140] cdns-ufshcd 4e84000.ufs: outstanding reqs=0x0 tasks=0x0
    1.684393] cdns-ufshcd 4e84000.ufs: saved_err=0x0, saved_uic_err=0x0
[    1.690732] cdns-ufshcd 4e84000.ufs: Device power mode=1, UIC link state=0
[    1.697594] cdns-ufshcd 4e84000.ufs: PM in progress=0, sys. suspended=0
[    1.704193] cdns-ufshcd 4e84000.ufs: Auto BKOPS=0, Host self-block=0
[    1.710531] cdns-ufshcd 4e84000.ufs: Clk gate=1
[    1.715049] cdns-ufshcd 4e84000.ufs: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0
[    1.723209] cdns-ufshcd 4e84000.ufs: last intr at 1550107 us, last intr status=0x404
[    1.730933] cdns-ufshcd 4e84000.ufs: error handling flags=0x0, req. abort count=0
[    1.738397] cdns-ufshcd 4e84000.ufs: hba->ufs_version=0x210, Host capabilities=0x1587031f, caps=0x0
[    1.747420] cdns-ufshcd 4e84000.ufs: quirks=0x0, dev. quirks=0x0
[    1.753411] cdns-ufshcd 4e84000.ufs: clk: core_clk, rate: 250000000
[    1.759662] cdns-ufshcd 4e84000.ufs: clk: phy_clk, rate: 19200000
[    1.765739] cdns-ufshcd 4e84000.ufs: clk: ref_clk, rate: 19200000
[    1.771818] cdns-ufshcd 4e84000.ufs: ufshcd_print_pwr_info:[RX, TX]: gear=[0, 0], lane[0, 0], pwr[INVALID MODE, INVALID MODE], rate = 0
[    1.783980] host_regs: 00000000: 1587031f 00000000 00000210 00000000
[    1.790317] host_regs: 00000010: 00000000 00000000 00000000 00000000
[    1.796655] host_regs: 00000020: 00000000 00000470 00000000 00000000
[    1.802992] host_regs: 00000030: 00000008 00000001 00000000 00000000
[    1.809329] host_regs: 00000040: 00000000 00000000 00000000 00000000
[    1.815666] host_regs: 00000050: 00000000 00000000 00000000 00000000
[    1.822006] host_regs: 00000060: 00000000 00000000 00000000 00000000
[    1.828346] host_regs: 00000070: 00000000 00000000 00000000 00000000
[    1.834682] host_regs: 00000080: 00000000 00000000 00000000 00000000
[    1.841019] host_regs: 00000090: 00000000 00000000 00000000 00000000
[    1.847359] cdns-ufshcd 4e84000.ufs: No record of pa_err
[    1.852657] cdns-ufshcd 4e84000.ufs: No record of dl_err
[    1.857954] cdns-ufshcd 4e84000.ufs: No record of nl_err
[    1.863251] cdns-ufshcd 4e84000.ufs: No record of tl_err
[    1.868548] cdns-ufshcd 4e84000.ufs: No record of dme_err
[    1.873932] cdns-ufshcd 4e84000.ufs: No record of auto_hibern8_err
[    1.880095] cdns-ufshcd 4e84000.ufs: No record of fatal_err
[    1.885652] cdns-ufshcd 4e84000.ufs: link_startup_fail[0] = 0x1 at 1563047 us
[    1.892770] cdns-ufshcd 4e84000.ufs: No record of resume_fail
[    1.898501] cdns-ufshcd 4e84000.ufs: No record of suspend_fail
[    1.904319] cdns-ufshcd 4e84000.ufs: No record of dev_reset
[    1.909876] cdns-ufshcd 4e84000.ufs: No record of host_reset
[    1.915519] cdns-ufshcd 4e84000.ufs: No record of task_abort
[    2.374758] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    2.383052] Waiting for root device PARTUUID=5a8abaf6-02...
[    2.419986] mmc1: Problem switching card into high-speed mode!
[    2.425914] mmc1: new SDHC card at address 0001
[    2.430750] mmcblk1: mmc1:0001 ASTC 7.37 GiB
[    2.442360]  mmcblk1: p1 p2
[    3.886756] EXT4-fs (mmcblk1p2): recovery complete
[    3.896785] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[    3.904897] VFS: Mounted root (ext4 filesystem) on device 179:98.
[    3.915608] devtmpfs: mounted
[    3.918860] Freeing unused kernel memory: 1856K
[    3.923411] Run /sbin/init as init process
[    4.543763] systemd[1]: System time before build time, advancing clock.
[    4.638176] systemd[1]: systemd 244.5+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[    4.659887] systemd[1]: Detected architecture arm64.

Welcome to Arago 2021.09!

[    4.697633] systemd[1]: Set hostname to <j7-evm>.
[    5.201630] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    5.210520] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    5.259571] systemd[1]: /lib/systemd/system/docker.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/docker.sock → /run/docker.sock; please update the unit file accordingly.
[    5.408014] random: systemd: uninitialized urandom read (16 bytes read)
[    5.414723] systemd[1]: system-getty.slice: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
[    5.427049] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
[    5.436931] systemd[1]: Created slice system-getty.slice.
[  OK  ] Created slice system-getty.slice.
[    5.460009] random: systemd: uninitialized urandom read (16 bytes read)
[    5.467249] systemd[1]: Created slice system-serial\x2dgetty.slice.
[  OK  ] Created slice system-serial\x2dgetty.slice.
[    5.487997] random: systemd: uninitialized urandom read (16 bytes read)
[    5.495131] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    5.516099] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password …ts to Console Directory Watch.
[    5.540033] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password R…uests to Wall Directory Watch.
[    5.564034] systemd[1]: Reached target Paths.
[  OK  ] Reached target Paths.
[    5.579988] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    5.599980] systemd[1]: Reached target Slices.
[  OK  ] Reached target Slices.
[    5.615983] systemd[1]: Reached target Swap.
[  OK  ] Reached target Swap.
[    5.635963] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    5.660003] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    5.683683] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    5.704114] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    5.743622] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
[    5.751952] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    5.772201] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    5.788263] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    5.812154] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    5.832090] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    5.854206] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    5.870433] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.894420] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.924740] systemd[1]: Mounting Temporary Directory (/tmp)...
         Mounting Temporary Directory (/tmp)...
[    5.940112] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped.
[    5.954059] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    5.981032] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    6.000114] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[    6.012439] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    6.058819] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    6.078565] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems...
[    6.094534] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
[    6.106372] systemd[1]: Starting udev Coldplug all Devices...
         Starting udev Coldplug all Devices...
[    6.134284] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    6.156282] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[  OK  ] Started Remount Root and Kernel File Systems.
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
[    6.379501] systemd-journald[175]: Received client request to flush runtime journal.
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create Static Device Nodes in /dev.
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram...
         Mounting /var/volatile...
         Starting udev Kernel Device Manager...
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Mounted /media/ram.
[  OK  ] Mounted /var/volatile.
         Starting udev Wait for Complete Device Initialization...
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Create Volatile Files and Directories.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target System Time Synchronized.
         Starting Update UTMP about System Boot/Shutdown...
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
         Starting Start psplash boot splash screen...
         Starting Load Kernel Modules...
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[    8.955974] random: crng init done
[    8.959374] random: 7 urandom warning(s) missed due to ratelimiting
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Created slice system-systemd\x2dfsck.slice.
[  OK  ] Found device /dev/mmcblk1p1.
         Starting File System Check on /dev/mmcblk1p1...
[  OK  ] Started udev Wait for Complete Device Initialization.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timers.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API.
[  OK  ] Listening on dropbear.socket.
         Starting Reboot and dump vmcore via kexec...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
         Starting Save/Restore Sound Card State...
[  OK  ] Started Job spooling tools.
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started D-Bus System Message Bus.
         Starting Print notice about GPLv3 packages...
         Starting set host name as per compatible name...
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
[  OK  ] Started irqbalance daemon.
         Starting Telephony service...
         Starting rc.pvr.service...
         Starting startwlanap...
         Starting startwlansta...
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started TEE Supplicant.
         Starting Update weston ini… based on the platform name...
[  OK  ] Started Reboot and dump vmcore via kexec.
[  OK  ] Started Save/Restore Sound Card State.
[  OK  ] Reached target Sound Card.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started startwlansta.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started File System Check on /dev/mmcblk1p1.
[  OK  ] Started set host name as per compatible name.
[  OK  ] Started IPv6 Packet Filtering Framework.
[  OK  ] Started IPv4 Packet Filtering Framework.
[  OK  ] Started rc.pvr.service.
[  OK  ] Started startwlanap.
[  OK  ] Started Update weston ini …ge based on the platform name.
[  OK  ] Started Telephony service.
[  OK  ] Reached target Network (Pre).
         Mounting /run/media/mmcblk1p1...
         Starting Network Service...
         Starting weston.service...
[  OK  ] Started weston.service.
         Starting DEMO...
         Starting telnetd.service...
[  OK  ] Started DEMO.
[  OK  ] Started telnetd.service.
[  OK  ] Started Network Service.
         Starting Wait for Network to be Configured...
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Reached target Ne[   10.987184] am65-cpsw-nuss 46000000.ethernet: phy /bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0 not found on slave 1
twork.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
         Starting Enable and configure wl18xx bluetooth stack...
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting Simple Network Ma…ent Protocol (SNMP) Daemon....
         Starting Permit User Sessions...
[  OK  ] Mounted /run/media/mmcblk1p1.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Serial Getty on ttyS3.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Enable and configure wl18xx bluetooth stack.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Simple Network Man…ement Protocol (SNMP) Daemon..
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
        autoconf
        bash-dev
        bash
        bc
        binutils
        cifs-utils
        coreutils-stdbuf
        coreutils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbserver
        gettext
        glmark2
        gstreamer1.0-libav-dev
        gstreamer1.0-libav
        gzip
        less
        libasm1
        libbfd
        libdw1
        libelf1
        libgdbm-compat4
        libgdbm-dev
        libgdbm6
        libgettextlib
        libgettextsrc
        libgmp-dev
        libgmp10
        libgmpxx4
        libidn2-0
        libidn2-dev
        libmpc3
        libmpfr6
        libreadline-dev
        libreadline8
        libunistring-dev
        libunistring2
        m4-dev
        m4
        make
        nettle-dev
        nettle
        parted
        python3-rfc3987
        python3-strict-rfc3339
        tar
        which
        zeromq

If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project http://arago-project.org j7-evm ttyS2

Arago 2021.09 j7-evm ttyS2

j7-evm login:

Could you help me to solved this issue?

Thank you very much!

Best Regards,

Shawn

Hi,

As you are using Custom Board, Can you please check exp1 & exp2 nodes applicable in your Board or not?
Also, check the reset GPIO setting in mdio node, whether you are using the same or not for PHY reset?
"reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;"

Can you please check by removing the above once. whether you are facing booting issue or not?

Best Regards,
Sudheer

Hello Sudheer,

I removed exp1, exp2 nodes and "reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;" in k3-j721e-gesi-exp-board.dts, please help to check. And I added "name_overlays=k3-j721e-gesi-exp-board.dtbo" in uenv.txt.

// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
                ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
				ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
				ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
				ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default
		     &rgmii5_pins_default>;
};

&cpsw0_port1 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};

&cpsw0_port3 {
	status = "disabled";
};

&cpsw0_port4 {
	status = "disabled";
};

&cpsw0_port2 {
	status = "disabled";
};

&cpsw0_port5 {
	phy-handle = <&cpsw9g_phy0>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 5>;
};

&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};


&cpsw9g_mdio {
	bus_freq = <1000000>;
	// reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw9g_virt_mac {
	status = "disabled";
};

// &exp1 {
// 	p15-hog {
// 		/* P15 - EXP_MUX2 */
// 		gpio-hog;
// 		gpios = <13 GPIO_ACTIVE_HIGH>;
// 		output-high;
// 		line-name = "EXP_MUX2";
// 	};

// 	p16-hog {
// 		/* P16 - EXP_MUX3 */
// 		gpio-hog;
// 		gpios = <14 GPIO_ACTIVE_HIGH>;
// 		output-high;
// 		line-name = "EXP_MUX3";
// 	};
// };

// &exp2 {
// 	qsgmii-line-hog {
// 		gpio-hog;
// 		gpios = <16 GPIO_ACTIVE_HIGH>;
// 		output-low;
// 		line-name = "qsgmii-pwrdn-line";
// 	};
// };

&main_pmx0 {
	mdio_pins_default: mdio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	rgmii5_pins_default: rgmii5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x184, PIN_INPUT, 0) /* (T23) RGMII5_RD0 */
			J721E_IOPAD(0x180, PIN_INPUT, 0) /* (R23) RGMII5_RD1 */
			J721E_IOPAD(0x17c, PIN_INPUT, 0) /* (U24) RGMII5_RD2 */
			J721E_IOPAD(0x178, PIN_INPUT, 0) /* (U27) RGMII5_RD3 */
			J721E_IOPAD(0x174, PIN_INPUT, 0) /* (U25) RGMII5_RXC */
			J721E_IOPAD(0x15c, PIN_INPUT, 0) /* (U26) RGMII5_RX_CTL */
			J721E_IOPAD(0x16c, PIN_OUTPUT, 0) /* (U28) RGMII5_TD0 */
			J721E_IOPAD(0x168, PIN_OUTPUT, 0) /* (V27) RGMII5_TD1 */
			J721E_IOPAD(0x164, PIN_OUTPUT, 0) /* (V29) RGMII5_TD2 */
			J721E_IOPAD(0x160, PIN_OUTPUT, 0) /* (V28) RGMII5_TD3 */
			J721E_IOPAD(0x170, PIN_OUTPUT, 0) /* (U29) RGMII5_TXC */
			J721E_IOPAD(0x158, PIN_OUTPUT, 0) /* (U23) RGMII5_TX_CTL */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};

&cpsw0_phy_gmii_sel {
    ti,qsgmii-main-ports = <2>, <4>;
};

It also boot failed.

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
42 bytes read in 11 ms (2.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 818 ms (22.5 MiB/s)
98024 bytes read in 20 ms (4.7 MiB/s)
3712 bytes read in 16 ms (226.6 KiB/s)
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
=>

Do you have any further instructions?

Thank you very much!

Best Regards,

Shawn

Hi,

shawn lin said:

And I added "name_overlays=k3-j721e-gesi-exp-board.dtbo" in uenv.txt.

Can you please correct overlay adding in uEnv.txt file as below. Quotes only for the overlay file.
name_overlays="k3-j721e-gesi-exp-board.dtbo"

Best Regards,
Sudheer

Hello Sudheer,

I modified uEnv.txt with 

name_overlays="k3-j721e-gesi-exp-board.dtbo"

It has same situation, "ERROR: Did not find a cmdline Flattened Device Tree   Could not find a valid device tree".

Best Regards,

Shawn

Hi,

Can you please share your device tree files, k3-j721e-common-proc-board.dts" and "k3-j721e-main.dtsi" along with the device tree overlay used.
Above error could be if any node referenced from overlay many not be found the device tree files so it is failed to apply the overlay.

Best Regards,
Sudheer

Hello Sudheer,

Thank you for your reply again!

The device tree file as below:

k3-j721e-common-proc-board.dts:

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;

		sw10: sw10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: sw11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		/* gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; */   /*mark by shawn...currently hw set this always on */
	};

	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		/* gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; */   /* mark by shawn...we don't need this pin to select voltage output */
		/* states = <1800000 0x0>, */   /* mark by shawn...our sd power is 3v3 */
		states = <3300000 0x0>,
			 <3300000 0x1>;
	};

	// Kevin - Enable McASP TDM
	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";

		// ti,cpb-mcasp = <&mcasp10>; // Kevin - Use McASP10 Interface
		ti,cpb-mcasp = <&mcasp0>; // Kevin - Use McASP0 Interface
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "cpb-mcasp-auxclk",
			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
			      "cpb-codec-scki",
			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
	};

/*	Bryant Lin modify - 2022-04-18
	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0]; 
		};
	};

	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethmac-device-1";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0];
		};
	};
*/
/*
	transceiver1: can-phy0 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};

	transceiver3: can-phy2 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
	};

	transceiver4: can-phy3 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
		standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
	};
*/

	dp_pwr_3v3: fixedregulator-dp-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		//gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
		enable-active-high;

		/* Always on for now, until dp-connector driver can handle this */
		regulator-always-on;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};
};

&main_pmx0 {
/* Jimmy Wei modify - 2023-05-02 */
	spi0_pins_default: spi0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT, 0) /* (AA1) SPI0_CLK */
			J721E_IOPAD(0x1c0, PIN_INPUT, 0) /* (AA2) SPI0_CS0 */
			J721E_IOPAD(0x1c4, PIN_INPUT, 0) /* (Y4) SPI0_CS1 */
			//J721E_IOPAD(0x1f0, PIN_INPUT, 2) /* (AC2) UART0_CTSn.SPI0_CS2 */
			//J721E_IOPAD(0x1f4, PIN_INPUT, 2) /* (AB1) UART0_RTSn.SPI0_CS3 */
			J721E_IOPAD(0x1cc, PIN_INPUT, 0) /* (AB5) SPI0_D0 */
			J721E_IOPAD(0x1d0, PIN_INPUT, 0) /* (AA3) SPI0_D1 */
		>;
	};

/* Sam Chu Modify – 2023-07-12 */
	spi1_pins_default: spi1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1dc, PIN_INPUT, 0) /* (Y1) SPI1_CLK */
			J721E_IOPAD(0x1d4, PIN_INPUT, 0) /* (Y3) SPI1_CS0 */
			//J721E_IOPAD(0x1d8, PIN_INPUT, 0) /* (W4) SPI1_CS1 */
			J721E_IOPAD(0x1e0, PIN_INPUT, 0) /* (Y5) SPI1_D0 */
			J721E_IOPAD(0x1e4, PIN_INPUT, 0) /* (Y2) SPI1_D1 */
		>;
	};

	sw10_button_pins_default: sw10-button-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
		pinctrl-single,pins = <
			//J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss1_pins_default: main-usbss1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
		>;
	};

	dp0_pins_default: dp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	// main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
	// 	>;
	// };

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c2_pins_default: main-i2c2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) // (AB5) SPI0_CLK.I2C2_SCL
			J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) // (AA1) SPI0_D0.I2C2_SDA
		>;
	};
*/

	main_i2c3_pins_default: main-i2c3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c6_pins_default: main-i2c6-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) // (AA3) SPI0_D1.I2C6_SCL
			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) // (Y2) SPI1_D1.I2C6_SDA
		>;
	};
*/
	// Kevin - Add McASP0 PinControl
	mcasp0_pins_default: mcasp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0D4, PIN_OUTPUT_PULLDOWN, 12) /* (AB26) prg0_pru0_gpo9.MCASP0_ACLKX */
			J721E_IOPAD(0x0D8, PIN_OUTPUT_PULLDOWN, 12) /* (AB25) prg0_pru0_gpo10.MCASP0_AFSX */
			J721E_IOPAD(0x0B0, PIN_OUTPUT_PULLDOWN, 12) /* (AF28) prg0_pru0_gpo0.MCASP0_AXR0 */
			J721E_IOPAD(0x0B4, PIN_INPUT_PULLDOWN, 12) /* (AE28) prg0_pru0_gpo1.MCASP0_AXR1 */
		>;
	};

	// mcasp10_pins_default: mcasp10-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
	// 		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
	// 		J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
	// 		J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
	// 		J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
	// 		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
	// 		J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
	// 		J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
	// 		J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
	// 	>;
	// };

	audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
		>;
	};

	main_mcan0_pins_default: main-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	main_mcan2_pins_default: main-mcan2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
			J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
		>;
	};

	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
		>;
	};
};

&wkup_pmx0 {
	sw11_button_pins_default: sw11-button-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
		>;
	};

	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	//status = "reserved";	Modify by Bryant Lin 2022-04-18
	status = "disabled";
};

&main_uart0 {
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart3 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio3 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio5 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&main_gpio7 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv_alt>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci2 {
	/* Unused */
	status = "disabled";
};

&usb_serdes_mux {
	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes3_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss1_pins_default>;
	ti,usb2-only;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/*	Bryant Lin modify - 2022-04-20
&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};
*/

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

		p08-hog {
			/* P10 - PM_I2C_CTRL_OE */
			gpio-hog;
			gpios = <8 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "CTRL_PM_I2C_OE";
		};

		p09-hog {
			/* P11 - MCASP/TRACE_MUX_S0 */
			gpio-hog;
			gpios = <9 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "MCASP/TRACE_MUX_S0";
		};

		p10-hog {
			/* P12 - MCASP/TRACE_MUX_S1 */
			gpio-hog;
			gpios = <10 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP/TRACE_MUX_S1";
		};
	};
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;
/*
	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
*/
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <100000>;

	ina226@40 {
		compatible = "ti,ina226";
		reg = <0x40>;
		shunt-resistor = <50>;
	};

	ina226@41 {
		compatible = "ti,ina226";
		reg = <0x41>;
		shunt-resistor = <50>;
	};

	ina226@42 {
		compatible = "ti,ina226";
		reg = <0x42>;
		shunt-resistor = <50>;
	};

	ina226@43 {
		compatible = "ti,ina226";
		reg = <0x43>;
		shunt-resistor = <50>;
	};

	ina226@44 {
		compatible = "ti,ina226";
		reg = <0x44>;
		shunt-resistor = <50>;
	};

	ina226@45 {
		compatible = "ti,ina226";
		reg = <0x45>;
		shunt-resistor = <50>;
	};

	ina226@46 {
		compatible = "ti,ina226";
		reg = <0x46>;
		shunt-resistor = <50>;
	};

	ina226@47 {
		compatible = "ti,ina226";
		reg = <0x48>;
		shunt-resistor = <10000>;
	};

	ina226@48 {
		compatible = "ti,ina226";
		reg = <0x49>;
		shunt-resistor = <50>;
	};

	ina226@4a {
		compatible = "ti,ina226";
		reg = <0x4a>;
		shunt-resistor = <50>;
	};

	ina226@4b {
		compatible = "ti,ina226";
		reg = <0x4b>;
		shunt-resistor = <50>;
	};
};
*/

&k3_clks {
	// Confiure AUDIO_EXT_REFCLK2 pin as output
	pinctrl-names = "default";
	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcm3168a_1: audio-codec@44 {
		compatible = "ti,pcm3168a";
		reg = <0x44>;

		#sound-dai-cells = <1>;

		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;

		// C_AUDIO_REFCLK2 -> RGMII6_RXC (W26)
		clocks = <&k3_clks 157 371>;
		clock-names = "scki";

		// HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2
		assigned-clocks = <&k3_clks 157 371>;
		assigned-clock-parents = <&k3_clks 157 400>;
		assigned-clock-rates = <24576000>; // for 48KHz

		VDD1-supply = <&vsys_3v3>;
		VDD2-supply = <&vsys_3v3>;
		VCCAD1-supply = <&vsys_5v0>;
		VCCAD2-supply = <&vsys_5v0>;
		VCCDA1-supply = <&vsys_5v0>;
		VCCDA2-supply = <&vsys_5v0>;
	};
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	// exp5: gpio@20 {
	// 	compatible = "ti,tca6408";
	// 	reg = <0x20>;
	// 	gpio-controller;
	// 	#gpio-cells = <2>;
	// };
};
*/

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port@0 {
		reg = <0>;

		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&mhdp {
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

// Kevin - Enable McASP0 Interface
&mcasp0 {
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins_default>;

	op-mode = <0>; /* I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF, IEC60958-1, and AES-3 formats. */
	tdm-slots = <8>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		0 0 0 0
	>;
	tx-num-evt = <8>;
	rx-num-evt = <8>;
};

&mcasp1 {
	status = "disabled";
};

&mcasp2 {
	status = "disabled";
};

&mcasp3 {
	status = "disabled";
};

&mcasp4 {
	status = "disabled";
};

&mcasp5 {
	status = "disabled";
};

&mcasp6 {
	status = "disabled";
};

&mcasp7 {
	status = "disabled";
};

&mcasp8 {
	status = "disabled";
};

&mcasp9 {
	status = "disabled";
};

&mcasp10 {
	status = "disabled";
	// #sound-dai-cells = <0>;

	// pinctrl-names = "default";
	// pinctrl-0 = <&mcasp10_pins_default>;

	// op-mode = <0>;          /* MCASP_IIS_MODE */
	// tdm-slots = <8>;
	// auxclk-fs-ratio = <256>;

	// serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
	// 	1 1 1 1
	// 	2 2 2 0
	// >;
	// tx-num-evt = <8>;
	// rx-num-evt = <8>;
};

&mcasp11 {
	status = "disabled";
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

/*
&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 2>;
	};

};

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};
*/

&pcie0_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
};

&pcie1_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie2_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie0_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
	// status = "disabled";
};

&pcie1_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie2_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie3_rc {
	status = "disabled";
};

&pcie3_ep {
	status = "disabled";
};

/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
&main_uart2 {
	status = "disabled";
};

&mcu_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan0_pins_default>;
	// phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan1_pins_default>;
	// phys = <&transceiver2>;
};

&main_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan0_pins_default>;
	// phys = <&transceiver3>;
};

&main_mcan1 {
	status = "disabled";
};

&main_mcan2 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan2_pins_default>;
	// phys = <&transceiver4>;
};

&main_mcan3 {
	status = "disabled";
};

&main_mcan4 {
	status = "disabled";
};

&main_mcan5 {
	status = "disabled";
};

&main_mcan6 {
	status = "disabled";
};

&main_mcan7 {
	status = "disabled";
};

&main_mcan8 {
	status = "disabled";
};

&main_mcan9 {
	status = "disabled";
};

&main_mcan10 {
	status = "disabled";
};

&main_mcan11 {
	status = "disabled";
};

&main_mcan12 {
	status = "disabled";
};

&main_mcan13 {
	status = "disabled";
};

&csi0_port0 {
	status = "disabled";
};

&csi0_port1 {
	status = "disabled";
};

&csi0_port2 {
	status = "disabled";
};

&csi0_port3 {
	status = "disabled";
};

&csi0_port4 {
	status = "disabled";
};

&main_ehrpwm0 {
	status = "disabled";
};

&main_ehrpwm1 {
	status = "disabled";
};

&main_ehrpwm2 {
	status = "disabled";
};

&main_ehrpwm3 {
	status = "disabled";
};

&main_ehrpwm4 {
	status = "disabled";
};

&main_ehrpwm5 {
	status = "disabled";
};

//Jimmy Wei modify - 2023-05-02
&main_spi0 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi0_pins_default>;
    status="okay";

    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

//Sam Chu modify - 2023-07-12
&main_spi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi1_pins_default>;
    status="okay";
    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

k3-j721e-main.dtsi:

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>

/ {
	cmn_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	cmn_refclk1: clock-cmnrefclk1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {

// Jimmy 2023/04/24
	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2100000 0x0 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 266 1>;
		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		};

// Sam 2023/07/12
	main_spi1: spi@2110000 {
                compatible = "ti,am654-mcspi","ti,omap4-mcspi";
                reg = <0x0 0x2110000 0x0 0x400>;
                interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 267 1>;
                power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
                };

	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};
	};

	scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: mux@4080 {
			compatible = "mmio-mux";
			reg = <0x00004080 0x50>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
					/* SERDES4 lane0/1/2/3 select */
			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
				      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
		};

		usb_serdes_mux: mux-controller@4000 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
		};

		ehrpwm_tbclk: clock@4140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	main_ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3000000 0x0 0x100>;
		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3010000 0x0 0x100>;
		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3020000 0x0 0x100>;
		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3030000 0x0 0x100>;
		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3040000 0x0 0x100>;
		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3050000 0x0 0x100>;
		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
		clock-names = "tbclk", "fck";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01900000 0x00 0x100000>;	/* GICR */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller0 {
		compatible = "ti,sci-intr";
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <131>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main-navss {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <199>;

		main_navss_intr: interrupt-controller1 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <213>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <209>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		smmu0: iommu@36600000 {
			compatible = "arm,smmu-v3";
			reg = <0x0 0x36600000 0x0 0x100000>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			#iommu-cells = <1>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x3c000000 0x0 0x400000>,
				<0x0 0x38000000 0x0 0x400000>,
				<0x0 0x31120000 0x0 0x100>,
				<0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <211>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg =	<0x0 0x31150000 0x0 0x100>,
				<0x0 0x34000000 0x0 0x100000>,
				<0x0 0x35000000 0x0 0x100000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <212>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 201 1>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";
		dma-coherent;

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 264 1>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x2b4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	serdes_wiz0: wiz@5000000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5000000 0x0 0x5000000 0x10000>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 292 0>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz0_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5000000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz0 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz1: wiz@5010000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5010000 0x0 0x5010000 0x10000>;

		wiz1_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 293 0>;
		};

		wiz1_refclk_dig: refclk-dig {
			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_refclk_dig>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
			clocks = <&wiz1_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz1_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes1: serdes@5010000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5010000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz1 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5020000 0x0 0x5020000 0x10000>;

		wiz2_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 294 0>;
		};

		wiz2_refclk_dig: refclk-dig {
			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_refclk_dig>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz2_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz2_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes2: serdes@5020000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5020000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz2 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz3: wiz@5030000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5030000 0x0 0x5030000 0x10000>;

		wiz3_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 295 0>;
		};

		wiz3_refclk_dig: refclk-dig {
			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_refclk_dig>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz3_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz3_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes3: serdes@5030000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5030000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz3 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	pcie0_rc: pcie@2900000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
				<0 0 0 2 &pcie0_intc 0>, /* INT B */
				<0 0 0 3 &pcie0_intc 0>, /* INT C */
				<0 0 0 4 &pcie0_intc 0>; /* INT D */

		pcie0_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie0_ep: pcie-ep@2900000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
				<0 0 0 2 &pcie1_intc 0>, /* INT B */
				<0 0 0 3 &pcie1_intc 0>, /* INT C */
				<0 0 0 4 &pcie1_intc 0>; /* INT D */

		pcie1_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */
				<0 0 0 2 &pcie2_intc 0>, /* INT B */
				<0 0 0 3 &pcie2_intc 0>, /* INT C */
				<0 0 0 4 &pcie2_intc 0>; /* INT D */

		pcie2_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie2_ep: pcie-ep@2920000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */
				<0 0 0 2 &pcie3_intc 0>, /* INT B */
				<0 0 0 3 &pcie3_intc 0>, /* INT C */
				<0 0 0 4 &pcie3_intc 0>; /* INT D */

		pcie3_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie3_ep: pcie-ep@2930000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
		#address-cells = <2>;
		#size-cells = <2>;
	};

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
			torrent_phy_dp: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>;
				cdns,phy-type = <PHY_TYPE_DP>;
				cdns,num-lanes = <4>;
				cdns,max-bit-rate = <5400>;
				#phy-cells = <0>;
			};
		};
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 0>;
		clock-names = "fclk";
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>;
		clock-names = "fclk";
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>;
		clock-names = "fclk";
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 281 0>;
		clock-names = "fclk";
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 282 0>;
		clock-names = "fclk";
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 283 0>;
		clock-names = "fclk";
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 284 0>;
		clock-names = "fclk";
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 285 0>;
		clock-names = "fclk";
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 286 0>;
		clock-names = "fclk";
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <256>, <257>, <258>, <259>,
			     <260>, <261>, <262>, <263>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 105 0>;
		clock-names = "gpio";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <288>, <289>, <290>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 0>;
		clock-names = "gpio";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00610000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <264>, <265>, <266>, <267>,
			     <268>, <269>, <270>, <271>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 0>;
		clock-names = "gpio";
	};

	main_gpio3: gpio@611000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00611000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <292>, <293>, <294>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 108 0>;
		clock-names = "gpio";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00620000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <272>, <273>, <274>, <275>,
			     <276>, <277>, <278>, <279>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 109 0>;
		clock-names = "gpio";
	};

	main_gpio5: gpio@621000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00621000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <296>, <297>, <298>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 110 0>;
		clock-names = "gpio";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00630000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <280>, <281>, <282>, <283>,
			     <284>, <285>, <286>, <287>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

	main_gpio7: gpio@631000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00631000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <300>, <301>, <302>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
		assigned-clocks = <&k3_clks 91 1>;
		assigned-clock-parents = <&k3_clks 91 2>;
		bus-width = <8>;
		mmc-hs200-1_8v;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0xf>;
		ti,otap-del-sel-mmc-hs = <0xf>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x6>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
		ti,itap-del-sel-ddr52 = <0x3>;
		ti,trm-icp = <0x8>;
		ti,strobe-sel = <0x77>;
		dma-coherent;
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
		assigned-clocks = <&k3_clks 92 0>;
		assigned-clock-parents = <&k3_clks 92 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
	};

	main_sdhci2: mmc@4f98000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
		assigned-clocks = <&k3_clks 93 0>;
		assigned-clock-parents = <&k3_clks 93 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4104000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6000000 0x00 0x10000>,
			      <0x00 0x6010000 0x00 0x10000>,
			      <0x00 0x6020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usbss1: cdns-usb@4114000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4114000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb1: usb@6400000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6400000 0x00 0x10000>,
			      <0x00 0x6410000 0x00 0x10000>,
			      <0x00 0x6420000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 187 0>;
		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 188 0>;
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 189 0>;
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 190 0>;
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2040000 0x0 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 191 0>;
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2050000 0x0 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 192 0>;
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2060000 0x0 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 193 0>;
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
	};

	d5520: video-decoder@4300000 {
	       /* IMG D5520 driver configuration */
	       compatible = "img,d5500-vxd";
	       reg = <0x00 0x04300000>,
		   <0x00 0x100000>;
	       power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
	       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};

	vxe384: video-encoder@4200000 {
		compatible = "img,vxe384";
		reg = <0x00 0x04200000>,
		    <0x00 0x100000>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	};

	ufs_wrapper: ufs-wrapper@4e80000 {
		compatible = "ti,j721e-ufs";
		reg = <0x0 0x4e80000 0x0 0x100>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 277 1>;
		assigned-clocks = <&k3_clks 277 1>;
		assigned-clock-parents = <&k3_clks 277 4>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		ufs@4e84000 {
			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
			reg = <0x0 0x4e84000 0x0 0x10000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
			clock-names = "core_clk", "phy_clk", "ref_clk";
			dma-coherent;
		};
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 151 36>;

		phys = <&torrent_phy_dp>;
		phy-names = "dpphy";

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks =	<&k3_clks 152 0>,
				<&k3_clks 152 1>,
				<&k3_clks 152 4>,
				<&k3_clks 152 9>,
				<&k3_clks 152 13>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 174 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 175 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 176 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp3: mcasp@2b30000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b30000 0x0 0x2000>,
			<0x0 0x02b38000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 177 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp4: mcasp@2b40000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b40000 0x0 0x2000>,
			<0x0 0x02b48000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 178 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp5: mcasp@2b50000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b50000 0x0 0x2000>,
			<0x0 0x02b58000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 179 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp6: mcasp@2b60000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b60000 0x0 0x2000>,
			<0x0 0x02b68000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 180 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp7: mcasp@2b70000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b70000 0x0 0x2000>,
			<0x0 0x02b78000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 181 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp8: mcasp@2b80000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b80000 0x0 0x2000>,
			<0x0 0x02b88000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 182 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp9: mcasp@2b90000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b90000 0x0 0x2000>,
			<0x0 0x02b98000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 183 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp10: mcasp@2ba0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02ba0000 0x0 0x2000>,
			<0x0 0x02ba8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 184 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp11: mcasp@2bb0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02bb0000 0x0 0x2000>,
			<0x0 0x02bb8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 185 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
	};

	watchdog0: watchdog@2200000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2200000 0x0 0x100>;
		clocks = <&k3_clks 252 1>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 252 1>;
		assigned-clock-parents = <&k3_clks 252 5>;
	};

	watchdog1: watchdog@2210000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2210000 0x0 0x100>;
		clocks = <&k3_clks 253 1>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 253 1>;
		assigned-clock-parents = <&k3_clks 253 5>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5c00000 0x00008000>,
			      <0x5c10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <245>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 245 1>;
			firmware-name = "j7-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5d00000 0x00008000>,
			      <0x5d10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <246>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 246 1>;
			firmware-name = "j7-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5e00000 0x00008000>,
			      <0x5e10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <247>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 247 1>;
			firmware-name = "j7-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5f00000 0x00008000>,
			      <0x5f10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <248>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 248 1>;
			firmware-name = "j7-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c66_0: dsp@4d80800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x80800000 0x00 0x00048000>,
		      <0x4d 0x80e00000 0x00 0x00008000>,
		      <0x4d 0x80f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <142>;
		ti,sci-proc-ids = <0x03 0xff>;
		resets = <&k3_reset 142 1>;
		firmware-name = "j7-c66_0-fw";
	};

	c66_1: dsp@4d81800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x81800000 0x00 0x00048000>,
		      <0x4d 0x81e00000 0x00 0x00008000>,
		      <0x4d 0x81f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <143>;
		ti,sci-proc-ids = <0x04 0xff>;
		resets = <&k3_reset 143 1>;
		firmware-name = "j7-c66_1-fw";
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721e-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <15>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 15 1>;
		firmware-name = "j7-c71_0-fw";
	};

	icssg0: icssg@b000000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb000000 0x00 0x80000>;
		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b000000 0x100000>;

		icssg0_mem: memories@0 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg0_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg0_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
						 <&k3_clks 119 1>;  /* icssg0_iclk */
					assigned-clocks = <&icssg0_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 119 1>;
				};

				icssg0_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
						 <&icssg0_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg0_iepclk_mux>;
					assigned-clock-parents = <&icssg0_coreclk_mux>;
				};
			};
		};

		icssg0_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg0_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg0_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru0_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x3000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_0-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <16 2 2>;
			interrupt-names = "vring";
		};

		rtu0_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_0-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <20 4 4>;
			interrupt-names = "vring";
		};

		tx_pru0_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_0-fw";
		};

		pru0_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x3000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_1-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <18 3 3>;
			interrupt-names = "vring";
		};

		rtu0_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_1-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <22 5 5>;
			interrupt-names = "vring";
		};

		tx_pru0_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_1-fw";
		};

		icssg0_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 119 1>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	icssg1: icssg@b100000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb100000 0x00 0x80000>;
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b100000 0x100000>;

		icssg1_mem: memories@b100000 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg1_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
						 <&k3_clks 120 4>;  /* icssg1_iclk */
					assigned-clocks = <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 120 4>;
				};

				icssg1_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
						 <&icssg1_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg1_iepclk_mux>;
					assigned-clock-parents = <&icssg1_coreclk_mux>;
				};
			};
		};

		icssg1_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg1_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg1_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru1_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x4000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_0-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <16 2 2>;
			interrupt-names = "vring";
		};

		rtu1_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_0-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <20 4 4>;
			interrupt-names = "vring";
		};

		tx_pru1_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_0-fw";
		};

		pru1_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x4000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_1-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <18 3 3>;
			interrupt-names = "vring";
		};

		rtu1_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_1-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <22 5 5>;
			interrupt-names = "vring";
		};

		tx_pru1_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_1-fw";
		};

		icssg1_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 120 4>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	timesync_router: timesync_router@A40000 {
		compatible = "pinctrl-single";
		reg = <0x0 0xa40000 0x0 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x000107ff>;
		status = "disabled";
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721e-pvr", "img,pvr-ge8430";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		reg-names = "gpu_regs";
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "gpu_0", "gpucore_0";
		clocks = <&k3_clks 125 0>;
		clock-names = "ctrl";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
			<&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
			<&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
			<&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
			<&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
			<&main_udmap 0x494f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4500000 0x0 0x1000>;
		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4504000 0x0 0x1000>;
			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
				<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy0>;
			phy-names = "dphy";
			power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
				};

				csi0_port1: port@1 {
					reg = <1>;
				};

				csi0_port2: port@2 {
					reg = <2>;
				};

				csi0_port3: port@3 {
					reg = <3>;
				};

				csi0_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
			<&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
			<&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
			<&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
			<&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
			<&main_udmap 0x496f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4510000 0x0 0x1000>;
		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4514000 0x0 0x1000>;
			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
				<&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";
			power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
				};

				csi1_port1: port@1 {
					reg = <1>;
				};

				csi1_port2: port@2 {
					reg = <2>;
				};

				csi1_port3: port@3 {
					reg = <3>;
				};

				csi1_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	dphy0: phy@4580000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4580000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	dphy1: phy@4590000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4590000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};
};

Please help to check, thank you!

Best Regards,

Shawn

HI,

From device tree files, few nodes are missing this might be the reason for following error.

failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree

Can you please remove below from gesi overlay file, as node is commented in "k3-j721e-common-proc-board.dts" file.

&cpsw9g_virt_mac {
	status = "disabled";
};

Hello Sudheer,

After I followed your instructions, it could boot successfully and load uenv.txt. But there is still no RGMII5 with a eth phy 88E1512 when I keyed in "ifconfig -a". 

Could you please help me investigate what caused it? The following is shown boot log, k3-j721e-common-proc-board.dts, k3-j721e-main.dtsi, k3-j721e-gesi-exp-board.dts.

Thank you very much!

boot log

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
44 bytes read in 12 ms (2.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 819 ms (22.4 MiB/s)
100462 bytes read in 20 ms (4.8 MiB/s)
3580 bytes read in 18 ms (193.4 KiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fee4000, end 000000008fffffff ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 5.10.100 (root@aep-COMPAL-SERVER) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Sun Dec 3 00:06:29 CST 2023
[    0.000000] Machine model: Texas Instruments K3 J721E SoC
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 2 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-queues@ac000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac200000, size 30 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-buffers@ac200000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a8ffffff]
[    0.000000]   node   0: [mem 0x00000000a9000000-0x00000000a9ffffff]
[    0.000000]   node   0: [mem 0x00000000aa000000-0x00000000abbfffff]
[    0.000000]   node   0: [mem 0x00000000abc00000-0x00000000abffffff]
[    0.000000]   node   0: [mem 0x00000000ac000000-0x00000000adffffff]
[    0.000000]   node   0: [mem 0x00000000ae000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] cma: Reserved 512 MiB at 0x00000000e0000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 2 pages/cpu s49880 r8192 d73000 u131072
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: EL2 vector hardening
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 65472
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs) root=PARTUUID=5a8abaf6-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 6, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 5, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x00000000dc000000-0x00000000e0000000] (64MB)
[    0.000000] Memory: 3339136K/4194304K available (10880K kernel code, 1290K rwdata, 4352K rodata, 1856K init, 748K bss, 330880K reserved, 524288K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: 16 PPIs implemented
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: allocated 1048576 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008800b0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008800c0000
[    0.000000] random: get_random_bytes called from start_kernel+0x31c/0x4c4 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000001] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008375] Console: colour dummy device 80x25
[    0.012936] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023607] pid_max: default: 32768 minimum: 301
[    0.028354] LSM: Security Framework initializing
[    0.033098] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.040664] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.049610] rcu: Hierarchical SRCU implementation.
[    0.054663] Platform MSI: msi-controller@1820000 domain created
[    0.060905] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.070197] EFI services will not be available.
[    0.074949] smp: Bringing up secondary CPUs ...
[    0.080182] Detected PIPT I-cache on CPU1
[    0.080207] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.080217] GICv3: CPU1: using allocated LPI pending table @0x00000008800d0000
[    0.080250] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.080303] smp: Brought up 1 node, 2 CPUs
[    0.109650] SMP: Total of 2 processors activated.
[    0.114455] CPU features: detected: 32-bit EL0 Support
[    0.119709] CPU features: detected: CRC32 instructions
[    0.133418] CPU: All CPU(s) started at EL2
[    0.137612] alternatives: patching kernel code
[    0.142600] devtmpfs: initialized
[    0.150953] KASLR disabled due to lack of seed
[    0.155602] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.165564] futex hash table entries: 512 (order: -1, 32768 bytes, linear)
[    0.173194] pinctrl core: initialized pinctrl subsystem
[    0.178770] DMI not present or invalid.
[    0.182980] NET: Registered protocol family 16
[    0.190399] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.197701] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.205705] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.214011] thermal_sys: Registered thermal governor 'step_wise'
[    0.214014] thermal_sys: Registered thermal governor 'power_allocator'
[    0.220433] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.234074] ASID allocator initialised with 65536 entries
[    0.255778] HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages
[    0.262634] HugeTLB registered 512 MiB page size, pre-allocated 0 pages
[    0.269394] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.277289] cryptd: max_cpu_qlen set to 1000
[    0.283292] k3-chipinfo 43000014.chipid: Family:J721E rev:SR2.0 JTAGID[0x1bb6402f] Detected
[    0.292111] vsys_3v3: supplied by evm_12v0
[    0.296475] vsys_5v0: supplied by evm_12v0
[    0.300788] vdd_mmc1: supplied by vsys_3v3
[    0.305489] iommu: Default domain type: Translated
[    0.310626] SCSI subsystem initialized
[    0.314745] mc: Linux media interface: v0.10
[    0.319122] videodev: Linux video capture interface: v2.00
[    0.324750] pps_core: LinuxPPS API ver. 1 registered
[    0.329820] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.339157] PTP clock support registered
[    0.343175] EDAC MC: Ver: 3.0.0
[    0.346906] FPGA manager framework
[    0.350418] Advanced Linux Sound Architecture Driver Initialized.
[    0.357026] clocksource: Switched to clocksource arch_sys_counter
[    0.363439] VFS: Disk quotas dquot_6.6.0
[    0.367481] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[    0.377195] NET: Registered protocol family 2
[    0.381778] IP idents hash table entries: 65536 (order: 3, 524288 bytes, linear)
[    0.390406] tcp_listen_portaddr_hash hash table entries: 4096 (order: 0, 65536 bytes, linear)
[    0.399175] TCP established hash table entries: 32768 (order: 2, 262144 bytes, linear)
[    0.407370] TCP bind hash table entries: 32768 (order: 3, 524288 bytes, linear)
[    0.415176] TCP: Hash tables configured (established 32768 bind 32768)
[    0.421925] UDP hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.428818] UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.436202] NET: Registered protocol family 1
[    0.440899] RPC: Registered named UNIX socket transport module.
[    0.446963] RPC: Registered udp transport module.
[    0.451767] RPC: Registered tcp transport module.
[    0.456570] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.463154] PCI: CLS 0 bytes, default 64
[    0.467496] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.477852] Initialise system trusted keyrings
[    0.482485] workingset: timestamp_bits=46 max_order=16 bucket_order=0
[    0.490714] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.496899] NFS: Registering the id_resolver key type
[    0.502132] Key type id_resolver registered
[    0.506403] Key type id_legacy registered
[    0.510521] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.517369] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.525006] 9p: Installing v9fs 9p2000 file system support
[    0.549998] Key type asymmetric registered
[    0.554184] Asymmetric key parser 'x509' registered
[    0.559180] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[    0.566739] io scheduler mq-deadline registered
[    0.571364] io scheduler kyber registered
[    0.576634] pinctrl-single 4301c000.pinctrl: 94 pins, size 376
[    0.582801] pinctrl-single 11c000.pinctrl: 173 pins, size 692
[    0.591192] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.597467] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.605225] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.613303] arm-smmu-v3 36600000.iommu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    0.622258] arm-smmu-v3 36600000.iommu: allocated 524288 entries for cmdq
[    0.631067] arm-smmu-v3 36600000.iommu: allocated 524288 entries for evtq
[    0.638775] arm-smmu-v3 36600000.iommu: msi_domain absent - falling back to wired irqs
[    0.651681] brd: module loaded
[    0.657619] loop: module loaded
[    0.661428] megasas: 07.714.04.00-rc1
[    0.666837] tun: Universal TUN/TAP device driver, 1.6
[    0.672273] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.678682] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.684752] sky2: driver version 1.30
[    0.689000] VFIO - User Level meta-driver version: 0.3
[    0.694667] i2c /dev entries driver
[    0.698828] sdhci: Secure Digital Host Controller Interface driver
[    0.705149] sdhci: Copyright(c) Pierre Ossman
[    0.709847] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.716175] ledtrig-cpu: registered to indicate activity on CPUs
[    0.722474] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.729589] optee: probing for conduit method.
[    0.734146] optee: revision 3.12 (3d47a131)
[    0.734384] optee: initialized driver
[    0.743848] NET: Registered protocol family 17
[    0.748459] 9pnet: Installing 9P2000 support
[    0.752842] Key type dns_resolver registered
[    0.757287] Loading compiled-in X.509 certificates
[    0.766147] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.772479] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.780724] ti-sci 44083000.dmsc: ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
[    0.810152] random: fast init done
[    0.842049] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    0.848405] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    0.856435] omap_i2c 40b00000.i2c: bus 0 rev0.12 at 100 kHz
[    0.862520] omap_i2c 40b10000.i2c: bus 1 rev0.12 at 100 kHz
[    0.868597] omap_i2c 42120000.i2c: bus 2 rev0.12 at 100 kHz
[    0.874862] pca953x 3-0020: supply vcc not found, using dummy regulator
[    0.881684] pca953x 3-0020: using no AI
[    0.909062] pca953x 3-0020: failed writing register
[    0.914095] pca953x: probe of 3-0020 failed with error -121
[    0.919996] pca953x 3-0022: supply vcc not found, using dummy regulator
[    0.926795] pca953x 3-0022: using AI
[    0.930497] pca953x 3-0022: failed writing register
[    0.935521] pca953x: probe of 3-0022 failed with error -121
[    0.941262] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz
[    0.947311] omap_i2c 2010000.i2c: bus 4 rev0.12 at 400 kHz
[    0.953307] omap_i2c 2020000.i2c: bus 5 rev0.12 at 100 kHz
[    0.959436] pca953x 6-0020: supply vcc not found, using dummy regulator
[    0.966246] pca953x 6-0020: using no AI
[    0.993063] pca953x 6-0020: failed writing register
[    0.998092] pca953x: probe of 6-0020 failed with error -121
[    1.005051] omap_i2c 2030000.i2c: bus 6 rev0.12 at 400 kHz
[    1.011123] omap_i2c 2040000.i2c: bus 7 rev0.12 at 100 kHz
[    1.017124] omap_i2c 2050000.i2c: bus 8 rev0.12 at 100 kHz
[    1.023088] omap_i2c 2060000.i2c: bus 9 rev0.12 at 100 kHz
[    1.029495] ti-sci-intr bus@100000:bus@28380000:interrupt-controller2: Interrupt Router 137 domain created
[    1.039526] ti-sci-intr bus@100000:interrupt-controller0: Interrupt Router 131 domain created
[    1.048340] ti-sci-intr bus@100000:main-navss:interrupt-controller1: Interrupt Router 213 domain created
[    1.058178] ti-sci-inta 33d00000.interrupt-controller: Interrupt Aggregator domain 209 created
[    1.077945] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    1.087824] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.094583] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.103445] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.113599] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.120357] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.128293] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 15, base_baud = 6000000) is a 8250
[    1.137671] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 28, base_baud = 3000000) is a 8250
[    1.146415] printk: console [ttyS2] enabled
[    1.146415] printk: console [ttyS2] enabled
[    1.154850] printk: bootconsole [ns16550a0] disabled
[    1.154850] printk: bootconsole [ns16550a0] disabled
[    1.165304] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 29, base_baud = 3000000) is a 8250
[    1.174224] 2840000.serial: ttyS6 at MMIO 0x2840000 (irq = 30, base_baud = 3000000) is a 8250
[    1.184637] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    1.195149] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    1.205305] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    1.215544] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[    1.226411] scsi host0: ufshcd
[    1.273037] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.281111] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.287834] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.301680] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    1.310545] mmc0: CQHCI version 5.10
[    1.310704] mmc1: CQHCI version 5.10
[    1.317868] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.324045] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    1.336650] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    1.343497] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    1.349604] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    1.350334] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    1.364445] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    1.371259] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    1.381985] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    1.392400] ti-udma 31150000.dma-controller: Channels: 122 (tchan: 61, rchan: 61, gp-rflow: 16)
[    1.406674] spi-nor spi2.0: mt35xu512aba (65536 Kbytes)
[    1.411918] 8 cmdlinepart partitions found on MTD device 47040000.spi.0
[    1.418517] Creating 8 MTD partitions on "47040000.spi.0":
[    1.423989] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    1.429967] 0x000000080000-0x000000280000 : "ospi.tispl"
[    1.435648] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    1.441452] 0x000000680000-0x0000006c0000 : "ospi.env"
[    1.446978] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    1.452654] 0x0000007c0000-0x000000800000 : "ospi.env.backup"
[    1.458819] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    1.464574] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
[    1.473166] spi-nor spi3.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
[    1.480060] spi-nor: probe of spi3.0 failed with error -2
[    1.489239] mmc0: Command Queue Engine enabled
[    1.493680] mmc0: new HS200 MMC card at address 0001
[    1.498913] mmcblk0: mmc0:0001 S0J56X 14.8 GiB
[    1.503539] mmcblk0boot0: mmc0:0001 S0J56X partition 1 31.5 MiB
[    1.509544] mmcblk0boot1: mmc0:0001 S0J56X partition 2 31.5 MiB
[    1.515522] mmcblk0rpmb: mmc0:0001 S0J56X partition 3 4.00 MiB, chardev (237:0)
[    1.525046] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.533130] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.539884] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.553505] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    1.560515] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.567725] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.574063] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:0
[    1.584235] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.599110] debugfs: Directory 'pd:27' with parent 'pm_genpd' already present!
[    1.606364] debugfs: Directory 'pd:26' with parent 'pm_genpd' already present!
[    1.614609] debugfs: Directory 'pd:242' with parent 'pm_genpd' already present!
[    1.621934] debugfs: Directory 'pd:241' with parent 'pm_genpd' already present!
[    1.629241] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present!
[    1.636548] debugfs: Directory 'pd:239' with parent 'pm_genpd' already present!
[    1.644831] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    1.665959] ALSA device list:
[    1.667067] cdns-ufshcd 4e84000.ufs: link startup failed 1
[    1.668919]   #0: j721e-cpb
[    1.674391] cdns-ufshcd 4e84000.ufs: UFS Host state=0
[    1.674394] cdns-ufshcd 4e84000.ufs: outstanding reqs=0x0 tasks=0x0
[    1.688460] cdns-ufshcd 4e84000.ufs: saved_err=0x0, saved_uic_err=0x0
[    1.688463] cdns-ufshcd 4e84000.ufs: Device power mode=1, UIC link state=0
    1.701742] cdns-ufshcd 4e84000.ufs: PM in progress=0, sys. suspended=0
[    1.708254] cdns-ufshcd 4e84000.ufs: Auto BKOPS=0, Host self-block=0
[    1.714596] cdns-ufshcd 4e84000.ufs: Clk gate=1
[    1.719114] cdns-ufshcd 4e84000.ufs: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0
[    1.727276] cdns-ufshcd 4e84000.ufs: last intr at 1555453 us, last intr status=0x404
[    1.735000] cdns-ufshcd 4e84000.ufs: error handling flags=0x0, req. abort count=0
[    1.742465] cdns-ufshcd 4e84000.ufs: hba->ufs_version=0x210, Host capabilities=0x1587031f, caps=0x0
[    1.751488] cdns-ufshcd 4e84000.ufs: quirks=0x0, dev. quirks=0x0
[    1.757479] cdns-ufshcd 4e84000.ufs: clk: core_clk, rate: 250000000
[    1.763729] cdns-ufshcd 4e84000.ufs: clk: phy_clk, rate: 19200000
[    1.769807] cdns-ufshcd 4e84000.ufs: clk: ref_clk, rate: 19200000
[    1.775886] cdns-ufshcd 4e84000.ufs: ufshcd_print_pwr_info:[RX, TX]: gear=[0, 0], lane[0, 0], pwr[INVALID MODE, INVALID MODE], rate = 0
[    1.788047] host_regs: 00000000: 1587031f 00000000 00000210 00000000
[    1.794386] host_regs: 00000010: 00000000 00000000 00000000 00000000
[    1.800724] host_regs: 00000020: 00000000 00000470 00000000 00000000
[    1.807061] host_regs: 00000030: 00000008 00000001 00000000 00000000
[    1.813398] host_regs: 00000040: 00000000 00000000 00000000 00000000
[    1.819735] host_regs: 00000050: 00000000 00000000 00000000 00000000
[    1.826072] host_regs: 00000060: 00000000 00000000 00000000 00000000
[    1.832410] host_regs: 00000070: 00000000 00000000 00000000 00000000
[    1.838750] host_regs: 00000080: 00000000 00000000 00000000 00000000
[    1.845093] host_regs: 00000090: 00000000 00000000 00000000 00000000
[    1.851431] cdns-ufshcd 4e84000.ufs: No record of pa_err
[    1.856728] cdns-ufshcd 4e84000.ufs: No record of dl_err
[    1.862025] cdns-ufshcd 4e84000.ufs: No record of nl_err
[    1.867323] cdns-ufshcd 4e84000.ufs: No record of tl_err
[    1.872620] cdns-ufshcd 4e84000.ufs: No record of dme_err
[    1.878004] cdns-ufshcd 4e84000.ufs: No record of auto_hibern8_err
[    1.884167] cdns-ufshcd 4e84000.ufs: No record of fatal_err
[    1.889725] cdns-ufshcd 4e84000.ufs: link_startup_fail[0] = 0x1 at 1562053 us
[    1.896842] cdns-ufshcd 4e84000.ufs: No record of resume_fail
[    1.902572] cdns-ufshcd 4e84000.ufs: No record of suspend_fail
[    1.908390] cdns-ufshcd 4e84000.ufs: No record of dev_reset
[    1.913947] cdns-ufshcd 4e84000.ufs: No record of host_reset
[    1.919591] cdns-ufshcd 4e84000.ufs: No record of task_abort
[    2.381853] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    2.390142] Waiting for root device PARTUUID=5a8abaf6-02...
[    2.427259] mmc1: Problem switching card into high-speed mode!
[    2.433188] mmc1: new SDHC card at address 0001
[    2.438026] mmcblk1: mmc1:0001 ASTC 7.37 GiB
[    2.449638]  mmcblk1: p1 p2
[    3.675044] EXT4-fs (mmcblk1p2): recovery complete
[    3.685076] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[    3.693188] VFS: Mounted root (ext4 filesystem) on device 179:98.
[    3.713678] devtmpfs: mounted
[    3.716923] Freeing unused kernel memory: 1856K
[    3.721479] Run /sbin/init as init process
[    4.341225] systemd[1]: System time before build time, advancing clock.
[    4.435685] systemd[1]: systemd 244.5+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[    4.457409] systemd[1]: Detected architecture arm64.

Welcome to Arago 2021.09!

[    4.506708] systemd[1]: Set hostname to <j7-evm>.
[    5.007584] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    5.016474] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    5.065523] systemd[1]: /lib/systemd/system/docker.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/docker.sock → /run/docker.sock; please update the unit file accordingly.
[    5.213737] random: systemd: uninitialized urandom read (16 bytes read)
[    5.220448] systemd[1]: system-getty.slice: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
[    5.232774] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
[    5.242659] systemd[1]: Created slice system-getty.slice.
[  OK  ] Created slice system-getty.slice.
[    5.265093] random: systemd: uninitialized urandom read (16 bytes read)
[    5.272332] systemd[1]: Created slice system-serial\x2dgetty.slice.
[  OK  ] Created slice system-serial\x2dgetty.slice.
[    5.293081] random: systemd: uninitialized urandom read (16 bytes read)
[    5.300233] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    5.321201] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password …ts to Console Directory Watch.
[    5.345127] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password R…uests to Wall Directory Watch.
[    5.369121] systemd[1]: Reached target Paths.
[  OK  ] Reached target Paths.
[    5.385076] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    5.405063] systemd[1]: Reached target Slices.
[  OK  ] Reached target Slices.
[    5.421076] systemd[1]: Reached target Swap.
[  OK  ] Reached target Swap.
[    5.441044] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    5.465091] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    5.488733] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    5.509231] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    5.548716] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
[    5.557048] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    5.577291] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    5.593349] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    5.617245] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    5.637185] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    5.659347] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    5.675474] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    5.699516] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    5.729508] systemd[1]: Mounting Temporary Directory (/tmp)...
         Mounting Temporary Directory (/tmp)...
[    5.745207] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped.
[    5.758528] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    5.786665] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    5.801237] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[    5.813274] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    5.864171] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    5.887401] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems...
[    5.907129] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
[    5.916197] systemd[1]: Starting udev Coldplug all Devices...
         Starting udev Coldplug all Devices...
[    5.939887] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    5.957316] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[  OK  ] Started Remount Root and Kernel File Systems.
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
[    6.180684] systemd-journald[175]: Received client request to flush runtime journal.
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create Static Device Nodes in /dev.
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram...
         Mounting /var/volatile...
         Starting udev Wait for Complete Device Initialization...
         Starting udev Kernel Device Manager...
[  OK  ] Mounted /media/ram.
[  OK  ] Mounted /var/volatile.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Create Volatile Files and Directories.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target System Time Synchronized.
         Starting Update UTMP about System Boot/Shutdown...
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
         Starting Start psplash boot splash screen...
         Starting Load Kernel Modules...
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[    8.809050] random: crng init done
[    8.812453] random: 7 urandom warning(s) missed due to ratelimiting
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Created slice system-systemd\x2dfsck.slice.
[  OK  ] Found device /dev/mmcblk1p1.
         Starting File System Check on /dev/mmcblk1p1...
[  OK  ] Started udev Wait for Complete Device Initialization.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timers.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API.
[  OK  ] Listening on dropbear.socket.
         Starting Reboot and dump vmcore via kexec...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
         Starting Save/Restore Sound Card State...
[  OK  ] Started Job spooling tools.
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started D-Bus System Message Bus.
         Starting Print notice about GPLv3 packages...
         Starting set host name as per compatible name...
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
[  OK  ] Started irqbalance daemon.
         Starting Telephony service...
         Starting rc.pvr.service...
         Starting startwlanap...
         Starting startwlansta...
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started TEE Supplicant.
         Starting Update weston ini… based on the platform name...
[  OK  ] Started Reboot and dump vmcore via kexec.
[  OK  ] Started Save/Restore Sound Card State.
[  OK  ] Reached target Sound Card.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started File System Check on /dev/mmcblk1p1.
[  OK  ] Started set host name as per compatible name.
[  OK  ] Started IPv6 Packet Filtering Framework.
[  OK  ] Started IPv4 Packet Filtering Framework.
[  OK  ] Started rc.pvr.service.
[  OK  ] Started startwlanap.
[  OK  ] Started startwlansta.
[  OK  ] Started Update weston ini …ge based on the platform name.
[  OK  ] Started Telephony service.
[  OK  ] Reached target Network (Pre).
         Mounting /run/media/mmcblk1p1...
         Starting Network Service...
         Starting weston.service...
[  OK  ] Started weston.service.
         Starting DEMO...
         Starting telnetd.service...
[  OK  ] Started DEMO.
[  OK  ] Started telnetd.service.
[  OK  ] Started Network Service.
         Starting Wait for Network to be Configured...
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Reached target Ne[   10.821319] am65-cpsw-nuss 46000000.ethernet: phy /bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0 not found on slave 1
twork.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
         Starting Enable and configure wl18xx bluetooth stack...
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting Simple Network Ma…ent Protocol (SNMP) Daemon....
         Starting Permit User Sessions...
[  OK  ] Mounted /run/media/mmcblk1p1.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Enable and configure wl18xx bluetooth stack.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Serial Getty on ttyS3.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Simple Network Man…ement Protocol (SNMP) Daemon..
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
        autoconf
        bash-dev
        bash
        bc
        binutils
        cifs-utils
        coreutils-stdbuf
        coreutils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbserver
        gettext
        glmark2
        gstreamer1.0-libav-dev
        gstreamer1.0-libav
        gzip
        less
        libasm1
        libbfd
        libdw1
        libelf1
        libgdbm-compat4
        libgdbm-dev
        libgdbm6
        libgettextlib
        libgettextsrc
        libgmp-dev
        libgmp10
        libgmpxx4
        libidn2-0
        libidn2-dev
        libmpc3
        libmpfr6
        libreadline-dev
        libreadline8
        libunistring-dev
        libunistring2
        m4-dev
        m4
        make
        nettle-dev
        nettle
        parted
        python3-rfc3987
        python3-strict-rfc3339
        tar
        which
        zeromq

If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project http://arago-project.org j7-evm ttyS2

Arago 2021.09 j7-evm ttyS2

j7-evm login: root
root@j7-evm:~#
root@j7-evm:~# ifconfig -a
eth0: flags=4098<BROADCAST,MULTICAST>  mtu 1500  metric 1
        ether 24:76:25:a1:a5:53  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536  metric 1
        inet 127.0.0.1  netmask 255.0.0.0
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 2  bytes 140 (140.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 2  bytes 140 (140.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j7-evm:~#

k3-j721e-common-proc-board.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;

		sw10: sw10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: sw11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		/* gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; */   /*mark by shawn...currently hw set this always on */
	};

	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		/* gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; */   /* mark by shawn...we don't need this pin to select voltage output */
		/* states = <1800000 0x0>, */   /* mark by shawn...our sd power is 3v3 */
		states = <3300000 0x0>,
			 <3300000 0x1>;
	};

	// Kevin - Enable McASP TDM
	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";

		// ti,cpb-mcasp = <&mcasp10>; // Kevin - Use McASP10 Interface
		ti,cpb-mcasp = <&mcasp0>; // Kevin - Use McASP0 Interface
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "cpb-mcasp-auxclk",
			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
			      "cpb-codec-scki",
			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
	};

/*	Bryant Lin modify - 2022-04-18
	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0]; 
		};
	};

	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethmac-device-1";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0];
		};
	};
*/
/*
	transceiver1: can-phy0 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};

	transceiver3: can-phy2 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
	};

	transceiver4: can-phy3 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
		standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
	};
*/

	dp_pwr_3v3: fixedregulator-dp-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		//gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
		enable-active-high;

		/* Always on for now, until dp-connector driver can handle this */
		regulator-always-on;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};
};

&main_pmx0 {
/* Jimmy Wei modify - 2023-05-02 */
	spi0_pins_default: spi0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT, 0) /* (AA1) SPI0_CLK */
			J721E_IOPAD(0x1c0, PIN_INPUT, 0) /* (AA2) SPI0_CS0 */
			J721E_IOPAD(0x1c4, PIN_INPUT, 0) /* (Y4) SPI0_CS1 */
			//J721E_IOPAD(0x1f0, PIN_INPUT, 2) /* (AC2) UART0_CTSn.SPI0_CS2 */
			//J721E_IOPAD(0x1f4, PIN_INPUT, 2) /* (AB1) UART0_RTSn.SPI0_CS3 */
			J721E_IOPAD(0x1cc, PIN_INPUT, 0) /* (AB5) SPI0_D0 */
			J721E_IOPAD(0x1d0, PIN_INPUT, 0) /* (AA3) SPI0_D1 */
		>;
	};

/* Sam Chu Modify – 2023-07-12 */
	spi1_pins_default: spi1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1dc, PIN_INPUT, 0) /* (Y1) SPI1_CLK */
			J721E_IOPAD(0x1d4, PIN_INPUT, 0) /* (Y3) SPI1_CS0 */
			//J721E_IOPAD(0x1d8, PIN_INPUT, 0) /* (W4) SPI1_CS1 */
			J721E_IOPAD(0x1e0, PIN_INPUT, 0) /* (Y5) SPI1_D0 */
			J721E_IOPAD(0x1e4, PIN_INPUT, 0) /* (Y2) SPI1_D1 */
		>;
	};

	sw10_button_pins_default: sw10-button-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
		pinctrl-single,pins = <
			//J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss1_pins_default: main-usbss1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
		>;
	};

	dp0_pins_default: dp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	// main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
	// 	>;
	// };

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c2_pins_default: main-i2c2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) // (AB5) SPI0_CLK.I2C2_SCL
			J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) // (AA1) SPI0_D0.I2C2_SDA
		>;
	};
*/

	main_i2c3_pins_default: main-i2c3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c6_pins_default: main-i2c6-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) // (AA3) SPI0_D1.I2C6_SCL
			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) // (Y2) SPI1_D1.I2C6_SDA
		>;
	};
*/
	// Kevin - Add McASP0 PinControl
	mcasp0_pins_default: mcasp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0D4, PIN_OUTPUT_PULLDOWN, 12) /* (AB26) prg0_pru0_gpo9.MCASP0_ACLKX */
			J721E_IOPAD(0x0D8, PIN_OUTPUT_PULLDOWN, 12) /* (AB25) prg0_pru0_gpo10.MCASP0_AFSX */
			J721E_IOPAD(0x0B0, PIN_OUTPUT_PULLDOWN, 12) /* (AF28) prg0_pru0_gpo0.MCASP0_AXR0 */
			J721E_IOPAD(0x0B4, PIN_INPUT_PULLDOWN, 12) /* (AE28) prg0_pru0_gpo1.MCASP0_AXR1 */
		>;
	};

	// mcasp10_pins_default: mcasp10-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
	// 		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
	// 		J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
	// 		J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
	// 		J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
	// 		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
	// 		J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
	// 		J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
	// 		J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
	// 	>;
	// };

	audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
		>;
	};

	main_mcan0_pins_default: main-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	main_mcan2_pins_default: main-mcan2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
			J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
		>;
	};

	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
		>;
	};
};

&wkup_pmx0 {
	sw11_button_pins_default: sw11-button-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
		>;
	};

	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	//status = "reserved";	Modify by Bryant Lin 2022-04-18
	status = "disabled";
};

&main_uart0 {
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart3 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio3 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio5 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&main_gpio7 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv_alt>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci2 {
	/* Unused */
	status = "disabled";
};

&usb_serdes_mux {
	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes3_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss1_pins_default>;
	ti,usb2-only;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/*	Bryant Lin modify - 2022-04-20
&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};
*/

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

		p08-hog {
			/* P10 - PM_I2C_CTRL_OE */
			gpio-hog;
			gpios = <8 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "CTRL_PM_I2C_OE";
		};

		p09-hog {
			/* P11 - MCASP/TRACE_MUX_S0 */
			gpio-hog;
			gpios = <9 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "MCASP/TRACE_MUX_S0";
		};

		p10-hog {
			/* P12 - MCASP/TRACE_MUX_S1 */
			gpio-hog;
			gpios = <10 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP/TRACE_MUX_S1";
		};
	};
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;
/*
	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
*/
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <100000>;

	ina226@40 {
		compatible = "ti,ina226";
		reg = <0x40>;
		shunt-resistor = <50>;
	};

	ina226@41 {
		compatible = "ti,ina226";
		reg = <0x41>;
		shunt-resistor = <50>;
	};

	ina226@42 {
		compatible = "ti,ina226";
		reg = <0x42>;
		shunt-resistor = <50>;
	};

	ina226@43 {
		compatible = "ti,ina226";
		reg = <0x43>;
		shunt-resistor = <50>;
	};

	ina226@44 {
		compatible = "ti,ina226";
		reg = <0x44>;
		shunt-resistor = <50>;
	};

	ina226@45 {
		compatible = "ti,ina226";
		reg = <0x45>;
		shunt-resistor = <50>;
	};

	ina226@46 {
		compatible = "ti,ina226";
		reg = <0x46>;
		shunt-resistor = <50>;
	};

	ina226@47 {
		compatible = "ti,ina226";
		reg = <0x48>;
		shunt-resistor = <10000>;
	};

	ina226@48 {
		compatible = "ti,ina226";
		reg = <0x49>;
		shunt-resistor = <50>;
	};

	ina226@4a {
		compatible = "ti,ina226";
		reg = <0x4a>;
		shunt-resistor = <50>;
	};

	ina226@4b {
		compatible = "ti,ina226";
		reg = <0x4b>;
		shunt-resistor = <50>;
	};
};
*/

&k3_clks {
	// Confiure AUDIO_EXT_REFCLK2 pin as output
	pinctrl-names = "default";
	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcm3168a_1: audio-codec@44 {
		compatible = "ti,pcm3168a";
		reg = <0x44>;

		#sound-dai-cells = <1>;

		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;

		// C_AUDIO_REFCLK2 -> RGMII6_RXC (W26)
		clocks = <&k3_clks 157 371>;
		clock-names = "scki";

		// HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2
		assigned-clocks = <&k3_clks 157 371>;
		assigned-clock-parents = <&k3_clks 157 400>;
		assigned-clock-rates = <24576000>; // for 48KHz

		VDD1-supply = <&vsys_3v3>;
		VDD2-supply = <&vsys_3v3>;
		VCCAD1-supply = <&vsys_5v0>;
		VCCAD2-supply = <&vsys_5v0>;
		VCCDA1-supply = <&vsys_5v0>;
		VCCDA2-supply = <&vsys_5v0>;
	};
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	// exp5: gpio@20 {
	// 	compatible = "ti,tca6408";
	// 	reg = <0x20>;
	// 	gpio-controller;
	// 	#gpio-cells = <2>;
	// };
};
*/

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port@0 {
		reg = <0>;

		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&mhdp {
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

// Kevin - Enable McASP0 Interface
&mcasp0 {
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins_default>;

	op-mode = <0>; /* I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF, IEC60958-1, and AES-3 formats. */
	tdm-slots = <8>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		0 0 0 0
	>;
	tx-num-evt = <8>;
	rx-num-evt = <8>;
};

&mcasp1 {
	status = "disabled";
};

&mcasp2 {
	status = "disabled";
};

&mcasp3 {
	status = "disabled";
};

&mcasp4 {
	status = "disabled";
};

&mcasp5 {
	status = "disabled";
};

&mcasp6 {
	status = "disabled";
};

&mcasp7 {
	status = "disabled";
};

&mcasp8 {
	status = "disabled";
};

&mcasp9 {
	status = "disabled";
};

&mcasp10 {
	status = "disabled";
	// #sound-dai-cells = <0>;

	// pinctrl-names = "default";
	// pinctrl-0 = <&mcasp10_pins_default>;

	// op-mode = <0>;          /* MCASP_IIS_MODE */
	// tdm-slots = <8>;
	// auxclk-fs-ratio = <256>;

	// serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
	// 	1 1 1 1
	// 	2 2 2 0
	// >;
	// tx-num-evt = <8>;
	// rx-num-evt = <8>;
};

&mcasp11 {
	status = "disabled";
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

/*
&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 2>;
	};

};

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};
*/

&pcie0_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
};

&pcie1_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie2_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie0_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
	// status = "disabled";
};

&pcie1_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie2_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie3_rc {
	status = "disabled";
};

&pcie3_ep {
	status = "disabled";
};

/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
&main_uart2 {
	status = "disabled";
};

&mcu_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan0_pins_default>;
	// phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan1_pins_default>;
	// phys = <&transceiver2>;
};

&main_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan0_pins_default>;
	// phys = <&transceiver3>;
};

&main_mcan1 {
	status = "disabled";
};

&main_mcan2 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan2_pins_default>;
	// phys = <&transceiver4>;
};

&main_mcan3 {
	status = "disabled";
};

&main_mcan4 {
	status = "disabled";
};

&main_mcan5 {
	status = "disabled";
};

&main_mcan6 {
	status = "disabled";
};

&main_mcan7 {
	status = "disabled";
};

&main_mcan8 {
	status = "disabled";
};

&main_mcan9 {
	status = "disabled";
};

&main_mcan10 {
	status = "disabled";
};

&main_mcan11 {
	status = "disabled";
};

&main_mcan12 {
	status = "disabled";
};

&main_mcan13 {
	status = "disabled";
};

&csi0_port0 {
	status = "disabled";
};

&csi0_port1 {
	status = "disabled";
};

&csi0_port2 {
	status = "disabled";
};

&csi0_port3 {
	status = "disabled";
};

&csi0_port4 {
	status = "disabled";
};

&main_ehrpwm0 {
	status = "disabled";
};

&main_ehrpwm1 {
	status = "disabled";
};

&main_ehrpwm2 {
	status = "disabled";
};

&main_ehrpwm3 {
	status = "disabled";
};

&main_ehrpwm4 {
	status = "disabled";
};

&main_ehrpwm5 {
	status = "disabled";
};

//Jimmy Wei modify - 2023-05-02
&main_spi0 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi0_pins_default>;
    status="okay";

    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

//Sam Chu modify - 2023-07-12
&main_spi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi1_pins_default>;
    status="okay";
    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

k3-j721e-main.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>

/ {
	cmn_refclk: clock-cmnrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	cmn_refclk1: clock-cmnrefclk1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {

// Jimmy 2023/04/24
	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2100000 0x0 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 266 1>;
		power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		};

// Sam 2023/07/12
	main_spi1: spi@2110000 {
                compatible = "ti,am654-mcspi","ti,omap4-mcspi";
                reg = <0x0 0x2110000 0x0 0x400>;
                interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&k3_clks 267 1>;
                power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
                #address-cells = <1>;
                #size-cells = <0>;
                };

	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};
	};

	scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: mux@4080 {
			compatible = "mmio-mux";
			reg = <0x00004080 0x50>;
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
					<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
					/* SERDES4 lane0/1/2/3 select */
			idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
				      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
				      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
		};

		cpsw0_phy_gmii_sel: phy@4044 {
			compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
			ti,qsgmii-main-ports = <2>, <1>;
			reg = <0x4044 0x20>;
			#phy-cells = <1>;
		};

		usb_serdes_mux: mux-controller@4000 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
		};

		ehrpwm_tbclk: clock@4140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	main_ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3000000 0x0 0x100>;
		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3010000 0x0 0x100>;
		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3020000 0x0 0x100>;
		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3030000 0x0 0x100>;
		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3040000 0x0 0x100>;
		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3050000 0x0 0x100>;
		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
		clock-names = "tbclk", "fck";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01900000 0x00 0x100000>;	/* GICR */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller0 {
		compatible = "ti,sci-intr";
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <131>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main-navss {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <199>;

		main_navss_intr: interrupt-controller1 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <213>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <209>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		smmu0: iommu@36600000 {
			compatible = "arm,smmu-v3";
			reg = <0x0 0x36600000 0x0 0x100000>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			#iommu-cells = <1>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x3c000000 0x0 0x400000>,
				<0x0 0x38000000 0x0 0x400000>,
				<0x0 0x31120000 0x0 0x100>,
				<0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <211>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg =	<0x0 0x31150000 0x0 0x100>,
				<0x0 0x34000000 0x0 0x100000>,
				<0x0 0x35000000 0x0 0x100000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <212>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 201 1>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	cpsw0: ethernet@c000000 {
		compatible = "ti,j721e-cpswxg-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x00 0xc000000 0x00 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
		clocks = <&k3_clks 19 89>;
		clock-names = "fck";
		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			cpsw0_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
			};

			cpsw0_port2: port@2 {
				reg = <2>;
				ti,mac-only;
				label = "port2";
			};

			cpsw0_port3: port@3 {
				reg = <3>;
				ti,mac-only;
				label = "port3";
			};

			cpsw0_port4: port@4 {
				reg = <4>;
				ti,mac-only;
				label = "port4";
			};

			cpsw0_port5: port@5 {
				reg = <5>;
				ti,mac-only;
				label = "port5";
			};

			cpsw0_port6: port@6 {
				reg = <6>;
				ti,mac-only;
				label = "port6";
			};

			cpsw0_port7: port@7 {
				reg = <7>;
				ti,mac-only;
				label = "port7";
			};

			cpsw0_port8: port@8 {
				reg = <8>;
				ti,mac-only;
				label = "port8";
			};
		};

		cpsw9g_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x00 0xf00 0x00 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 19 89>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,j721e-cpts";
			reg = <0x00 0x3d000 0x00 0x400>;
			clocks = <&k3_clks 19 16>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";
		dma-coherent;

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 264 1>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x2b4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	serdes_wiz0: wiz@5000000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5000000 0x0 0x5000000 0x10000>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 292 0>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz0_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5000000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz0 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz1: wiz@5010000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5010000 0x0 0x5010000 0x10000>;

		wiz1_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 293 0>;
		};

		wiz1_refclk_dig: refclk-dig {
			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_refclk_dig>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
			clocks = <&wiz1_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz1_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes1: serdes@5010000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5010000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz1 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5020000 0x0 0x5020000 0x10000>;

		wiz2_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 294 0>;
		};

		wiz2_refclk_dig: refclk-dig {
			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_refclk_dig>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz2_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz2_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes2: serdes@5020000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5020000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz2 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz3: wiz@5030000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5030000 0x0 0x5030000 0x10000>;

		wiz3_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 295 0>;
		};

		wiz3_refclk_dig: refclk-dig {
			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_refclk_dig>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz3_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz3_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes3: serdes@5030000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5030000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz3 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	pcie0_rc: pcie@2900000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
				<0 0 0 2 &pcie0_intc 0>, /* INT B */
				<0 0 0 3 &pcie0_intc 0>, /* INT C */
				<0 0 0 4 &pcie0_intc 0>; /* INT D */

		pcie0_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie0_ep: pcie-ep@2900000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
				<0 0 0 2 &pcie1_intc 0>, /* INT B */
				<0 0 0 3 &pcie1_intc 0>, /* INT C */
				<0 0 0 4 &pcie1_intc 0>; /* INT D */

		pcie1_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */
				<0 0 0 2 &pcie2_intc 0>, /* INT B */
				<0 0 0 3 &pcie2_intc 0>, /* INT C */
				<0 0 0 4 &pcie2_intc 0>; /* INT D */

		pcie2_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie2_ep: pcie-ep@2920000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */
				<0 0 0 2 &pcie3_intc 0>, /* INT B */
				<0 0 0 3 &pcie3_intc 0>, /* INT C */
				<0 0 0 4 &pcie3_intc 0>; /* INT D */

		pcie3_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie3_ep: pcie-ep@2930000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
		#address-cells = <2>;
		#size-cells = <2>;
	};

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
			torrent_phy_dp: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>;
				cdns,phy-type = <PHY_TYPE_DP>;
				cdns,num-lanes = <4>;
				cdns,max-bit-rate = <5400>;
				#phy-cells = <0>;
			};
		};
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 0>;
		clock-names = "fclk";
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>;
		clock-names = "fclk";
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>;
		clock-names = "fclk";
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 281 0>;
		clock-names = "fclk";
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 282 0>;
		clock-names = "fclk";
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 283 0>;
		clock-names = "fclk";
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 284 0>;
		clock-names = "fclk";
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 285 0>;
		clock-names = "fclk";
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 286 0>;
		clock-names = "fclk";
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <256>, <257>, <258>, <259>,
			     <260>, <261>, <262>, <263>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 105 0>;
		clock-names = "gpio";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <288>, <289>, <290>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 0>;
		clock-names = "gpio";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00610000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <264>, <265>, <266>, <267>,
			     <268>, <269>, <270>, <271>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 0>;
		clock-names = "gpio";
	};

	main_gpio3: gpio@611000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00611000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <292>, <293>, <294>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 108 0>;
		clock-names = "gpio";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00620000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <272>, <273>, <274>, <275>,
			     <276>, <277>, <278>, <279>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 109 0>;
		clock-names = "gpio";
	};

	main_gpio5: gpio@621000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00621000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <296>, <297>, <298>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 110 0>;
		clock-names = "gpio";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00630000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <280>, <281>, <282>, <283>,
			     <284>, <285>, <286>, <287>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

	main_gpio7: gpio@631000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00631000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <300>, <301>, <302>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
		assigned-clocks = <&k3_clks 91 1>;
		assigned-clock-parents = <&k3_clks 91 2>;
		bus-width = <8>;
		mmc-hs200-1_8v;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0xf>;
		ti,otap-del-sel-mmc-hs = <0xf>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x6>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
		ti,itap-del-sel-ddr52 = <0x3>;
		ti,trm-icp = <0x8>;
		ti,strobe-sel = <0x77>;
		dma-coherent;
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
		assigned-clocks = <&k3_clks 92 0>;
		assigned-clock-parents = <&k3_clks 92 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
	};

	main_sdhci2: mmc@4f98000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
		assigned-clocks = <&k3_clks 93 0>;
		assigned-clock-parents = <&k3_clks 93 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,itap-del-sel-ddr50 = <0x2>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
		sdhci-caps-mask = <0x2 0x0>;
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4104000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6000000 0x00 0x10000>,
			      <0x00 0x6010000 0x00 0x10000>,
			      <0x00 0x6020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usbss1: cdns-usb@4114000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4114000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb1: usb@6400000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6400000 0x00 0x10000>,
			      <0x00 0x6410000 0x00 0x10000>,
			      <0x00 0x6420000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 187 0>;
		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 188 0>;
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 189 0>;
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 190 0>;
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2040000 0x0 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 191 0>;
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2050000 0x0 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 192 0>;
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2060000 0x0 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 193 0>;
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
	};

	d5520: video-decoder@4300000 {
	       /* IMG D5520 driver configuration */
	       compatible = "img,d5500-vxd";
	       reg = <0x00 0x04300000>,
		   <0x00 0x100000>;
	       power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
	       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};

	vxe384: video-encoder@4200000 {
		compatible = "img,vxe384";
		reg = <0x00 0x04200000>,
		    <0x00 0x100000>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	};

	ufs_wrapper: ufs-wrapper@4e80000 {
		compatible = "ti,j721e-ufs";
		reg = <0x0 0x4e80000 0x0 0x100>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 277 1>;
		assigned-clocks = <&k3_clks 277 1>;
		assigned-clock-parents = <&k3_clks 277 4>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		ufs@4e84000 {
			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
			reg = <0x0 0x4e84000 0x0 0x10000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
			clock-names = "core_clk", "phy_clk", "ref_clk";
			dma-coherent;
		};
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 151 36>;

		phys = <&torrent_phy_dp>;
		phy-names = "dpphy";

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks =	<&k3_clks 152 0>,
				<&k3_clks 152 1>,
				<&k3_clks 152 4>,
				<&k3_clks 152 9>,
				<&k3_clks 152 13>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 174 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 175 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 176 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp3: mcasp@2b30000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b30000 0x0 0x2000>,
			<0x0 0x02b38000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 177 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp4: mcasp@2b40000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b40000 0x0 0x2000>,
			<0x0 0x02b48000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 178 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp5: mcasp@2b50000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b50000 0x0 0x2000>,
			<0x0 0x02b58000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 179 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp6: mcasp@2b60000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b60000 0x0 0x2000>,
			<0x0 0x02b68000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 180 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp7: mcasp@2b70000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b70000 0x0 0x2000>,
			<0x0 0x02b78000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 181 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp8: mcasp@2b80000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b80000 0x0 0x2000>,
			<0x0 0x02b88000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 182 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp9: mcasp@2b90000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b90000 0x0 0x2000>,
			<0x0 0x02b98000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 183 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp10: mcasp@2ba0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02ba0000 0x0 0x2000>,
			<0x0 0x02ba8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 184 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp11: mcasp@2bb0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02bb0000 0x0 0x2000>,
			<0x0 0x02bb8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 185 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
	};

	watchdog0: watchdog@2200000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2200000 0x0 0x100>;
		clocks = <&k3_clks 252 1>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 252 1>;
		assigned-clock-parents = <&k3_clks 252 5>;
	};

	watchdog1: watchdog@2210000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2210000 0x0 0x100>;
		clocks = <&k3_clks 253 1>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 253 1>;
		assigned-clock-parents = <&k3_clks 253 5>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5c00000 0x00008000>,
			      <0x5c10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <245>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 245 1>;
			firmware-name = "j7-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5d00000 0x00008000>,
			      <0x5d10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <246>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 246 1>;
			firmware-name = "j7-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5e00000 0x00008000>,
			      <0x5e10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <247>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 247 1>;
			firmware-name = "j7-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5f00000 0x00008000>,
			      <0x5f10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <248>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 248 1>;
			firmware-name = "j7-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c66_0: dsp@4d80800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x80800000 0x00 0x00048000>,
		      <0x4d 0x80e00000 0x00 0x00008000>,
		      <0x4d 0x80f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <142>;
		ti,sci-proc-ids = <0x03 0xff>;
		resets = <&k3_reset 142 1>;
		firmware-name = "j7-c66_0-fw";
	};

	c66_1: dsp@4d81800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x81800000 0x00 0x00048000>,
		      <0x4d 0x81e00000 0x00 0x00008000>,
		      <0x4d 0x81f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <143>;
		ti,sci-proc-ids = <0x04 0xff>;
		resets = <&k3_reset 143 1>;
		firmware-name = "j7-c66_1-fw";
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721e-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <15>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 15 1>;
		firmware-name = "j7-c71_0-fw";
	};

	icssg0: icssg@b000000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb000000 0x00 0x80000>;
		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b000000 0x100000>;

		icssg0_mem: memories@0 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg0_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg0_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
						 <&k3_clks 119 1>;  /* icssg0_iclk */
					assigned-clocks = <&icssg0_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 119 1>;
				};

				icssg0_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
						 <&icssg0_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg0_iepclk_mux>;
					assigned-clock-parents = <&icssg0_coreclk_mux>;
				};
			};
		};

		icssg0_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg0_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg0_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru0_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x3000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_0-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <16 2 2>;
			interrupt-names = "vring";
		};

		rtu0_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_0-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <20 4 4>;
			interrupt-names = "vring";
		};

		tx_pru0_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_0-fw";
		};

		pru0_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x3000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_1-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <18 3 3>;
			interrupt-names = "vring";
		};

		rtu0_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_1-fw";
			interrupt-parent = <&icssg0_intc>;
			interrupts = <22 5 5>;
			interrupt-names = "vring";
		};

		tx_pru0_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_1-fw";
		};

		icssg0_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 119 1>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	icssg1: icssg@b100000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb100000 0x00 0x80000>;
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b100000 0x100000>;

		icssg1_mem: memories@b100000 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg1_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
						 <&k3_clks 120 4>;  /* icssg1_iclk */
					assigned-clocks = <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 120 4>;
				};

				icssg1_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
						 <&icssg1_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg1_iepclk_mux>;
					assigned-clock-parents = <&icssg1_coreclk_mux>;
				};
			};
		};

		icssg1_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg1_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg1_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru1_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x4000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_0-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <16 2 2>;
			interrupt-names = "vring";
		};

		rtu1_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_0-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <20 4 4>;
			interrupt-names = "vring";
		};

		tx_pru1_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_0-fw";
		};

		pru1_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x4000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_1-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <18 3 3>;
			interrupt-names = "vring";
		};

		rtu1_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_1-fw";
			interrupt-parent = <&icssg1_intc>;
			interrupts = <22 5 5>;
			interrupt-names = "vring";
		};

		tx_pru1_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_1-fw";
		};

		icssg1_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 120 4>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	timesync_router: timesync_router@A40000 {
		compatible = "pinctrl-single";
		reg = <0x0 0xa40000 0x0 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x000107ff>;
		status = "disabled";
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721e-pvr", "img,pvr-ge8430";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		reg-names = "gpu_regs";
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "gpu_0", "gpucore_0";
		clocks = <&k3_clks 125 0>;
		clock-names = "ctrl";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
			<&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
			<&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
			<&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
			<&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
			<&main_udmap 0x494f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4500000 0x0 0x1000>;
		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4504000 0x0 0x1000>;
			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
				<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy0>;
			phy-names = "dphy";
			power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
				};

				csi0_port1: port@1 {
					reg = <1>;
				};

				csi0_port2: port@2 {
					reg = <2>;
				};

				csi0_port3: port@3 {
					reg = <3>;
				};

				csi0_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
			<&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
			<&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
			<&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
			<&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
			<&main_udmap 0x496f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4510000 0x0 0x1000>;
		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4514000 0x0 0x1000>;
			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
				<&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";
			power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
				};

				csi1_port1: port@1 {
					reg = <1>;
				};

				csi1_port2: port@2 {
					reg = <2>;
				};

				csi1_port3: port@3 {
					reg = <3>;
				};

				csi1_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	dphy0: phy@4580000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4580000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	dphy1: phy@4590000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4590000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};
};

k3-j721e-gesi-exp-board.dts

// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
                ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
				ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
				ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
				ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default
		     &rgmii5_pins_default>;
};

&cpsw0_port1 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};

&cpsw0_port3 {
	status = "disabled";
};

&cpsw0_port4 {
	status = "disabled";
};

&cpsw0_port2 {
	status = "disabled";
};

&cpsw0_port5 {
	phy-handle = <&cpsw9g_phy0>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 5>;
};

&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};


&cpsw9g_mdio {
	bus_freq = <1000000>;
	// reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

// &cpsw9g_virt_mac {
// 	status = "disabled";
// };

// &exp1 {
// 	p15-hog {
// 		/* P15 - EXP_MUX2 */
// 		gpio-hog;
// 		gpios = <13 GPIO_ACTIVE_HIGH>;
// 		output-high;
// 		line-name = "EXP_MUX2";
// 	};

// 	p16-hog {
// 		/* P16 - EXP_MUX3 */
// 		gpio-hog;
// 		gpios = <14 GPIO_ACTIVE_HIGH>;
// 		output-high;
// 		line-name = "EXP_MUX3";
// 	};
// };

// &exp2 {
// 	qsgmii-line-hog {
// 		gpio-hog;
// 		gpios = <16 GPIO_ACTIVE_HIGH>;
// 		output-low;
// 		line-name = "qsgmii-pwrdn-line";
// 	};
// };

&main_pmx0 {
	mdio_pins_default: mdio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	rgmii5_pins_default: rgmii5-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x184, PIN_INPUT, 0) /* (T23) RGMII5_RD0 */
			J721E_IOPAD(0x180, PIN_INPUT, 0) /* (R23) RGMII5_RD1 */
			J721E_IOPAD(0x17c, PIN_INPUT, 0) /* (U24) RGMII5_RD2 */
			J721E_IOPAD(0x178, PIN_INPUT, 0) /* (U27) RGMII5_RD3 */
			J721E_IOPAD(0x174, PIN_INPUT, 0) /* (U25) RGMII5_RXC */
			J721E_IOPAD(0x15c, PIN_INPUT, 0) /* (U26) RGMII5_RX_CTL */
			J721E_IOPAD(0x16c, PIN_OUTPUT, 0) /* (U28) RGMII5_TD0 */
			J721E_IOPAD(0x168, PIN_OUTPUT, 0) /* (V27) RGMII5_TD1 */
			J721E_IOPAD(0x164, PIN_OUTPUT, 0) /* (V29) RGMII5_TD2 */
			J721E_IOPAD(0x160, PIN_OUTPUT, 0) /* (V28) RGMII5_TD3 */
			J721E_IOPAD(0x170, PIN_OUTPUT, 0) /* (U29) RGMII5_TXC */
			J721E_IOPAD(0x158, PIN_OUTPUT, 0) /* (U23) RGMII5_TX_CTL */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};

&cpsw0_phy_gmii_sel {
    ti,qsgmii-main-ports = <2>, <4>;
};

Best Regards,

Shawn

Hi,

From boot log it seems like driver is not loaded for CPSW9G. This could be the reason for you are not observing the RGMII5 interface from "ifconfig -a" command.
Can you please convert the dtb (k3-j721e-common-proc-board.dtb) to dts and share with us.
Also, May I know which SDK you are using.

Best Regards,
Sudheer

Hello Sudheer,

k3-j721e-common-proc-board.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;

		sw10: sw10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: sw11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		/* gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; */   /*mark by shawn...currently hw set this always on */
	};

	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		/* gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; */   /* mark by shawn...we don't need this pin to select voltage output */
		/* states = <1800000 0x0>, */   /* mark by shawn...our sd power is 3v3 */
		states = <3300000 0x0>,
			 <3300000 0x1>;
	};

	// Kevin - Enable McASP TDM
	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";

		// ti,cpb-mcasp = <&mcasp10>; // Kevin - Use McASP10 Interface
		ti,cpb-mcasp = <&mcasp0>; // Kevin - Use McASP0 Interface
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "cpb-mcasp-auxclk",
			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
			      "cpb-codec-scki",
			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
	};

/*	Bryant Lin modify - 2022-04-18
	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0]; 
		};
	};

	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethmac-device-1";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			// local-mac-address = [0 0 0 0 0 0];
		};
	};
*/
/*
	transceiver1: can-phy0 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};

	transceiver3: can-phy2 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
	};

	transceiver4: can-phy3 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
		standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
	};
*/

	dp_pwr_3v3: fixedregulator-dp-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		//gpio = <&exp4 0 0>;	/* P0 - DP0_PWR_SW_EN */
		enable-active-high;

		/* Always on for now, until dp-connector driver can handle this */
		regulator-always-on;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};
};

&main_pmx0 {
/* Jimmy Wei modify - 2023-05-02 */
	spi0_pins_default: spi0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT, 0) /* (AA1) SPI0_CLK */
			J721E_IOPAD(0x1c0, PIN_INPUT, 0) /* (AA2) SPI0_CS0 */
			J721E_IOPAD(0x1c4, PIN_INPUT, 0) /* (Y4) SPI0_CS1 */
			//J721E_IOPAD(0x1f0, PIN_INPUT, 2) /* (AC2) UART0_CTSn.SPI0_CS2 */
			//J721E_IOPAD(0x1f4, PIN_INPUT, 2) /* (AB1) UART0_RTSn.SPI0_CS3 */
			J721E_IOPAD(0x1cc, PIN_INPUT, 0) /* (AB5) SPI0_D0 */
			J721E_IOPAD(0x1d0, PIN_INPUT, 0) /* (AA3) SPI0_D1 */
		>;
	};

/* Sam Chu Modify – 2023-07-12 */
	spi1_pins_default: spi1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1dc, PIN_INPUT, 0) /* (Y1) SPI1_CLK */
			J721E_IOPAD(0x1d4, PIN_INPUT, 0) /* (Y3) SPI1_CS0 */
			//J721E_IOPAD(0x1d8, PIN_INPUT, 0) /* (W4) SPI1_CS1 */
			J721E_IOPAD(0x1e0, PIN_INPUT, 0) /* (Y5) SPI1_D0 */
			J721E_IOPAD(0x1e4, PIN_INPUT, 0) /* (Y2) SPI1_D1 */
		>;
	};

	sw10_button_pins_default: sw10-button-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
		pinctrl-single,pins = <
			//J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss1_pins_default: main-usbss1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
		>;
	};

	dp0_pins_default: dp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	// main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
	// 	>;
	// };

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c2_pins_default: main-i2c2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) // (AB5) SPI0_CLK.I2C2_SCL
			J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) // (AA1) SPI0_D0.I2C2_SDA
		>;
	};
*/

	main_i2c3_pins_default: main-i2c3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
		>;
	};

/* Jimmy Wei modify - 2023-05-02
	main_i2c6_pins_default: main-i2c6-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) // (AA3) SPI0_D1.I2C6_SCL
			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) // (Y2) SPI1_D1.I2C6_SDA
		>;
	};
*/
	// Kevin - Add McASP0 PinControl
	mcasp0_pins_default: mcasp0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0D4, PIN_OUTPUT_PULLDOWN, 12) /* (AB26) prg0_pru0_gpo9.MCASP0_ACLKX */
			J721E_IOPAD(0x0D8, PIN_OUTPUT_PULLDOWN, 12) /* (AB25) prg0_pru0_gpo10.MCASP0_AFSX */
			J721E_IOPAD(0x0B0, PIN_OUTPUT_PULLDOWN, 12) /* (AF28) prg0_pru0_gpo0.MCASP0_AXR0 */
			J721E_IOPAD(0x0B4, PIN_INPUT_PULLDOWN, 12) /* (AE28) prg0_pru0_gpo1.MCASP0_AXR1 */
		>;
	};

	// mcasp10_pins_default: mcasp10-pins-default {
	// 	pinctrl-single,pins = <
	// 		J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
	// 		J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
	// 		J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
	// 		J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
	// 		J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
	// 		J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
	// 		J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
	// 		J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
	// 		J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
	// 	>;
	// };

	audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
		>;
	};

	main_mcan0_pins_default: main-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	main_mcan2_pins_default: main-mcan2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
			J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
		>;
	};

	main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
		>;
	};
};

&wkup_pmx0 {
	sw11_button_pins_default: sw11-button-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
		>;
	};

	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	//status = "reserved";	Modify by Bryant Lin 2022-04-18
	status = "disabled";
};

&main_uart0 {
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart3 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio3 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio5 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&main_gpio7 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv_alt>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci2 {
	/* Unused */
	status = "disabled";
};

&usb_serdes_mux {
	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes3_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss1_pins_default>;
	ti,usb2-only;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/*	Bryant Lin modify - 2022-04-20
&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};
*/

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

		p08-hog {
			/* P10 - PM_I2C_CTRL_OE */
			gpio-hog;
			gpios = <8 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "CTRL_PM_I2C_OE";
		};

		p09-hog {
			/* P11 - MCASP/TRACE_MUX_S0 */
			gpio-hog;
			gpios = <9 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "MCASP/TRACE_MUX_S0";
		};

		p10-hog {
			/* P12 - MCASP/TRACE_MUX_S1 */
			gpio-hog;
			gpios = <10 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP/TRACE_MUX_S1";
		};
	};
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;
/*
	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
*/
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <100000>;

	ina226@40 {
		compatible = "ti,ina226";
		reg = <0x40>;
		shunt-resistor = <50>;
	};

	ina226@41 {
		compatible = "ti,ina226";
		reg = <0x41>;
		shunt-resistor = <50>;
	};

	ina226@42 {
		compatible = "ti,ina226";
		reg = <0x42>;
		shunt-resistor = <50>;
	};

	ina226@43 {
		compatible = "ti,ina226";
		reg = <0x43>;
		shunt-resistor = <50>;
	};

	ina226@44 {
		compatible = "ti,ina226";
		reg = <0x44>;
		shunt-resistor = <50>;
	};

	ina226@45 {
		compatible = "ti,ina226";
		reg = <0x45>;
		shunt-resistor = <50>;
	};

	ina226@46 {
		compatible = "ti,ina226";
		reg = <0x46>;
		shunt-resistor = <50>;
	};

	ina226@47 {
		compatible = "ti,ina226";
		reg = <0x48>;
		shunt-resistor = <10000>;
	};

	ina226@48 {
		compatible = "ti,ina226";
		reg = <0x49>;
		shunt-resistor = <50>;
	};

	ina226@4a {
		compatible = "ti,ina226";
		reg = <0x4a>;
		shunt-resistor = <50>;
	};

	ina226@4b {
		compatible = "ti,ina226";
		reg = <0x4b>;
		shunt-resistor = <50>;
	};
};
*/

&k3_clks {
	// Confiure AUDIO_EXT_REFCLK2 pin as output
	pinctrl-names = "default";
	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcm3168a_1: audio-codec@44 {
		compatible = "ti,pcm3168a";
		reg = <0x44>;

		#sound-dai-cells = <1>;

		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;

		// C_AUDIO_REFCLK2 -> RGMII6_RXC (W26)
		clocks = <&k3_clks 157 371>;
		clock-names = "scki";

		// HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2
		assigned-clocks = <&k3_clks 157 371>;
		assigned-clock-parents = <&k3_clks 157 400>;
		assigned-clock-rates = <24576000>; // for 48KHz

		VDD1-supply = <&vsys_3v3>;
		VDD2-supply = <&vsys_3v3>;
		VCCAD1-supply = <&vsys_5v0>;
		VCCAD2-supply = <&vsys_5v0>;
		VCCDA1-supply = <&vsys_5v0>;
		VCCDA2-supply = <&vsys_5v0>;
	};
};

/* Jimmy Wei modify - 2023-05-02
&main_i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	// exp5: gpio@20 {
	// 	compatible = "ti,tca6408";
	// 	reg = <0x20>;
	// 	gpio-controller;
	// 	#gpio-cells = <2>;
	// };
};
*/

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port@0 {
		reg = <0>;

		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&mhdp {
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

// Kevin - Enable McASP0 Interface
&mcasp0 {
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins_default>;

	op-mode = <0>; /* I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF, IEC60958-1, and AES-3 formats. */
	tdm-slots = <8>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
		0 0 0 0
	>;
	tx-num-evt = <8>;
	rx-num-evt = <8>;
};

&mcasp1 {
	status = "disabled";
};

&mcasp2 {
	status = "disabled";
};

&mcasp3 {
	status = "disabled";
};

&mcasp4 {
	status = "disabled";
};

&mcasp5 {
	status = "disabled";
};

&mcasp6 {
	status = "disabled";
};

&mcasp7 {
	status = "disabled";
};

&mcasp8 {
	status = "disabled";
};

&mcasp9 {
	status = "disabled";
};

&mcasp10 {
	status = "disabled";
	// #sound-dai-cells = <0>;

	// pinctrl-names = "default";
	// pinctrl-0 = <&mcasp10_pins_default>;

	// op-mode = <0>;          /* MCASP_IIS_MODE */
	// tdm-slots = <8>;
	// auxclk-fs-ratio = <256>;

	// serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
	// 	1 1 1 1
	// 	2 2 2 0
	// >;
	// tx-num-evt = <8>;
	// rx-num-evt = <8>;
};

&mcasp11 {
	status = "disabled";
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

/*
&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 2>;
	};

};

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};
*/

&pcie0_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
};

&pcie1_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie2_rc {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
};

&pcie0_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes0_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <1>;
	// status = "disabled";
};

&pcie1_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes1_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie2_ep {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// phys = <&serdes2_pcie_link>;
	// phy-names = "pcie-phy";
	// num-lanes = <2>;
	// status = "disabled";
};

&pcie3_rc {
	status = "disabled";
};

&pcie3_ep {
	status = "disabled";
};

/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
&main_uart2 {
	status = "disabled";
};

&mcu_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan0_pins_default>;
	// phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&mcu_mcan1_pins_default>;
	// phys = <&transceiver2>;
};

&main_mcan0 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan0_pins_default>;
	// phys = <&transceiver3>;
};

&main_mcan1 {
	status = "disabled";
};

&main_mcan2 {
	status = "disabled";	// Modify by Bryant - 2022-04-18
	// pinctrl-names = "default";
	// pinctrl-0 = <&main_mcan2_pins_default>;
	// phys = <&transceiver4>;
};

&main_mcan3 {
	status = "disabled";
};

&main_mcan4 {
	status = "disabled";
};

&main_mcan5 {
	status = "disabled";
};

&main_mcan6 {
	status = "disabled";
};

&main_mcan7 {
	status = "disabled";
};

&main_mcan8 {
	status = "disabled";
};

&main_mcan9 {
	status = "disabled";
};

&main_mcan10 {
	status = "disabled";
};

&main_mcan11 {
	status = "disabled";
};

&main_mcan12 {
	status = "disabled";
};

&main_mcan13 {
	status = "disabled";
};

&csi0_port0 {
	status = "disabled";
};

&csi0_port1 {
	status = "disabled";
};

&csi0_port2 {
	status = "disabled";
};

&csi0_port3 {
	status = "disabled";
};

&csi0_port4 {
	status = "disabled";
};

&main_ehrpwm0 {
	status = "disabled";
};

&main_ehrpwm1 {
	status = "disabled";
};

&main_ehrpwm2 {
	status = "disabled";
};

&main_ehrpwm3 {
	status = "disabled";
};

&main_ehrpwm4 {
	status = "disabled";
};

&main_ehrpwm5 {
	status = "disabled";
};

//Jimmy Wei modify - 2023-05-02
&main_spi0 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi0_pins_default>;
    status="okay";

    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

//Sam Chu modify - 2023-07-12
&main_spi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi1_pins_default>;
    status="okay";
    spidev@0 {
       spi-max-frequency = <24000000>;
       reg = <0>;
       compatible = "linux,spidev";
	};
};

And the SDK version is ti-processor-sdk-linux-j7-evm-08_02_00_03.

Thank you!

Best Regards,

Shawn

Hi,

shawn lin said:

k3-j721e-common-proc-board.dts

Above seems to be same as initially shared dts file.

Doredla Sudheer Kumar said:

Can you please convert the dtb (k3-j721e-common-proc-board.dtb) to dts and share with us.

Can you please convert the dtb file in rootfs/boot/ to dts using below command and share with us.
# dtc -I dtb -O dts k3-j721e-common-proc-board.dtb > j721e-common-proc-board.dts

Also, can you please make sure,CPSW9 register address space mentioned in "k3-j721e.dtsi" under cbass_main node as shown below.


Best Regards,
Sudheer

Hello Sudheer,

Sorry for my misunderstanding. The j721e-common-proc-board.dts which converted from k3-j721e-common-proc-board.dtb in rootfs/boot/ is shown below:

/dts-v1/;

/ {
	model = "Texas Instruments K3 J721E SoC";
	compatible = "ti,j721e";
	interrupt-parent = <0x1>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;

	aliases {
		serial0 = "/bus@100000/bus@28380000/serial@42300000";
		serial1 = "/bus@100000/bus@28380000/serial@40a00000";
		serial2 = "/bus@100000/serial@2800000";
		serial3 = "/bus@100000/serial@2810000";
		serial4 = "/bus@100000/serial@2820000";
		serial5 = "/bus@100000/serial@2830000";
		serial6 = "/bus@100000/serial@2840000";
		serial7 = "/bus@100000/serial@2850000";
		serial8 = "/bus@100000/serial@2860000";
		serial9 = "/bus@100000/serial@2870000";
		serial10 = "/bus@100000/serial@2880000";
		serial11 = "/bus@100000/serial@2890000";
		ethernet0 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
	};

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {

			cluster0 {
				phandle = <0x89>;

				core0 {
					cpu = <0x2>;
				};

				core1 {
					cpu = <0x3>;
				};
			};
		};

		cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x4>;
			phandle = <0x2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x4>;
			phandle = <0x3>;
		};
	};

	l2-cache0 {
		compatible = "cache";
		cache-level = <0x2>;
		cache-size = <0x100000>;
		cache-line-size = <0x40>;
		cache-sets = <0x400>;
		next-level-cache = <0x5>;
		phandle = <0x4>;
	};

	l3-cache0 {
		compatible = "cache";
		cache-level = <0x3>;
		phandle = <0x5>;
	};

	firmware {

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
			phandle = <0x8a>;
		};
	};

	timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
		phandle = <0x8b>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <0x1 0x7 0x4>;
		phandle = <0x8c>;
	};

	bus@100000 {
		compatible = "simple-bus";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges = <0x0 0x100000 0x0 0x100000 0x0 0x20000 0x0 0x600000 0x0 0x600000 0x0 0x31100 0x0 0x900000 0x0 0x900000 0x0 0x12000 0x0 0xa40000 0x0 0xa40000 0x0 0x800 0x0 0x6000000 0x0 0x6000000 0x0 0x400000 0x0 0x6400000 0x0 0x6400000 0x0 0x400000 0x0 0x1000000 0x0 0x1000000 0x0 0xaf02400 0x0 0x30000000 0x0 0x30000000 0x0 0xc400000 0x0 0xd000000 0x0 0xd000000 0x0 0x1800000 0x0 0xe000000 0x0 0xe000000 0x0 0x1800000 0x0 0x10000000 0x0 0x10000000 0x0 0x10000000 0x0 0x64800000 0x0 0x64800000 0x0 0x800000 0x44 0x0 0x44 0x0 0x0 0x8000000 0x44 0x10000000 0x44 0x10000000 0x0 0x8000000 0x4d 0x80800000 0x4d 0x80800000 0x0 0x800000 0x4d 0x81800000 0x4d 0x81800000 0x0 0x800000 0x4e 0x20000000 0x4e 0x20000000 0x0 0x80000 0x0 0x70000000 0x0 0x70000000 0x0 0x800000 0x0 0x28380000 0x0 0x28380000 0x0 0x3880000 0x0 0x40200000 0x0 0x40200000 0x0 0x998400 0x0 0x40f00000 0x0 0x40f00000 0x0 0x20000 0x0 0x41000000 0x0 0x41000000 0x0 0x20000 0x0 0x41400000 0x0 0x41400000 0x0 0x20000 0x0 0x41c00000 0x0 0x41c00000 0x0 0x100000 0x0 0x42040000 0x0 0x42040000 0x0 0x3ac2400 0x0 0x45100000 0x0 0x45100000 0x0 0xc24000 0x0 0x46000000 0x0 0x46000000 0x0 0x200000 0x0 0x47000000 0x0 0x47000000 0x0 0x68400 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000 0x5 0x0 0x5 0x0 0x1 0x0 0x7 0x0 0x7 0x0 0x1 0x0>;
		phandle = <0x8d>;

		bus@28380000 {
			compatible = "simple-bus";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges = <0x0 0x28380000 0x0 0x28380000 0x0 0x3880000 0x0 0x40200000 0x0 0x40200000 0x0 0x998400 0x0 0x40f00000 0x0 0x40f00000 0x0 0x20000 0x0 0x41000000 0x0 0x41000000 0x0 0x20000 0x0 0x41400000 0x0 0x41400000 0x0 0x20000 0x0 0x41c00000 0x0 0x41c00000 0x0 0x100000 0x0 0x42040000 0x0 0x42040000 0x0 0x3ac2400 0x0 0x45100000 0x0 0x45100000 0x0 0xc24000 0x0 0x46000000 0x0 0x46000000 0x0 0x200000 0x0 0x47000000 0x0 0x47000000 0x0 0x68400 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000 0x5 0x0 0x5 0x0 0x1 0x0 0x7 0x0 0x7 0x0 0x1 0x0>;
			phandle = <0x8e>;

			dmsc@44083000 {
				compatible = "ti,k2g-sci";
				ti,host-id = <0xc>;
				mbox-names = "rx", "tx";
				mboxes = <0x6 0xb 0x6 0xd>;
				reg-names = "debug_messages";
				reg = <0x0 0x44083000 0x0 0x1000>;
				phandle = <0xa>;

				power-controller {
					compatible = "ti,sci-pm-domain";
					#power-domain-cells = <0x2>;
					phandle = <0x8>;
				};

				clocks {
					compatible = "ti,k2g-sci-clk";
					#clock-cells = <0x2>;
					pinctrl-names = "default";
					pinctrl-0 = <0x7>;
					phandle = <0x9>;
				};

				reset-controller {
					compatible = "ti,sci-reset";
					#reset-cells = <0x2>;
					phandle = <0x17>;
				};
			};

			syscon@40f00000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x0 0x40f00000 0x0 0x20000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x0 0x40f00000 0x20000>;
				phandle = <0x14>;

				phy@4040 {
					compatible = "ti,am654-phy-gmii-sel";
					reg = <0x4040 0x4>;
					#phy-cells = <0x1>;
					phandle = <0x15>;
				};
			};

			chipid@43000014 {
				compatible = "ti,am654-chipid";
				reg = <0x0 0x43000014 0x0 0x4>;
			};

			pinctrl@4301c000 {
				compatible = "pinctrl-single";
				reg = <0x0 0x4301c000 0x0 0x178>;
				#pinctrl-cells = <0x1>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0xffffffff>;
				phandle = <0x8f>;

				wkup-i2c0-pins-default {
					pinctrl-single,pins = <0xf8 0x60000 0xfc 0x60000>;
					phandle = <0x90>;
				};

				mcu-fss0-ospi0-pins-default {
					pinctrl-single,pins = <0x0 0x10000 0x8 0x50000 0xc 0x50000 0x10 0x50000 0x14 0x50000 0x18 0x50000 0x1c 0x50000 0x20 0x50000 0x24 0x50000 0x28 0x50000 0x2c 0x10000>;
					phandle = <0xc>;
				};

				sw11-button-pins-default {
					pinctrl-single,pins = <0xcc 0x50007>;
					phandle = <0x80>;
				};

				mcu-fss0-ospi1-pins-default {
					pinctrl-single,pins = <0x34 0x10000 0x50 0x10000 0x40 0x50000 0x44 0x50000 0x48 0x50000 0x4c 0x50000 0x3c 0x50000 0x38 0x50000>;
					phandle = <0xd>;
				};

				mcu-cpsw-pins-default {
					pinctrl-single,pins = <0x58 0x10000 0x5c 0x50000 0x60 0x10000 0x64 0x10000 0x68 0x10000 0x6c 0x10000 0x78 0x50000 0x7c 0x50000 0x80 0x50000 0x84 0x50000 0x70 0x10000 0x74 0x50000>;
					phandle = <0x12>;
				};

				mcu-mdio1-pins-default {
					pinctrl-single,pins = <0x8c 0x10000 0x88 0x50000>;
					phandle = <0x13>;
				};

				mcu-mcan0-pins-default {
					pinctrl-single,pins = <0xac 0x50000 0xa8 0x10000>;
					phandle = <0x91>;
				};

				mcu-mcan0-gpio-pins-default {
					pinctrl-single,pins = <0xb0 0x50007 0x98 0x50007>;
					phandle = <0x92>;
				};

				mcu-mcan1-pins-default {
					pinctrl-single,pins = <0xc4 0x50000 0xc0 0x10000>;
					phandle = <0x93>;
				};

				mcu-mcan1-gpio-pins-default {
					pinctrl-single,pins = <0xb8 0x50007>;
					phandle = <0x94>;
				};
			};

			sram@41c00000 {
				compatible = "mmio-sram";
				reg = <0x0 0x41c00000 0x0 0x100000>;
				ranges = <0x0 0x0 0x41c00000 0x100000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				phandle = <0x95>;
			};

			serial@42300000 {
				compatible = "ti,j721e-uart", "ti,am654-uart";
				reg = <0x0 0x42300000 0x0 0x100>;
				reg-shift = <0x2>;
				reg-io-width = <0x4>;
				interrupts = <0x0 0x381 0x4>;
				clock-frequency = <0x2dc6c00>;
				current-speed = <0x1c200>;
				power-domains = <0x8 0x11f 0x1>;
				clocks = <0x9 0x11f 0x0>;
				clock-names = "fclk";
				status = "disabled";
				phandle = <0x96>;
			};

			serial@40a00000 {
				compatible = "ti,j721e-uart", "ti,am654-uart";
				reg = <0x0 0x40a00000 0x0 0x100>;
				reg-shift = <0x2>;
				reg-io-width = <0x4>;
				interrupts = <0x0 0x34e 0x4>;
				clock-frequency = <0x5b8d800>;
				current-speed = <0x1c200>;
				power-domains = <0x8 0x95 0x1>;
				clocks = <0x9 0x95 0x0>;
				clock-names = "fclk";
				phandle = <0x97>;
			};

			interrupt-controller2 {
				compatible = "ti,sci-intr";
				ti,intr-trigger-type = <0x1>;
				interrupt-controller;
				interrupt-parent = <0x1>;
				#interrupt-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0x89>;
				ti,interrupt-ranges = <0x10 0x3c0 0x10>;
				phandle = <0xb>;
			};

			gpio@42110000 {
				compatible = "ti,j721e-gpio", "ti,keystone-gpio";
				reg = <0x0 0x42110000 0x0 0x100>;
				gpio-controller;
				#gpio-cells = <0x2>;
				interrupt-parent = <0xb>;
				interrupts = <0x67 0x68 0x69 0x6a 0x6b 0x6c>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x0>;
				power-domains = <0x8 0x71 0x1>;
				clocks = <0x9 0x71 0x0>;
				clock-names = "gpio";
				phandle = <0x82>;
			};

			gpio@42100000 {
				compatible = "ti,j721e-gpio", "ti,keystone-gpio";
				reg = <0x0 0x42100000 0x0 0x100>;
				gpio-controller;
				#gpio-cells = <0x2>;
				interrupt-parent = <0xb>;
				interrupts = <0x70 0x71 0x72 0x73 0x74 0x75>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x0>;
				power-domains = <0x8 0x72 0x1>;
				clocks = <0x9 0x72 0x0>;
				clock-names = "gpio";
				status = "disabled";
				phandle = <0x98>;
			};

			i2c@40b00000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x40b00000 0x0 0x100>;
				interrupts = <0x0 0x354 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc2 0x0>;
				power-domains = <0x8 0xc2 0x1>;
				phandle = <0x99>;
			};

			i2c@40b10000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x40b10000 0x0 0x100>;
				interrupts = <0x0 0x355 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc3 0x0>;
				power-domains = <0x8 0xc3 0x1>;
				phandle = <0x9a>;
			};

			i2c@42120000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x42120000 0x0 0x100>;
				interrupts = <0x0 0x380 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc5 0x0>;
				power-domains = <0x8 0xc5 0x0>;
				phandle = <0x9b>;
			};

			fss@47000000 {
				compatible = "simple-bus";
				reg = <0x0 0x47000000 0x0 0x100>;
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				ranges;
				phandle = <0x9c>;

				spi@47040000 {
					compatible = "ti,am654-ospi";
					reg = <0x0 0x47040000 0x0 0x100 0x5 0x0 0x1 0x0>;
					interrupts = <0x0 0x348 0x4>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x4>;
					cdns,trigger-address = <0x0>;
					clocks = <0x9 0x67 0x0>;
					assigned-clocks = <0x9 0x67 0x0>;
					assigned-clock-parents = <0x9 0x67 0x2>;
					assigned-clock-rates = <0x9ef21aa>;
					power-domains = <0x8 0x67 0x1>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0xc>;
					phandle = <0x9d>;

					flash@0 {
						compatible = "jedec,spi-nor";
						reg = <0x0>;
						spi-tx-bus-width = <0x8>;
						spi-rx-bus-width = <0x8>;
						spi-max-frequency = <0x17d7840>;
						cdns,tshsl-ns = <0x3c>;
						cdns,tsd2d-ns = <0x3c>;
						cdns,tchsh-ns = <0x3c>;
						cdns,tslch-ns = <0x3c>;
						cdns,read-delay = <0x0>;
						#address-cells = <0x1>;
						#size-cells = <0x1>;
					};
				};

				spi@47050000 {
					compatible = "ti,am654-ospi";
					reg = <0x0 0x47050000 0x0 0x100 0x7 0x0 0x1 0x0>;
					interrupts = <0x0 0x349 0x4>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x4>;
					cdns,trigger-address = <0x0>;
					clocks = <0x9 0x68 0x0>;
					power-domains = <0x8 0x68 0x1>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0xd>;
					phandle = <0x9e>;

					flash@0 {
						compatible = "jedec,spi-nor";
						reg = <0x0>;
						spi-tx-bus-width = <0x1>;
						spi-rx-bus-width = <0x4>;
						spi-max-frequency = <0x2625a00>;
						cdns,tshsl-ns = <0x3c>;
						cdns,tsd2d-ns = <0x3c>;
						cdns,tchsh-ns = <0x3c>;
						cdns,tslch-ns = <0x3c>;
						cdns,read-delay = <0x2>;
						#address-cells = <0x1>;
						#size-cells = <0x1>;
					};
				};
			};

			tscadc@40200000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x0 0x40200000 0x0 0x1000>;
				interrupts = <0x0 0x35c 0x4>;
				power-domains = <0x8 0x0 0x1>;
				clocks = <0x9 0x0 0x1>;
				assigned-clocks = <0x9 0x0 0x3>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "adc_tsc_fck";
				dmas = <0xe 0x7400 0xe 0x7401>;
				dma-names = "fifo0", "fifo1";
				phandle = <0x9f>;

				adc {
					#io-channel-cells = <0x1>;
					compatible = "ti,am3359-adc";
				};
			};

			tscadc@40210000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x0 0x40210000 0x0 0x1000>;
				interrupts = <0x0 0x35d 0x4>;
				power-domains = <0x8 0x1 0x1>;
				clocks = <0x9 0x1 0x1>;
				assigned-clocks = <0x9 0x1 0x3>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "adc_tsc_fck";
				dmas = <0xe 0x7402 0xe 0x7403>;
				dma-names = "fifo0", "fifo1";
				phandle = <0xa0>;

				adc {
					#io-channel-cells = <0x1>;
					compatible = "ti,am3359-adc";
				};
			};

			mcu-navss {
				compatible = "simple-mfd";
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				ranges;
				dma-coherent;
				dma-ranges;
				ti,sci-dev-id = <0xe8>;

				ringacc@2b800000 {
					compatible = "ti,am654-navss-ringacc";
					reg = <0x0 0x2b800000 0x0 0x400000 0x0 0x2b000000 0x0 0x400000 0x0 0x28590000 0x0 0x100 0x0 0x2a500000 0x0 0x40000>;
					reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
					ti,num-rings = <0x11e>;
					ti,sci-rm-range-gp-rings = <0x1>;
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xeb>;
					msi-parent = <0xf>;
					phandle = <0x10>;
				};

				dma-controller@285c0000 {
					compatible = "ti,j721e-navss-mcu-udmap";
					reg = <0x0 0x285c0000 0x0 0x100 0x0 0x2a800000 0x0 0x40000 0x0 0x2aa00000 0x0 0x40000>;
					reg-names = "gcfg", "rchanrt", "tchanrt";
					msi-parent = <0xf>;
					#dma-cells = <0x1>;
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xec>;
					ti,ringacc = <0x10>;
					ti,sci-rm-range-tchan = <0xd 0xf>;
					ti,sci-rm-range-rchan = <0xa 0xb>;
					ti,sci-rm-range-rflow = <0x0>;
					phandle = <0x11>;
				};
			};

			ethernet@46000000 {
				compatible = "ti,j721e-cpsw-nuss";
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				reg = <0x0 0x46000000 0x0 0x200000>;
				reg-names = "cpsw_nuss";
				ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
				dma-coherent;
				clocks = <0x9 0x12 0x16>;
				clock-names = "fck";
				power-domains = <0x8 0x12 0x1>;
				dmas = <0x11 0xf000 0x11 0xf001 0x11 0xf002 0x11 0xf003 0x11 0xf004 0x11 0xf005 0x11 0xf006 0x11 0xf007 0x11 0x7000>;
				dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <0x12 0x13>;
				phandle = <0xa1>;

				ethernet-ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@1 {
						reg = <0x1>;
						ti,mac-only;
						label = "port1";
						ti,syscon-efuse = <0x14 0x200>;
						phys = <0x15 0x1>;
						phy-mode = "rgmii-rxid";
						phy-handle = <0x16>;
						phandle = <0xa2>;
					};
				};

				mdio@f00 {
					compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
					reg = <0x0 0xf00 0x0 0x100>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0x9 0x12 0x16>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					phandle = <0xa3>;

					ethernet-phy@0 {
						reg = <0x0>;
						ti,rx-internal-delay = <0x7>;
						ti,fifo-depth = <0x1>;
						phandle = <0x16>;
					};
				};

				cpts@3d000 {
					compatible = "ti,am65-cpts";
					reg = <0x0 0x3d000 0x0 0x400>;
					clocks = <0x9 0x12 0x2>;
					clock-names = "cpts";
					interrupts-extended = <0x1 0x0 0x35a 0x4>;
					interrupt-names = "cpts";
					ti,cpts-ext-ts-inputs = <0x4>;
					ti,cpts-periodic-outputs = <0x2>;
				};
			};

			r5fss@41000000 {
				compatible = "ti,j721e-r5fss";
				ti,cluster-mode = <0x1>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x41000000 0x0 0x41000000 0x20000 0x41400000 0x0 0x41400000 0x20000>;
				power-domains = <0x8 0xf9 0x1>;
				phandle = <0xa4>;

				r5f@41000000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41000000 0x8000 0x41010000 0x8000>;
					reg-names = "atcm", "btcm";
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xfa>;
					ti,sci-proc-ids = <0x1 0xff>;
					resets = <0x17 0xfa 0x1>;
					firmware-name = "j7-mcu-r5f0_0-fw";
					ti,atcm-enable = <0x1>;
					ti,btcm-enable = <0x1>;
					ti,loczrama = <0x1>;
					mboxes = <0x18 0x19>;
					memory-region = <0x1a 0x1b>;
					phandle = <0xa5>;
				};

				r5f@41400000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41400000 0x8000 0x41410000 0x8000>;
					reg-names = "atcm", "btcm";
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xfb>;
					ti,sci-proc-ids = <0x2 0xff>;
					resets = <0x17 0xfb 0x1>;
					firmware-name = "j7-mcu-r5f0_1-fw";
					ti,atcm-enable = <0x1>;
					ti,btcm-enable = <0x1>;
					ti,loczrama = <0x1>;
					mboxes = <0x18 0x1c>;
					memory-region = <0x1d 0x1e>;
					phandle = <0xa6>;
				};
			};

			can@40528000 {
				compatible = "bosch,m_can";
				reg = <0x0 0x40528000 0x0 0x200 0x0 0x40500000 0x0 0x8000>;
				reg-names = "m_can", "message_ram";
				power-domains = <0x8 0xac 0x1>;
				clocks = <0x9 0xac 0x0 0x9 0xac 0x1>;
				clock-names = "hclk", "cclk";
				interrupts = <0x0 0x340 0x4 0x0 0x341 0x4>;
				interrupt-names = "int0", "int1";
				bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xa7>;
			};

			can@40568000 {
				compatible = "bosch,m_can";
				reg = <0x0 0x40568000 0x0 0x200 0x0 0x40540000 0x0 0x8000>;
				reg-names = "m_can", "message_ram";
				power-domains = <0x8 0xad 0x1>;
				clocks = <0x9 0xad 0x0 0x9 0xad 0x1>;
				clock-names = "hclk", "cclk";
				interrupts = <0x0 0x343 0x4 0x0 0x344 0x4>;
				interrupt-names = "int0", "int1";
				bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xa8>;
			};
		};

		spi@2100000 {
			compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
			reg = <0x0 0x2100000 0x0 0x400>;
			interrupts = <0x0 0xb8 0x4>;
			clocks = <0x9 0x10a 0x1>;
			power-domains = <0x8 0x10a 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x1f>;
			status = "okay";
			phandle = <0xa9>;

			spidev@0 {
				spi-max-frequency = <0x16e3600>;
				reg = <0x0>;
				compatible = "linux,spidev";
			};
		};

		spi@2110000 {
			compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
			reg = <0x0 0x2110000 0x0 0x400>;
			interrupts = <0x0 0xb9 0x4>;
			clocks = <0x9 0x10b 0x1>;
			power-domains = <0x8 0x10b 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x20>;
			status = "okay";
			phandle = <0xaa>;

			spidev@0 {
				spi-max-frequency = <0x16e3600>;
				reg = <0x0>;
				compatible = "linux,spidev";
			};
		};

		sram@70000000 {
			compatible = "mmio-sram";
			reg = <0x0 0x70000000 0x0 0x800000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0x70000000 0x800000>;
			phandle = <0xab>;

			atf-sram@0 {
				reg = <0x0 0x20000>;
			};
		};

		scm-conf@100000 {
			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
			reg = <0x0 0x100000 0x0 0x1c000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0x100000 0x1c000>;
			phandle = <0x3f>;

			mux@4080 {
				compatible = "mmio-mux";
				reg = <0x4080 0x50>;
				#mux-control-cells = <0x1>;
				mux-reg-masks = <0x4080 0x3 0x4084 0x3 0x4090 0x3 0x4094 0x3 0x40a0 0x3 0x40a4 0x3 0x40b0 0x3 0x40b4 0x3 0x40c0 0x3 0x40c4 0x3 0x40c8 0x3 0x40cc 0x3>;
				idle-states = <0x1 0x0 0x1 0x1 0x1 0x1 0x2 0x2 0x0 0x0 0x0 0x0>;
				phandle = <0xac>;
			};

			phy@4044 {
				compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
				ti,qsgmii-main-ports = <0x2 0x1>;
				reg = <0x4044 0x20>;
				#phy-cells = <0x1>;
				phandle = <0xad>;
			};

			mux-controller@4000 {
				compatible = "mmio-mux";
				#mux-control-cells = <0x1>;
				mux-reg-masks = <0x4000 0x8000000 0x4010 0x8000000>;
				idle-states = <0x1 0x0>;
				phandle = <0xae>;
			};

			clock@4140 {
				compatible = "ti,am654-ehrpwm-tbclk", "syscon";
				reg = <0x4140 0x18>;
				#clock-cells = <0x1>;
				phandle = <0x21>;
			};
		};

		pwm@3000000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3000000 0x0 0x100>;
			power-domains = <0x8 0x53 0x1>;
			clocks = <0x21 0x0 0x9 0x53 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xaf>;
		};

		pwm@3010000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3010000 0x0 0x100>;
			power-domains = <0x8 0x54 0x1>;
			clocks = <0x21 0x1 0x9 0x54 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb0>;
		};

		pwm@3020000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3020000 0x0 0x100>;
			power-domains = <0x8 0x55 0x1>;
			clocks = <0x21 0x2 0x9 0x55 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb1>;
		};

		pwm@3030000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3030000 0x0 0x100>;
			power-domains = <0x8 0x56 0x1>;
			clocks = <0x21 0x3 0x9 0x56 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb2>;
		};

		pwm@3040000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3040000 0x0 0x100>;
			power-domains = <0x8 0x57 0x1>;
			clocks = <0x21 0x4 0x9 0x57 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb3>;
		};

		pwm@3050000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3050000 0x0 0x100>;
			power-domains = <0x8 0x58 0x1>;
			clocks = <0x21 0x5 0x9 0x58 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb4>;
		};

		interrupt-controller@1800000 {
			compatible = "arm,gic-v3";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			#interrupt-cells = <0x3>;
			interrupt-controller;
			reg = <0x0 0x1800000 0x0 0x10000 0x0 0x1900000 0x0 0x100000>;
			interrupts = <0x1 0x9 0x4>;
			phandle = <0x1>;

			msi-controller@1820000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x1820000 0x0 0x10000>;
				socionext,synquacer-pre-its = <0x1000000 0x400000>;
				msi-controller;
				#msi-cells = <0x1>;
				phandle = <0x40>;
			};
		};

		interrupt-controller0 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <0x1>;
			interrupt-controller;
			interrupt-parent = <0x1>;
			#interrupt-cells = <0x1>;
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x83>;
			ti,interrupt-ranges = <0x8 0x188 0x38>;
			phandle = <0x49>;
		};

		main-navss {
			compatible = "simple-mfd";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			dma-coherent;
			dma-ranges;
			ti,sci-dev-id = <0xc7>;

			interrupt-controller1 {
				compatible = "ti,sci-intr";
				ti,intr-trigger-type = <0x4>;
				interrupt-controller;
				interrupt-parent = <0x1>;
				#interrupt-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd5>;
				ti,interrupt-ranges = <0x0 0x40 0x40 0x40 0x1c0 0x40 0x80 0x2a0 0x40>;
				phandle = <0x22>;
			};

			interrupt-controller@33d00000 {
				compatible = "ti,sci-inta";
				reg = <0x0 0x33d00000 0x0 0x100000>;
				interrupt-controller;
				interrupt-parent = <0x22>;
				msi-controller;
				#interrupt-cells = <0x0>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd1>;
				ti,interrupt-ranges = <0x0 0x0 0x100>;
				phandle = <0xf>;
			};

			mailbox@32c00000 {
				compatible = "ti,am654-secure-proxy";
				#mbox-cells = <0x1>;
				reg-names = "target_data", "rt", "scfg";
				reg = <0x0 0x32c00000 0x0 0x100000 0x0 0x32400000 0x0 0x100000 0x0 0x32800000 0x0 0x100000>;
				interrupt-names = "rx_011";
				interrupts = <0x0 0x25 0x4>;
				phandle = <0x6>;
			};

			iommu@36600000 {
				compatible = "arm,smmu-v3";
				reg = <0x0 0x36600000 0x0 0x100000>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x304 0x1 0x0 0x300 0x1>;
				interrupt-names = "eventq", "gerror";
				#iommu-cells = <0x1>;
				phandle = <0xb5>;
			};

			spinlock@30e00000 {
				compatible = "ti,am654-hwspinlock";
				reg = <0x0 0x30e00000 0x0 0x1000>;
				#hwlock-cells = <0x1>;
				phandle = <0xb6>;
			};

			mailbox@31f80000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f80000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1b4>;
				phandle = <0x18>;

				mbox-mcu-r5fss0-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x19>;
				};

				mbox-mcu-r5fss0-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x1c>;
				};
			};

			mailbox@31f81000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f81000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1b0>;
				phandle = <0x5c>;

				mbox-main-r5fss0-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x5d>;
				};

				mbox-main-r5fss0-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x62>;
				};
			};

			mailbox@31f82000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f82000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1ac>;
				phandle = <0x65>;

				mbox-main-r5fss1-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x66>;
				};

				mbox-main-r5fss1-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x69>;
				};
			};

			mailbox@31f83000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f83000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1a8>;
				phandle = <0x6c>;

				mbox-c66-0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x6d>;
				};

				mbox-c66-1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x70>;
				};
			};

			mailbox@31f84000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f84000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1a4>;
				phandle = <0x73>;

				mbox-c71-0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x74>;
				};
			};

			mailbox@31f85000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f85000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb7>;
			};

			mailbox@31f86000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f86000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb8>;
			};

			mailbox@31f87000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f87000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb9>;
			};

			mailbox@31f88000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f88000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xba>;
			};

			mailbox@31f89000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f89000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbb>;
			};

			mailbox@31f8a000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f8a000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbc>;
			};

			mailbox@31f8b000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f8b000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbd>;
			};

			ringacc@3c000000 {
				compatible = "ti,am654-navss-ringacc";
				reg = <0x0 0x3c000000 0x0 0x400000 0x0 0x38000000 0x0 0x400000 0x0 0x31120000 0x0 0x100 0x0 0x33000000 0x0 0x40000>;
				reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
				ti,num-rings = <0x400>;
				ti,sci-rm-range-gp-rings = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd3>;
				msi-parent = <0xf>;
				phandle = <0x23>;
			};

			dma-controller@31150000 {
				compatible = "ti,j721e-navss-main-udmap";
				reg = <0x0 0x31150000 0x0 0x100 0x0 0x34000000 0x0 0x100000 0x0 0x35000000 0x0 0x100000>;
				reg-names = "gcfg", "rchanrt", "tchanrt";
				msi-parent = <0xf>;
				#dma-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd4>;
				ti,ringacc = <0x23>;
				ti,sci-rm-range-tchan = <0xd 0xf 0x10>;
				ti,sci-rm-range-rchan = <0xa 0xb 0xc>;
				ti,sci-rm-range-rflow = <0x0>;
				phandle = <0xe>;
			};

			cpts@310d0000 {
				compatible = "ti,j721e-cpts";
				reg = <0x0 0x310d0000 0x0 0x400>;
				reg-names = "cpts";
				clocks = <0x9 0xc9 0x1>;
				clock-names = "cpts";
				interrupts-extended = <0x22 0x187>;
				interrupt-names = "cpts";
				ti,cpts-periodic-outputs = <0x6>;
				ti,cpts-ext-ts-inputs = <0x8>;
			};
		};

		ethernet@c000000 {
			compatible = "ti,j721e-cpswxg-nuss";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			reg = <0x0 0xc000000 0x0 0x200000>;
			reg-names = "cpsw_nuss";
			ranges = <0x0 0x0 0x0 0xc000000 0x0 0x200000>;
			clocks = <0x9 0x13 0x59>;
			clock-names = "fck";
			power-domains = <0x8 0x13 0x1>;
			dmas = <0xe 0xca00 0xe 0xca01 0xe 0xca02 0xe 0xca03 0xe 0xca04 0xe 0xca05 0xe 0xca06 0xe 0xca07 0xe 0x4a00>;
			dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx";
			phandle = <0xbe>;

			ethernet-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@1 {
					reg = <0x1>;
					ti,mac-only;
					label = "port1";
					phandle = <0xbf>;
				};

				port@2 {
					reg = <0x2>;
					ti,mac-only;
					label = "port2";
					phandle = <0xc0>;
				};

				port@3 {
					reg = <0x3>;
					ti,mac-only;
					label = "port3";
					phandle = <0xc1>;
				};

				port@4 {
					reg = <0x4>;
					ti,mac-only;
					label = "port4";
					phandle = <0xc2>;
				};

				port@5 {
					reg = <0x5>;
					ti,mac-only;
					label = "port5";
					phandle = <0xc3>;
				};

				port@6 {
					reg = <0x6>;
					ti,mac-only;
					label = "port6";
					phandle = <0xc4>;
				};

				port@7 {
					reg = <0x7>;
					ti,mac-only;
					label = "port7";
					phandle = <0xc5>;
				};

				port@8 {
					reg = <0x8>;
					ti,mac-only;
					label = "port8";
					phandle = <0xc6>;
				};
			};

			mdio@f00 {
				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
				reg = <0x0 0xf00 0x0 0x100>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clocks = <0x9 0x13 0x59>;
				clock-names = "fck";
				bus_freq = <0xf4240>;
				phandle = <0xc7>;
			};

			cpts@3d000 {
				compatible = "ti,j721e-cpts";
				reg = <0x0 0x3d000 0x0 0x400>;
				clocks = <0x9 0x13 0x10>;
				clock-names = "cpts";
				interrupts-extended = <0x1 0x0 0x10 0x4>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <0x4>;
				ti,cpts-periodic-outputs = <0x2>;
			};
		};

		crypto@4e00000 {
			compatible = "ti,j721e-sa2ul";
			reg = <0x0 0x4e00000 0x0 0x1200>;
			power-domains = <0x8 0x108 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges = <0x0 0x4e00000 0x0 0x4e00000 0x0 0x30000>;
			dmas = <0xe 0xc000 0xe 0x4000 0xe 0x4001>;
			dma-names = "tx", "rx1", "rx2";
			dma-coherent;
			phandle = <0xc8>;

			rng@4e10000 {
				compatible = "inside-secure,safexcel-eip76";
				reg = <0x0 0x4e10000 0x0 0x7d>;
				interrupts = <0x0 0xb 0x4>;
				clocks = <0x9 0x108 0x1>;
				phandle = <0xc9>;
			};
		};

		pinctrl@11c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0x11c000 0x0 0x2b4>;
			#pinctrl-cells = <0x1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0xffffffff>;
			phandle = <0xca>;

			spi0_pins_default {
				pinctrl-single,pins = <0x1c8 0x50000 0x1c0 0x50000 0x1c4 0x50000 0x1cc 0x50000 0x1d0 0x50000>;
				phandle = <0x1f>;
			};

			spi1_pins_default {
				pinctrl-single,pins = <0x1dc 0x50000 0x1d4 0x50000 0x1e0 0x50000 0x1e4 0x50000>;
				phandle = <0x20>;
			};

			sw10-button-pins-default {
				pinctrl-single,pins = <0x0 0x50007>;
				phandle = <0x7f>;
			};

			main-mmc1-pins-default {
				pinctrl-single,pins = <0x254 0x50000 0x250 0x50000 0x2ac 0x50000 0x24c 0x50000 0x248 0x50000 0x244 0x50000 0x240 0x50000 0x258 0x50000 0x25c 0x50000>;
				phandle = <0x4c>;
			};

			vdd-sd-dv-alt-pins-default {
				pinctrl-single,pins = <0x210 0x50007>;
				phandle = <0x84>;
			};

			main-usbss0-pins-default {
				pinctrl-single,pins = <0x290 0x10000 0x210 0x50007>;
				phandle = <0x4d>;
			};

			main-usbss1-pins-default {
				pinctrl-single,pins = <0x214 0x10004>;
				phandle = <0x4f>;
			};

			dp0-pins-default {
				pinctrl-single,pins = <0x1c4 0x50005>;
				phandle = <0x57>;
			};

			main-i2c0-pins-default {
				pinctrl-single,pins = <0x220 0x60000 0x224 0x60000>;
				phandle = <0x50>;
			};

			main-i2c1-pins-default {
				pinctrl-single,pins = <0x228 0x60000 0x22c 0x60000>;
				phandle = <0x51>;
			};

			main-i2c3-pins-default {
				pinctrl-single,pins = <0x270 0x60004 0x274 0x60004>;
				phandle = <0x52>;
			};

			mcasp0-pins-default {
				pinctrl-single,pins = <0xd4 0xc 0xd8 0xc 0xb0 0xc 0xb4 0x4000c>;
				phandle = <0x5b>;
			};

			audi-ext-refclk2-pins-default {
				pinctrl-single,pins = <0x1a4 0x10003>;
				phandle = <0x7>;
			};

			main-mcan0-pins-default {
				pinctrl-single,pins = <0x208 0x50000 0x20c 0x10000>;
				phandle = <0xcb>;
			};

			main-mcan2-pins-default {
				pinctrl-single,pins = <0x1f0 0x50003 0x1f4 0x10003>;
				phandle = <0xcc>;
			};

			main-mcan2-gpio-pins-default {
				pinctrl-single,pins = <0x200 0x50007>;
				phandle = <0xcd>;
			};
		};

		wiz@5000000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x124 0x1>;
			clocks = <0x9 0x124 0x5 0x9 0x124 0xb 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x124 0xb 0x9 0x124 0x0>;
			assigned-clock-parents = <0x9 0x124 0xf 0x9 0x124 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5000000 0x0 0x5000000 0x10000>;
			phandle = <0x29>;

			pll0-refclk {
				clocks = <0x9 0x124 0xb 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x25>;
				assigned-clock-parents = <0x9 0x124 0xb>;
				phandle = <0x25>;
			};

			pll1-refclk {
				clocks = <0x9 0x124 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x27>;
				assigned-clock-parents = <0x26>;
				phandle = <0x27>;
			};

			refclk-dig {
				clocks = <0x9 0x124 0xb 0x9 0x124 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x28>;
				assigned-clock-parents = <0x26>;
				phandle = <0x28>;
			};

			cmn-refclk-dig-div {
				clocks = <0x28>;
				#clock-cells = <0x0>;
				phandle = <0x2a>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x27>;
				#clock-cells = <0x0>;
				phandle = <0x2b>;
			};

			serdes@5000000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5000000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x29 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x2a 0x2b 0x25 0x27>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xce>;
			};
		};

		wiz@5010000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x125 0x1>;
			clocks = <0x9 0x125 0x5 0x9 0x125 0xd 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x125 0xd 0x9 0x125 0x0>;
			assigned-clock-parents = <0x9 0x125 0x11 0x9 0x125 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5010000 0x0 0x5010000 0x10000>;
			phandle = <0x2f>;

			pll0-refclk {
				clocks = <0x9 0x125 0xd 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2c>;
				assigned-clock-parents = <0x9 0x125 0xd>;
				phandle = <0x2c>;
			};

			pll1-refclk {
				clocks = <0x9 0x125 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2d>;
				assigned-clock-parents = <0x26>;
				phandle = <0x2d>;
			};

			refclk-dig {
				clocks = <0x9 0x125 0xd 0x9 0x125 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2e>;
				assigned-clock-parents = <0x26>;
				phandle = <0x2e>;
			};

			cmn-refclk-dig-div {
				clocks = <0x2e>;
				#clock-cells = <0x0>;
				phandle = <0x30>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x2d>;
				#clock-cells = <0x0>;
				phandle = <0x31>;
			};

			serdes@5010000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5010000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x2f 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x30 0x31 0x2c 0x2d>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xcf>;
			};
		};

		wiz@5020000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x126 0x1>;
			clocks = <0x9 0x126 0x5 0x9 0x126 0xb 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x126 0xb 0x9 0x126 0x0>;
			assigned-clock-parents = <0x9 0x126 0xf 0x9 0x126 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5020000 0x0 0x5020000 0x10000>;
			phandle = <0x35>;

			pll0-refclk {
				clocks = <0x9 0x126 0xb 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x32>;
				assigned-clock-parents = <0x9 0x126 0xb>;
				phandle = <0x32>;
			};

			pll1-refclk {
				clocks = <0x9 0x126 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x33>;
				assigned-clock-parents = <0x26>;
				phandle = <0x33>;
			};

			refclk-dig {
				clocks = <0x9 0x126 0xb 0x9 0x126 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x34>;
				assigned-clock-parents = <0x26>;
				phandle = <0x34>;
			};

			cmn-refclk-dig-div {
				clocks = <0x34>;
				#clock-cells = <0x0>;
				phandle = <0x36>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x33>;
				#clock-cells = <0x0>;
				phandle = <0x37>;
			};

			serdes@5020000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5020000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x35 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x36 0x37 0x32 0x33>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xd0>;
			};
		};

		wiz@5030000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x127 0x1>;
			clocks = <0x9 0x127 0x5 0x9 0x127 0x9 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x127 0x9 0x9 0x127 0x0>;
			assigned-clock-parents = <0x9 0x127 0xd 0x9 0x127 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5030000 0x0 0x5030000 0x10000>;
			typec-dir-gpios = <0x38 0x3 0x0>;
			typec-dir-debounce-ms = <0x2bc>;
			phandle = <0x3c>;

			pll0-refclk {
				clocks = <0x9 0x127 0x9 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x39>;
				assigned-clock-parents = <0x9 0x127 0x9>;
				phandle = <0x39>;
			};

			pll1-refclk {
				clocks = <0x9 0x127 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x3a>;
				assigned-clock-parents = <0x9 0x127 0x0>;
				phandle = <0x3a>;
			};

			refclk-dig {
				clocks = <0x9 0x127 0x9 0x9 0x127 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x3b>;
				assigned-clock-parents = <0x9 0x127 0x9>;
				phandle = <0x3b>;
			};

			cmn-refclk-dig-div {
				clocks = <0x3b>;
				#clock-cells = <0x0>;
				phandle = <0x3d>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x3a>;
				#clock-cells = <0x0>;
				phandle = <0x3e>;
			};

			serdes@5030000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5030000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x3c 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x3d 0x3e 0x39 0x3a>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xd1>;

				phy@0 {
					reg = <0x0>;
					cdns,num-lanes = <0x2>;
					#phy-cells = <0x0>;
					cdns,phy-type = <0x4>;
					resets = <0x3c 0x1 0x3c 0x2>;
					phandle = <0x4e>;
				};
			};
		};

		pcie@2900000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2900000 0x0 0x1000 0x0 0x2907000 0x0 0x400 0x0 0xd000000 0x0 0x800000 0x0 0x10000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x13e 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4070>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xef 0x1>;
			clocks = <0x9 0xef 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x0 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x10001000 0x0 0x10001000 0x0 0x10000 0x2000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x41 0x0 0x0 0x0 0x0 0x2 0x41 0x0 0x0 0x0 0x0 0x3 0x41 0x0 0x0 0x0 0x0 0x4 0x41 0x0>;
			status = "disabled";
			phandle = <0xd2>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x1>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x138 0x1>;
				phandle = <0x41>;
			};
		};

		pcie-ep@2900000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2900000 0x0 0x1000 0x0 0x2907000 0x0 0x400 0x0 0xd000000 0x0 0x800000 0x0 0x10000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x13e 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4070>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xef 0x1>;
			clocks = <0x9 0xef 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd3>;
		};

		pcie@2910000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2910000 0x0 0x1000 0x0 0x2917000 0x0 0x400 0x0 0xd800000 0x0 0x800000 0x0 0x18000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x14a 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4074>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf0 0x1>;
			clocks = <0x9 0xf0 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x10000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x18001000 0x0 0x18001000 0x0 0x10000 0x2000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x42 0x0 0x0 0x0 0x0 0x2 0x42 0x0 0x0 0x0 0x0 0x3 0x42 0x0 0x0 0x0 0x0 0x4 0x42 0x0>;
			status = "disabled";
			phandle = <0xd4>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x144 0x1>;
				phandle = <0x42>;
			};
		};

		pcie-ep@2910000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2910000 0x0 0x1000 0x0 0x2917000 0x0 0x400 0x0 0xd800000 0x0 0x800000 0x0 0x18000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x14a 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4074>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf0 0x1>;
			clocks = <0x9 0xf0 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd5>;
		};

		pcie@2920000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2920000 0x0 0x1000 0x0 0x2927000 0x0 0x400 0x0 0xe000000 0x0 0x800000 0x44 0x0 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x156 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4078>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf1 0x1>;
			clocks = <0x9 0xf1 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x20000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x1000 0x44 0x1000 0x0 0x10000 0x2000000 0x0 0x11000 0x44 0x11000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x43 0x0 0x0 0x0 0x0 0x2 0x43 0x0 0x0 0x0 0x0 0x3 0x43 0x0 0x0 0x0 0x0 0x4 0x43 0x0>;
			status = "disabled";
			phandle = <0xd6>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x150 0x1>;
				phandle = <0x43>;
			};
		};

		pcie-ep@2920000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2920000 0x0 0x1000 0x0 0x2927000 0x0 0x400 0x0 0xe000000 0x0 0x800000 0x44 0x0 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x156 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4078>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf1 0x1>;
			clocks = <0x9 0xf1 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd7>;
		};

		pcie@2930000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2930000 0x0 0x1000 0x0 0x2937000 0x0 0x400 0x0 0xe800000 0x0 0x800000 0x44 0x10000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x162 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x407c>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf2 0x1>;
			clocks = <0x9 0xf2 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x30000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x1000 0x44 0x10001000 0x0 0x10000 0x2000000 0x0 0x11000 0x44 0x10011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x44 0x0 0x0 0x0 0x0 0x2 0x44 0x0 0x0 0x0 0x0 0x3 0x44 0x0 0x0 0x0 0x0 0x4 0x44 0x0>;
			status = "disabled";
			phandle = <0xd8>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x15c 0x1>;
				phandle = <0x44>;
			};
		};

		pcie-ep@2930000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2930000 0x0 0x1000 0x0 0x2937000 0x0 0x400 0x0 0xe800000 0x0 0x800000 0x44 0x10000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x162 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x407c>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf2 0x1>;
			clocks = <0x9 0xf2 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			status = "disabled";
			phandle = <0xd9>;
		};

		wiz@5050000 {
			compatible = "ti,j721e-wiz-10g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x129 0x1>;
			clocks = <0x9 0x129 0x1 0x9 0x129 0x9 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x129 0x9>;
			assigned-clock-parents = <0x9 0x129 0xa>;
			assigned-clock-rates = <0x124f800>;
			num-lanes = <0x4>;
			#reset-cells = <0x1>;
			ranges = <0x5050000 0x0 0x5050000 0x10000 0xa030a00 0x0 0xa030a00 0x40>;
			phandle = <0x48>;

			pll0-refclk {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_pll0_refclk";
				#clock-cells = <0x0>;
				assigned-clocks = <0x45>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x45>;
			};

			pll1-refclk {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_pll1_refclk";
				#clock-cells = <0x0>;
				assigned-clocks = <0x46>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x46>;
			};

			refclk-dig {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_refclk_dig";
				#clock-cells = <0x0>;
				assigned-clocks = <0x47>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x47>;
			};

			cmn-refclk-dig-div {
				clocks = <0x47>;
				#clock-cells = <0x0>;
				phandle = <0xda>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x46>;
				#clock-cells = <0x0>;
				phandle = <0xdb>;
			};

			serdes@5050000 {
				compatible = "ti,j721e-serdes-10g";
				reg = <0x5050000 0x10000 0xa030a00 0x40>;
				reg-names = "torrent_phy", "dptx_phy";
				resets = <0x48 0x0>;
				reset-names = "torrent_reset";
				clocks = <0x45>;
				clock-names = "refclk";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0xdc>;

				phy@0 {
					reg = <0x0>;
					resets = <0x48 0x1>;
					cdns,phy-type = <0x6>;
					cdns,num-lanes = <0x4>;
					cdns,max-bit-rate = <0x1518>;
					#phy-cells = <0x0>;
					phandle = <0x56>;
				};
			};
		};

		serial@2800000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2800000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc0 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x92 0x0>;
			clocks = <0x9 0x92 0x0>;
			clock-names = "fclk";
			phandle = <0xdd>;
		};

		serial@2810000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2810000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc1 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x116 0x1>;
			clocks = <0x9 0x116 0x0>;
			clock-names = "fclk";
			phandle = <0xde>;
		};

		serial@2820000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2820000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc2 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x117 0x1>;
			clocks = <0x9 0x117 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xdf>;
		};

		serial@2830000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2830000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc3 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x118 0x1>;
			clocks = <0x9 0x118 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe0>;
		};

		serial@2840000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2840000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc4 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x119 0x1>;
			clocks = <0x9 0x119 0x0>;
			clock-names = "fclk";
			phandle = <0xe1>;
		};

		serial@2850000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2850000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc5 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11a 0x1>;
			clocks = <0x9 0x11a 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe2>;
		};

		serial@2860000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2860000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc6 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11b 0x1>;
			clocks = <0x9 0x11b 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe3>;
		};

		serial@2870000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2870000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc7 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11c 0x1>;
			clocks = <0x9 0x11c 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe4>;
		};

		serial@2880000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2880000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xf8 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11d 0x1>;
			clocks = <0x9 0x11d 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe5>;
		};

		serial@2890000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2890000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xf9 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11e 0x1>;
			clocks = <0x9 0x11e 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe6>;
		};

		gpio@600000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x600000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x69 0x1>;
			clocks = <0x9 0x69 0x0>;
			clock-names = "gpio";
			phandle = <0x81>;
		};

		gpio@601000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x601000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x120 0x121 0x122>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6a 0x1>;
			clocks = <0x9 0x6a 0x0>;
			clock-names = "gpio";
			phandle = <0x38>;
		};

		gpio@610000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x610000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6b 0x1>;
			clocks = <0x9 0x6b 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe7>;
		};

		gpio@611000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x611000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x124 0x125 0x126>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6c 0x1>;
			clocks = <0x9 0x6c 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe8>;
		};

		gpio@620000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x620000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6d 0x1>;
			clocks = <0x9 0x6d 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe9>;
		};

		gpio@621000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x621000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x128 0x129 0x12a>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6e 0x1>;
			clocks = <0x9 0x6e 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xea>;
		};

		gpio@630000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x630000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x118 0x119 0x11a 0x11b 0x11c 0x11d 0x11e 0x11f>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6f 0x1>;
			clocks = <0x9 0x6f 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xeb>;
		};

		gpio@631000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x631000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x12c 0x12d 0x12e>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x70 0x1>;
			clocks = <0x9 0x70 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xec>;
		};

		mmc@4f80000 {
			compatible = "ti,j721e-sdhci-8bit";
			reg = <0x0 0x4f80000 0x0 0x1000 0x0 0x4f88000 0x0 0x400>;
			interrupts = <0x0 0x3 0x4>;
			power-domains = <0x8 0x5b 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5b 0x0 0x9 0x5b 0x1>;
			assigned-clocks = <0x9 0x5b 0x1>;
			assigned-clock-parents = <0x9 0x5b 0x2>;
			bus-width = <0x8>;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
			ti,otap-del-sel-legacy = <0xf>;
			ti,otap-del-sel-mmc-hs = <0xf>;
			ti,otap-del-sel-ddr52 = <0x5>;
			ti,otap-del-sel-hs200 = <0x6>;
			ti,otap-del-sel-hs400 = <0x0>;
			ti,itap-del-sel-legacy = <0x10>;
			ti,itap-del-sel-mmc-hs = <0xa>;
			ti,itap-del-sel-ddr52 = <0x3>;
			ti,trm-icp = <0x8>;
			ti,strobe-sel = <0x77>;
			dma-coherent;
			non-removable;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			phandle = <0xed>;
		};

		mmc@4fb0000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x0 0x4fb0000 0x0 0x1000 0x0 0x4fb8000 0x0 0x400>;
			interrupts = <0x0 0x4 0x4>;
			power-domains = <0x8 0x5c 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5c 0x5 0x9 0x5c 0x0>;
			assigned-clocks = <0x9 0x5c 0x0>;
			assigned-clock-parents = <0x9 0x5c 0x1>;
			ti,otap-del-sel-legacy = <0x0>;
			ti,otap-del-sel-sd-hs = <0xf>;
			ti,otap-del-sel-sdr12 = <0xf>;
			ti,otap-del-sel-sdr25 = <0xf>;
			ti,otap-del-sel-sdr50 = <0xc>;
			ti,otap-del-sel-ddr50 = <0xc>;
			ti,itap-del-sel-legacy = <0x0>;
			ti,itap-del-sel-sd-hs = <0x0>;
			ti,itap-del-sel-sdr12 = <0x0>;
			ti,itap-del-sel-sdr25 = <0x0>;
			ti,itap-del-sel-ddr50 = <0x2>;
			ti,trm-icp = <0x8>;
			ti,clkbuf-sel = <0x7>;
			dma-coherent;
			sdhci-caps-mask = <0x2 0x0>;
			vmmc-supply = <0x4a>;
			vqmmc-supply = <0x4b>;
			pinctrl-names = "default";
			pinctrl-0 = <0x4c>;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			phandle = <0xee>;
		};

		mmc@4f98000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x0 0x4f98000 0x0 0x1000 0x0 0x4f90000 0x0 0x400>;
			interrupts = <0x0 0x5 0x4>;
			power-domains = <0x8 0x5d 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5d 0x5 0x9 0x5d 0x0>;
			assigned-clocks = <0x9 0x5d 0x0>;
			assigned-clock-parents = <0x9 0x5d 0x1>;
			ti,otap-del-sel-legacy = <0x0>;
			ti,otap-del-sel-sd-hs = <0xf>;
			ti,otap-del-sel-sdr12 = <0xf>;
			ti,otap-del-sel-sdr25 = <0xf>;
			ti,otap-del-sel-sdr50 = <0xc>;
			ti,otap-del-sel-ddr50 = <0xc>;
			ti,itap-del-sel-legacy = <0x0>;
			ti,itap-del-sel-sd-hs = <0x0>;
			ti,itap-del-sel-sdr12 = <0x0>;
			ti,itap-del-sel-sdr25 = <0x0>;
			ti,itap-del-sel-ddr50 = <0x2>;
			ti,trm-icp = <0x8>;
			ti,clkbuf-sel = <0x7>;
			dma-coherent;
			sdhci-caps-mask = <0x2 0x0>;
			status = "disabled";
			phandle = <0xef>;
		};

		cdns-usb@4104000 {
			compatible = "ti,j721e-usb";
			reg = <0x0 0x4104000 0x0 0x100>;
			dma-coherent;
			power-domains = <0x8 0x120 0x1>;
			clocks = <0x9 0x120 0xf 0x9 0x120 0x3>;
			clock-names = "ref", "lpm";
			assigned-clocks = <0x9 0x120 0xf>;
			assigned-clock-parents = <0x9 0x120 0x10>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <0x4d>;
			ti,vbus-divider;
			phandle = <0xf0>;

			usb@6000000 {
				compatible = "cdns,usb3";
				reg = <0x0 0x6000000 0x0 0x10000 0x0 0x6010000 0x0 0x10000 0x0 0x6020000 0x0 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <0x0 0x60 0x4 0x0 0x66 0x4 0x0 0x78 0x4>;
				interrupt-names = "host", "peripheral", "otg";
				maximum-speed = "super-speed";
				dr_mode = "otg";
				phys = <0x4e>;
				phy-names = "cdns3,usb3-phy";
				phandle = <0xf1>;
			};
		};

		cdns-usb@4114000 {
			compatible = "ti,j721e-usb";
			reg = <0x0 0x4114000 0x0 0x100>;
			dma-coherent;
			power-domains = <0x8 0x121 0x1>;
			clocks = <0x9 0x121 0xf 0x9 0x121 0x3>;
			clock-names = "ref", "lpm";
			assigned-clocks = <0x9 0x121 0xf>;
			assigned-clock-parents = <0x9 0x121 0x10>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <0x4f>;
			ti,usb2-only;
			phandle = <0xf2>;

			usb@6400000 {
				compatible = "cdns,usb3";
				reg = <0x0 0x6400000 0x0 0x10000 0x0 0x6410000 0x0 0x10000 0x0 0x6420000 0x0 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <0x0 0x68 0x4 0x0 0x6e 0x4 0x0 0x79 0x4>;
				interrupt-names = "host", "peripheral", "otg";
				maximum-speed = "high-speed";
				dr_mode = "host";
				phandle = <0xf3>;
			};
		};

		i2c@2000000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2000000 0x0 0x100>;
			interrupts = <0x0 0xc8 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbb 0x0>;
			power-domains = <0x8 0xbb 0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x50>;
			clock-frequency = <0x61a80>;
			phandle = <0xf4>;

			gpio@20 {
				compatible = "ti,tca6416";
				reg = <0x20>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0xf5>;
			};

			gpio@22 {
				compatible = "ti,tca6424";
				reg = <0x22>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0xf6>;

				p08-hog {
					gpio-hog;
					gpios = <0x8 0x0>;
					output-high;
					line-name = "CTRL_PM_I2C_OE";
				};

				p09-hog {
					gpio-hog;
					gpios = <0x9 0x0>;
					output-low;
					line-name = "MCASP/TRACE_MUX_S0";
				};

				p10-hog {
					gpio-hog;
					gpios = <0xa 0x0>;
					output-high;
					line-name = "MCASP/TRACE_MUX_S1";
				};
			};
		};

		i2c@2010000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2010000 0x0 0x100>;
			interrupts = <0x0 0xc9 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbc 0x0>;
			power-domains = <0x8 0xbc 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x51>;
			clock-frequency = <0x61a80>;
			phandle = <0xf7>;
		};

		i2c@2020000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2020000 0x0 0x100>;
			interrupts = <0x0 0xca 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbd 0x0>;
			power-domains = <0x8 0xbd 0x1>;
			phandle = <0xf8>;
		};

		i2c@2030000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2030000 0x0 0x100>;
			interrupts = <0x0 0xcb 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbe 0x0>;
			power-domains = <0x8 0xbe 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x52>;
			clock-frequency = <0x61a80>;
			phandle = <0xf9>;

			gpio@20 {
				compatible = "ti,tca6408";
				reg = <0x20>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0x53>;
			};

			audio-codec@44 {
				compatible = "ti,pcm3168a";
				reg = <0x44>;
				#sound-dai-cells = <0x1>;
				reset-gpios = <0x53 0x0 0x1>;
				clocks = <0x9 0x9d 0x173>;
				clock-names = "scki";
				assigned-clocks = <0x9 0x9d 0x173>;
				assigned-clock-parents = <0x9 0x9d 0x190>;
				assigned-clock-rates = <0x1770000>;
				VDD1-supply = <0x54>;
				VDD2-supply = <0x54>;
				VCCAD1-supply = <0x55>;
				VCCAD2-supply = <0x55>;
				VCCDA1-supply = <0x55>;
				VCCDA2-supply = <0x55>;
				phandle = <0x86>;
			};
		};

		i2c@2040000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2040000 0x0 0x100>;
			interrupts = <0x0 0xcc 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbf 0x0>;
			power-domains = <0x8 0xbf 0x1>;
			phandle = <0xfa>;
		};

		i2c@2050000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2050000 0x0 0x100>;
			interrupts = <0x0 0xcd 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xc0 0x0>;
			power-domains = <0x8 0xc0 0x1>;
			phandle = <0xfb>;
		};

		i2c@2060000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2060000 0x0 0x100>;
			interrupts = <0x0 0xce 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xc1 0x0>;
			power-domains = <0x8 0xc1 0x1>;
			phandle = <0xfc>;
		};

		video-decoder@4300000 {
			compatible = "img,d5500-vxd";
			reg = <0x0 0x4300000 0x0 0x100000>;
			power-domains = <0x8 0x90 0x1>;
			interrupts = <0x0 0xb4 0x4>;
			phandle = <0xfd>;
		};

		video-encoder@4200000 {
			compatible = "img,vxe384";
			reg = <0x0 0x4200000 0x0 0x100000>;
			power-domains = <0x8 0x99 0x1>;
			interrupts = <0x0 0xb5 0x4>;
			phandle = <0xfe>;
		};

		ufs-wrapper@4e80000 {
			compatible = "ti,j721e-ufs";
			reg = <0x0 0x4e80000 0x0 0x100>;
			power-domains = <0x8 0x115 0x1>;
			clocks = <0x9 0x115 0x1>;
			assigned-clocks = <0x9 0x115 0x1>;
			assigned-clock-parents = <0x9 0x115 0x4>;
			ranges;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			phandle = <0xff>;

			ufs@4e84000 {
				compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
				reg = <0x0 0x4e84000 0x0 0x10000>;
				interrupts = <0x0 0x11 0x4>;
				freq-table-hz = <0xee6b280 0xee6b280 0x124f800 0x124f800 0x124f800 0x124f800>;
				clocks = <0x9 0x115 0x0 0x9 0x115 0x1 0x9 0x115 0x1>;
				clock-names = "core_clk", "phy_clk", "ref_clk";
				dma-coherent;
			};
		};

		dp-bridge@a000000 {
			compatible = "ti,j721e-mhdp8546";
			reg = <0x0 0xa000000 0x0 0x30a00 0x0 0x4f40000 0x0 0x20>;
			reg-names = "mhdptx", "j721e-intg";
			clocks = <0x9 0x97 0x24>;
			phys = <0x56>;
			phy-names = "dpphy";
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x266 0x4>;
			power-domains = <0x8 0x97 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x57>;
			phandle = <0x100>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x101>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x58>;
						phandle = <0x5a>;
					};
				};

				port@4 {
					reg = <0x4>;

					endpoint {
						remote-endpoint = <0x59>;
						phandle = <0x88>;
					};
				};
			};
		};

		dss@4a00000 {
			compatible = "ti,j721e-dss";
			reg = <0x0 0x4a00000 0x0 0x10000 0x0 0x4a10000 0x0 0x10000 0x0 0x4b00000 0x0 0x10000 0x0 0x4b10000 0x0 0x10000 0x0 0x4a20000 0x0 0x10000 0x0 0x4a30000 0x0 0x10000 0x0 0x4a50000 0x0 0x10000 0x0 0x4a60000 0x0 0x10000 0x0 0x4a70000 0x0 0x10000 0x0 0x4a90000 0x0 0x10000 0x0 0x4ab0000 0x0 0x10000 0x0 0x4ad0000 0x0 0x10000 0x0 0x4a80000 0x0 0x10000 0x0 0x4aa0000 0x0 0x10000 0x0 0x4ac0000 0x0 0x10000 0x0 0x4ae0000 0x0 0x10000 0x0 0x4af0000 0x0 0x10000>;
			reg-names = "common_m", "common_s0", "common_s1", "common_s2", "vidl1", "vidl2", "vid1", "vid2", "ovr1", "ovr2", "ovr3", "ovr4", "vp1", "vp2", "vp3", "vp4", "wb";
			clocks = <0x9 0x98 0x0 0x9 0x98 0x1 0x9 0x98 0x4 0x9 0x98 0x9 0x9 0x98 0xd>;
			clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
			power-domains = <0x8 0x98 0x1>;
			interrupts = <0x0 0x25a 0x4 0x0 0x25b 0x4 0x0 0x25c 0x4 0x0 0x25d 0x4>;
			interrupt-names = "common_m", "common_s0", "common_s1", "common_s2";
			assigned-clocks = <0x9 0x98 0x1 0x9 0x98 0x4 0x9 0x98 0x9 0x9 0x98 0xd>;
			assigned-clock-parents = <0x9 0x98 0x2 0x9 0x98 0x6 0x9 0x98 0xb 0x9 0x98 0x12>;
			phandle = <0x102>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x103>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x5a>;
						phandle = <0x58>;
					};
				};
			};
		};

		mcasp@2b00000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b00000 0x0 0x2000 0x0 0x2b08000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x220 0x4 0x0 0x221 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc400 0xe 0x4400>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xae 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xae 0x1>;
			#sound-dai-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x5b>;
			op-mode = <0x0>;
			tdm-slots = <0x8>;
			auxclk-fs-ratio = <0x100>;
			serial-dir = <0x1 0x2 0x0 0x0 0x0 0x0 0x0 0x0>;
			tx-num-evt = <0x8>;
			rx-num-evt = <0x8>;
			phandle = <0x85>;
		};

		mcasp@2b10000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b10000 0x0 0x2000 0x0 0x2b18000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x222 0x4 0x0 0x223 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc401 0xe 0x4401>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xaf 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xaf 0x1>;
			status = "disabled";
			phandle = <0x104>;
		};

		mcasp@2b20000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b20000 0x0 0x2000 0x0 0x2b28000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x224 0x4 0x0 0x225 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc402 0xe 0x4402>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb0 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb0 0x1>;
			status = "disabled";
			phandle = <0x105>;
		};

		mcasp@2b30000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b30000 0x0 0x2000 0x0 0x2b38000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x226 0x4 0x0 0x227 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc500 0xe 0x4500>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb1 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb1 0x1>;
			status = "disabled";
			phandle = <0x106>;
		};

		mcasp@2b40000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b40000 0x0 0x2000 0x0 0x2b48000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x228 0x4 0x0 0x229 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc501 0xe 0x4501>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb2 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb2 0x1>;
			status = "disabled";
			phandle = <0x107>;
		};

		mcasp@2b50000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b50000 0x0 0x2000 0x0 0x2b58000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22a 0x4 0x0 0x22b 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc502 0xe 0x4502>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb3 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb3 0x1>;
			status = "disabled";
			phandle = <0x108>;
		};

		mcasp@2b60000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b60000 0x0 0x2000 0x0 0x2b68000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22c 0x4 0x0 0x22d 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc503 0xe 0x4503>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb4 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb4 0x1>;
			status = "disabled";
			phandle = <0x109>;
		};

		mcasp@2b70000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b70000 0x0 0x2000 0x0 0x2b78000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22e 0x4 0x0 0x22f 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc504 0xe 0x4504>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb5 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb5 0x1>;
			status = "disabled";
			phandle = <0x10a>;
		};

		mcasp@2b80000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b80000 0x0 0x2000 0x0 0x2b88000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x230 0x4 0x0 0x231 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc505 0xe 0x4505>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb6 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb6 0x1>;
			status = "disabled";
			phandle = <0x10b>;
		};

		mcasp@2b90000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b90000 0x0 0x2000 0x0 0x2b98000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x232 0x4 0x0 0x233 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc506 0xe 0x4506>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb7 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb7 0x1>;
			status = "disabled";
			phandle = <0x10c>;
		};

		mcasp@2ba0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2ba0000 0x0 0x2000 0x0 0x2ba8000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x234 0x4 0x0 0x235 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc507 0xe 0x4507>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb8 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb8 0x1>;
			status = "disabled";
			phandle = <0x10d>;
		};

		mcasp@2bb0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2bb0000 0x0 0x2000 0x0 0x2bb8000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x236 0x4 0x0 0x237 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc508 0xe 0x4508>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb9 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb9 0x1>;
			status = "disabled";
			phandle = <0x10e>;
		};

		watchdog@2200000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x0 0x2200000 0x0 0x100>;
			clocks = <0x9 0xfc 0x1>;
			power-domains = <0x8 0xfc 0x1>;
			assigned-clocks = <0x9 0xfc 0x1>;
			assigned-clock-parents = <0x9 0xfc 0x5>;
			phandle = <0x10f>;
		};

		watchdog@2210000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x0 0x2210000 0x0 0x100>;
			clocks = <0x9 0xfd 0x1>;
			power-domains = <0x8 0xfd 0x1>;
			assigned-clocks = <0x9 0xfd 0x1>;
			assigned-clock-parents = <0x9 0xfd 0x5>;
			phandle = <0x110>;
		};

		r5fss@5c00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x0>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x5c00000 0x0 0x5c00000 0x20000 0x5d00000 0x0 0x5d00000 0x20000>;
			power-domains = <0x8 0xf3 0x1>;
			phandle = <0x111>;

			r5f@5c00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5c00000 0x8000 0x5c10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf5>;
				ti,sci-proc-ids = <0x6 0xff>;
				resets = <0x17 0xf5 0x1>;
				firmware-name = "j7-main-r5f0_0-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x5c 0x5d>;
				memory-region = <0x5e 0x5f 0x60 0x61>;
				phandle = <0x112>;
			};

			r5f@5d00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5d00000 0x8000 0x5d10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf6>;
				ti,sci-proc-ids = <0x7 0xff>;
				resets = <0x17 0xf6 0x1>;
				firmware-name = "j7-main-r5f0_1-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x5c 0x62>;
				memory-region = <0x63 0x64>;
				phandle = <0x113>;
			};
		};

		r5fss@5e00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x0>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x5e00000 0x0 0x5e00000 0x20000 0x5f00000 0x0 0x5f00000 0x20000>;
			power-domains = <0x8 0xf4 0x1>;
			phandle = <0x114>;

			r5f@5e00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5e00000 0x8000 0x5e10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf7>;
				ti,sci-proc-ids = <0x8 0xff>;
				resets = <0x17 0xf7 0x1>;
				firmware-name = "j7-main-r5f1_0-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x65 0x66>;
				memory-region = <0x67 0x68>;
				phandle = <0x115>;
			};

			r5f@5f00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5f00000 0x8000 0x5f10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf8>;
				ti,sci-proc-ids = <0x9 0xff>;
				resets = <0x17 0xf8 0x1>;
				firmware-name = "j7-main-r5f1_1-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x65 0x69>;
				memory-region = <0x6a 0x6b>;
				phandle = <0x116>;
			};
		};

		dsp@4d80800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x80800000 0x0 0x48000 0x4d 0x80e00000 0x0 0x8000 0x4d 0x80f00000 0x0 0x8000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x8e>;
			ti,sci-proc-ids = <0x3 0xff>;
			resets = <0x17 0x8e 0x1>;
			firmware-name = "j7-c66_0-fw";
			mboxes = <0x6c 0x6d>;
			memory-region = <0x6e 0x6f>;
			phandle = <0x117>;
		};

		dsp@4d81800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x81800000 0x0 0x48000 0x4d 0x81e00000 0x0 0x8000 0x4d 0x81f00000 0x0 0x8000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x8f>;
			ti,sci-proc-ids = <0x4 0xff>;
			resets = <0x17 0x8f 0x1>;
			firmware-name = "j7-c66_1-fw";
			mboxes = <0x6c 0x70>;
			memory-region = <0x71 0x72>;
			phandle = <0x118>;
		};

		dsp@64800000 {
			compatible = "ti,j721e-c71-dsp";
			reg = <0x0 0x64800000 0x0 0x80000 0x0 0x64e00000 0x0 0xc000>;
			reg-names = "l2sram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0xf>;
			ti,sci-proc-ids = <0x30 0xff>;
			resets = <0x17 0xf 0x1>;
			firmware-name = "j7-c71_0-fw";
			mboxes = <0x73 0x74>;
			memory-region = <0x75 0x76>;
			phandle = <0x119>;
		};

		icssg@b000000 {
			compatible = "ti,j721e-icssg";
			reg = <0x0 0xb000000 0x0 0x80000>;
			power-domains = <0x8 0x77 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0xb000000 0x100000>;
			phandle = <0x11a>;

			memories@0 {
				reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0", "dram1", "shrdram2";
				phandle = <0x11b>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg", "syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x26000 0x2000>;
				phandle = <0x11c>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x77 0x18 0x9 0x77 0x1>;
						assigned-clocks = <0x77>;
						assigned-clock-parents = <0x9 0x77 0x1>;
						phandle = <0x77>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x77 0x3 0x77>;
						assigned-clocks = <0x78>;
						assigned-clock-parents = <0x77>;
						phandle = <0x78>;
					};
				};
			};

			iep@2e000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2e000 0x1000>;
				clocks = <0x78>;
				phandle = <0x11d>;
			};

			iep@2f000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2f000 0x1000>;
				clocks = <0x78>;
				phandle = <0x11e>;
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii", "syscon";
				reg = <0x32000 0x100>;
				phandle = <0x11f>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g", "syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x120>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x3>;
				interrupts = <0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4 0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4 0x0 0x105 0x4>;
				interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7";
				phandle = <0x79>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x3000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru0_0-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x10 0x2 0x2>;
				interrupt-names = "vring";
				phandle = <0x121>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu0_0-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x14 0x4 0x4>;
				interrupt-names = "vring";
				phandle = <0x122>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru0_0-fw";
				phandle = <0x123>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x3000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru0_1-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x12 0x3 0x3>;
				interrupt-names = "vring";
				phandle = <0x124>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu0_1-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x16 0x5 0x5>;
				interrupt-names = "vring";
				phandle = <0x125>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru0_1-fw";
				phandle = <0x126>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x9 0x77 0x1>;
				clock-names = "fck";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x127>;
			};
		};

		icssg@b100000 {
			compatible = "ti,j721e-icssg";
			reg = <0x0 0xb100000 0x0 0x80000>;
			power-domains = <0x8 0x78 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0xb100000 0x100000>;
			phandle = <0x128>;

			memories@b100000 {
				reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0", "dram1", "shrdram2";
				phandle = <0x129>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg", "syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x26000 0x2000>;
				phandle = <0x12a>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x78 0x36 0x9 0x78 0x4>;
						assigned-clocks = <0x7a>;
						assigned-clock-parents = <0x9 0x78 0x4>;
						phandle = <0x7a>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x78 0x9 0x7a>;
						assigned-clocks = <0x7b>;
						assigned-clock-parents = <0x7a>;
						phandle = <0x7b>;
					};
				};
			};

			iep@2e000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2e000 0x1000>;
				clocks = <0x7b>;
				phandle = <0x12b>;
			};

			iep@2f000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2f000 0x1000>;
				clocks = <0x7b>;
				phandle = <0x12c>;
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii", "syscon";
				reg = <0x32000 0x100>;
				phandle = <0x12d>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g", "syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x12e>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x3>;
				interrupts = <0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4 0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4 0x0 0x10d 0x4>;
				interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7";
				phandle = <0x7c>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x4000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru1_0-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x10 0x2 0x2>;
				interrupt-names = "vring";
				phandle = <0x12f>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu1_0-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x14 0x4 0x4>;
				interrupt-names = "vring";
				phandle = <0x130>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru1_0-fw";
				phandle = <0x131>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x4000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru1_1-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x12 0x3 0x3>;
				interrupt-names = "vring";
				phandle = <0x132>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu1_1-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x16 0x5 0x5>;
				interrupt-names = "vring";
				phandle = <0x133>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru1_1-fw";
				phandle = <0x134>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x9 0x78 0x4>;
				clock-names = "fck";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x135>;
			};
		};

		timesync_router@A40000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xa40000 0x0 0x800>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			#pinctrl-cells = <0x1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x107ff>;
			status = "disabled";
			phandle = <0x136>;
		};

		gpu@4e20000000 {
			compatible = "ti,j721e-pvr", "img,pvr-ge8430";
			reg = <0x4e 0x20000000 0x0 0x80000>;
			reg-names = "gpu_regs";
			interrupts = <0x0 0x18 0x4>;
			power-domains = <0x8 0x7d 0x1 0x8 0x7e 0x1>;
			power-domain-names = "gpu_0", "gpucore_0";
			clocks = <0x9 0x7d 0x0>;
			clock-names = "ctrl";
			phandle = <0x137>;
		};

		can@2701000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2701000 0x0 0x200 0x0 0x2708000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0x9c 0x1>;
			clocks = <0x9 0x9c 0x0 0x9 0x9c 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x7c 0x4 0x0 0x7d 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x138>;
		};

		can@2711000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2711000 0x0 0x200 0x0 0x2718000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0x9e 0x1>;
			clocks = <0x9 0x9e 0x0 0x9 0x9e 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x7f 0x4 0x0 0x80 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x139>;
		};

		can@2721000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2721000 0x0 0x200 0x0 0x2728000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa0 0x1>;
			clocks = <0x9 0xa0 0x0 0x9 0xa0 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x82 0x4 0x0 0x83 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13a>;
		};

		can@2731000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2731000 0x0 0x200 0x0 0x2738000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa1 0x1>;
			clocks = <0x9 0xa1 0x0 0x9 0xa1 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x85 0x4 0x0 0x86 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13b>;
		};

		can@2741000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2741000 0x0 0x200 0x0 0x2748000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa2 0x1>;
			clocks = <0x9 0xa2 0x0 0x9 0xa2 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x88 0x4 0x0 0x89 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13c>;
		};

		can@2751000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2751000 0x0 0x200 0x0 0x2758000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa3 0x1>;
			clocks = <0x9 0xa3 0x0 0x9 0xa3 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x8b 0x4 0x0 0x8c 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13d>;
		};

		can@2761000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2761000 0x0 0x200 0x0 0x2768000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa4 0x1>;
			clocks = <0x9 0xa4 0x0 0x9 0xa4 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x8e 0x4 0x0 0x8f 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13e>;
		};

		can@2771000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2771000 0x0 0x200 0x0 0x2778000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa5 0x1>;
			clocks = <0x9 0xa5 0x0 0x9 0xa5 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x91 0x4 0x0 0x92 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13f>;
		};

		can@2781000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2781000 0x0 0x200 0x0 0x2788000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa6 0x1>;
			clocks = <0x9 0xa6 0x0 0x9 0xa6 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x240 0x4 0x0 0x241 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x140>;
		};

		can@2791000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2791000 0x0 0x200 0x0 0x2798000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa7 0x1>;
			clocks = <0x9 0xa7 0x0 0x9 0xa7 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x243 0x4 0x0 0x244 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x141>;
		};

		can@27a1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27a1000 0x0 0x200 0x0 0x27a8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa8 0x1>;
			clocks = <0x9 0xa8 0x0 0x9 0xa8 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x246 0x4 0x0 0x247 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x142>;
		};

		can@27b1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27b1000 0x0 0x200 0x0 0x27b8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa9 0x1>;
			clocks = <0x9 0xa9 0x0 0x9 0xa9 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x249 0x4 0x0 0x24a 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x143>;
		};

		can@27c1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27c1000 0x0 0x200 0x0 0x27c8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xaa 0x1>;
			clocks = <0x9 0xaa 0x0 0x9 0xaa 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x24c 0x4 0x0 0x24d 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x144>;
		};

		can@27d1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27d1000 0x0 0x200 0x0 0x27d8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xab 0x1>;
			clocks = <0x9 0xab 0x0 0x9 0xab 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x24f 0x4 0x0 0x250 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x145>;
		};

		ticsi2rx@4500000 {
			compatible = "ti,j721e-csi2rx";
			dmas = <0xe 0x4940 0xe 0x4941 0xe 0x4942 0xe 0x4943 0xe 0x4944 0xe 0x4945 0xe 0x4946 0xe 0x4947 0xe 0x4948 0xe 0x4949 0xe 0x494a 0xe 0x494b 0xe 0x494c 0xe 0x494d 0xe 0x494e 0xe 0x494f>;
			dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
			reg = <0x0 0x4500000 0x0 0x1000>;
			power-domains = <0x8 0x1a 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			phandle = <0x146>;

			csi-bridge@4504000 {
				compatible = "cdns,csi2rx";
				reg = <0x0 0x4504000 0x0 0x1000>;
				clocks = <0x9 0x1a 0x2 0x9 0x1a 0x0 0x9 0x1a 0x2 0x9 0x1a 0x2 0x9 0x1a 0x3 0x9 0x1a 0x3>;
				clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
				phys = <0x7d>;
				phy-names = "dphy";
				power-domains = <0x8 0x1a 0x1>;
				phandle = <0x147>;

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;
						status = "disabled";
						phandle = <0x148>;
					};

					port@1 {
						reg = <0x1>;
						status = "disabled";
						phandle = <0x149>;
					};

					port@2 {
						reg = <0x2>;
						status = "disabled";
						phandle = <0x14a>;
					};

					port@3 {
						reg = <0x3>;
						status = "disabled";
						phandle = <0x14b>;
					};

					port@4 {
						reg = <0x4>;
						status = "disabled";
						phandle = <0x14c>;
					};
				};
			};
		};

		ticsi2rx@4510000 {
			compatible = "ti,j721e-csi2rx";
			dmas = <0xe 0x4960 0xe 0x4961 0xe 0x4962 0xe 0x4963 0xe 0x4964 0xe 0x4965 0xe 0x4966 0xe 0x4967 0xe 0x4968 0xe 0x4969 0xe 0x496a 0xe 0x496b 0xe 0x496c 0xe 0x496d 0xe 0x496e 0xe 0x496f>;
			dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
			reg = <0x0 0x4510000 0x0 0x1000>;
			power-domains = <0x8 0x1b 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			phandle = <0x14d>;

			csi-bridge@4514000 {
				compatible = "cdns,csi2rx";
				reg = <0x0 0x4514000 0x0 0x1000>;
				clocks = <0x9 0x1b 0x2 0x9 0x1b 0x0 0x9 0x1b 0x2 0x9 0x1b 0x2 0x9 0x1b 0x3 0x9 0x1b 0x3>;
				clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
				phys = <0x7e>;
				phy-names = "dphy";
				power-domains = <0x8 0x1b 0x1>;
				phandle = <0x14e>;

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;
						phandle = <0x14f>;
					};

					port@1 {
						reg = <0x1>;
						phandle = <0x150>;
					};

					port@2 {
						reg = <0x2>;
						phandle = <0x151>;
					};

					port@3 {
						reg = <0x3>;
						phandle = <0x152>;
					};

					port@4 {
						reg = <0x4>;
						phandle = <0x153>;
					};
				};
			};
		};

		phy@4580000 {
			compatible = "ti,j721e-dphy", "cdns,dphy";
			reg = <0x0 0x4580000 0x0 0x1100>;
			#phy-cells = <0x0>;
			power-domains = <0x8 0x93 0x1>;
			phandle = <0x7d>;
		};

		phy@4590000 {
			compatible = "ti,j721e-dphy", "cdns,dphy";
			reg = <0x0 0x4590000 0x0 0x1100>;
			#phy-cells = <0x0>;
			power-domains = <0x8 0x94 0x1>;
			phandle = <0x7e>;
		};
	};

	clock-cmnrefclk {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x0>;
		phandle = <0x24>;
	};

	clock-cmnrefclk1 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x5f5e100>;
		phandle = <0x26>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000 0x8 0x80000000 0x0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		phandle = <0x154>;

		optee@9e800000 {
			reg = <0x0 0x9e800000 0x0 0x1800000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x155>;
		};

		r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa0000000 0x0 0x100000>;
			no-map;
			phandle = <0x1a>;
		};

		r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa0100000 0x0 0xf00000>;
			no-map;
			phandle = <0x1b>;
		};

		r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa1000000 0x0 0x100000>;
			no-map;
			phandle = <0x1d>;
		};

		r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa1100000 0x0 0xf00000>;
			no-map;
			phandle = <0x1e>;
		};

		r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa2000000 0x0 0x100000>;
			no-map;
			phandle = <0x5e>;
		};

		r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa2100000 0x0 0xf00000>;
			no-map;
			phandle = <0x5f>;
		};

		r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa3000000 0x0 0x100000>;
			no-map;
			phandle = <0x63>;
		};

		r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa3100000 0x0 0xf00000>;
			no-map;
			phandle = <0x64>;
		};

		r5f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa4000000 0x0 0x100000>;
			no-map;
			phandle = <0x67>;
		};

		r5f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa4100000 0x0 0xf00000>;
			no-map;
			phandle = <0x68>;
		};

		r5f-dma-memory@a5000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa5000000 0x0 0x100000>;
			no-map;
			phandle = <0x6a>;
		};

		r5f-memory@a5100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa5100000 0x0 0xf00000>;
			no-map;
			phandle = <0x6b>;
		};

		c66-dma-memory@a6000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa6000000 0x0 0x100000>;
			no-map;
			phandle = <0x71>;
		};

		c66-memory@a6100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa6100000 0x0 0xf00000>;
			no-map;
			phandle = <0x6f>;
		};

		c66-dma-memory@a7000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa7000000 0x0 0x100000>;
			no-map;
			phandle = <0x6e>;
		};

		c66-memory@a7100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa7100000 0x0 0xf00000>;
			no-map;
			phandle = <0x72>;
		};

		c71-dma-memory@a8000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa8000000 0x0 0x100000>;
			no-map;
			phandle = <0x75>;
		};

		c71-memory@a8100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa8100000 0x0 0xf00000>;
			no-map;
			phandle = <0x76>;
		};

		ipc-memories@aa000000 {
			reg = <0x0 0xaa000000 0x0 0x1c00000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x156>;
		};

		r5f-virtual-eth-queues@ac000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xac000000 0x0 0x200000>;
			no-map;
			phandle = <0x60>;
		};

		r5f-virtual-eth-buffers@ac200000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xac200000 0x0 0x1e00000>;
			no-map;
			phandle = <0x61>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <0x7f 0x80>;
		phandle = <0x157>;

		sw10 {
			label = "GPIO Key USER1";
			linux,code = <0x100>;
			gpios = <0x81 0x0 0x1>;
			phandle = <0x158>;
		};

		sw11 {
			label = "GPIO Key USER2";
			linux,code = <0x101>;
			gpios = <0x82 0x7 0x1>;
			phandle = <0x159>;
		};
	};

	fixedregulator-evm12v0 {
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x83>;
	};

	fixedregulator-vsys3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0x83>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x54>;
	};

	fixedregulator-vsys5v0 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x83>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x55>;
	};

	fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <0x54>;
		phandle = <0x4a>;
	};

	gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <0x84>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		vin-supply = <0x55>;
		states = <0x325aa0 0x0 0x325aa0 0x1>;
		phandle = <0x4b>;
	};

	sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";
		ti,cpb-mcasp = <0x85>;
		ti,cpb-codec = <0x86>;
		clocks = <0x9 0xb8 0x1 0x9 0xb8 0x2 0x9 0xb8 0x4 0x9 0x9d 0x173 0x9 0x9d 0x190 0x9 0x9d 0x191>;
		clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", "cpb-codec-scki", "cpb-codec-scki-48000", "cpb-codec-scki-44100";
		phandle = <0x15a>;
	};

	fixedregulator-dp-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		enable-active-high;
		regulator-always-on;
		phandle = <0x87>;
	};

	connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <0x87>;
		phandle = <0x15b>;

		port {

			endpoint {
				remote-endpoint = <0x88>;
				phandle = <0x59>;
			};
		};
	};

	__symbols__ {
		cluster0 = "/cpus/cpu-map/cluster0";
		cpu0 = "/cpus/cpu@0";
		cpu1 = "/cpus/cpu@1";
		L2_0 = "/l2-cache0";
		msmc_l3 = "/l3-cache0";
		psci = "/firmware/psci";
		a72_timer0 = "/timer-cl0-cpu0";
		pmu = "/pmu";
		cbass_main = "/bus@100000";
		cbass_mcu_wakeup = "/bus@100000/bus@28380000";
		dmsc = "/bus@100000/bus@28380000/dmsc@44083000";
		k3_pds = "/bus@100000/bus@28380000/dmsc@44083000/power-controller";
		k3_clks = "/bus@100000/bus@28380000/dmsc@44083000/clocks";
		k3_reset = "/bus@100000/bus@28380000/dmsc@44083000/reset-controller";
		mcu_conf = "/bus@100000/bus@28380000/syscon@40f00000";
		phy_gmii_sel = "/bus@100000/bus@28380000/syscon@40f00000/phy@4040";
		wkup_pmx0 = "/bus@100000/bus@28380000/pinctrl@4301c000";
		wkup_i2c0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/wkup-i2c0-pins-default";
		mcu_fss0_ospi0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-ospi0-pins-default";
		sw11_button_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/sw11-button-pins-default";
		mcu_fss0_ospi1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-ospi1-pins-default";
		mcu_cpsw_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-cpsw-pins-default";
		mcu_mdio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mdio1-pins-default";
		mcu_mcan0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-pins-default";
		mcu_mcan0_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-gpio-pins-default";
		mcu_mcan1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-pins-default";
		mcu_mcan1_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-gpio-pins-default";
		mcu_ram = "/bus@100000/bus@28380000/sram@41c00000";
		wkup_uart0 = "/bus@100000/bus@28380000/serial@42300000";
		mcu_uart0 = "/bus@100000/bus@28380000/serial@40a00000";
		wkup_gpio_intr = "/bus@100000/bus@28380000/interrupt-controller2";
		wkup_gpio0 = "/bus@100000/bus@28380000/gpio@42110000";
		wkup_gpio1 = "/bus@100000/bus@28380000/gpio@42100000";
		mcu_i2c0 = "/bus@100000/bus@28380000/i2c@40b00000";
		mcu_i2c1 = "/bus@100000/bus@28380000/i2c@40b10000";
		wkup_i2c0 = "/bus@100000/bus@28380000/i2c@42120000";
		fss = "/bus@100000/bus@28380000/fss@47000000";
		ospi0 = "/bus@100000/bus@28380000/fss@47000000/spi@47040000";
		ospi1 = "/bus@100000/bus@28380000/fss@47000000/spi@47050000";
		tscadc0 = "/bus@100000/bus@28380000/tscadc@40200000";
		tscadc1 = "/bus@100000/bus@28380000/tscadc@40210000";
		mcu_ringacc = "/bus@100000/bus@28380000/mcu-navss/ringacc@2b800000";
		mcu_udmap = "/bus@100000/bus@28380000/mcu-navss/dma-controller@285c0000";
		mcu_cpsw = "/bus@100000/bus@28380000/ethernet@46000000";
		cpsw_port1 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
		davinci_mdio = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00";
		phy0 = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0";
		mcu_r5fss0 = "/bus@100000/bus@28380000/r5fss@41000000";
		mcu_r5fss0_core0 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41000000";
		mcu_r5fss0_core1 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41400000";
		mcu_mcan0 = "/bus@100000/bus@28380000/can@40528000";
		mcu_mcan1 = "/bus@100000/bus@28380000/can@40568000";
		main_spi0 = "/bus@100000/spi@2100000";
		main_spi1 = "/bus@100000/spi@2110000";
		msmc_ram = "/bus@100000/sram@70000000";
		scm_conf = "/bus@100000/scm-conf@100000";
		serdes_ln_ctrl = "/bus@100000/scm-conf@100000/mux@4080";
		cpsw0_phy_gmii_sel = "/bus@100000/scm-conf@100000/phy@4044";
		usb_serdes_mux = "/bus@100000/scm-conf@100000/mux-controller@4000";
		ehrpwm_tbclk = "/bus@100000/scm-conf@100000/clock@4140";
		main_ehrpwm0 = "/bus@100000/pwm@3000000";
		main_ehrpwm1 = "/bus@100000/pwm@3010000";
		main_ehrpwm2 = "/bus@100000/pwm@3020000";
		main_ehrpwm3 = "/bus@100000/pwm@3030000";
		main_ehrpwm4 = "/bus@100000/pwm@3040000";
		main_ehrpwm5 = "/bus@100000/pwm@3050000";
		gic500 = "/bus@100000/interrupt-controller@1800000";
		gic_its = "/bus@100000/interrupt-controller@1800000/msi-controller@1820000";
		main_gpio_intr = "/bus@100000/interrupt-controller0";
		main_navss_intr = "/bus@100000/main-navss/interrupt-controller1";
		main_udmass_inta = "/bus@100000/main-navss/interrupt-controller@33d00000";
		secure_proxy_main = "/bus@100000/main-navss/mailbox@32c00000";
		smmu0 = "/bus@100000/main-navss/iommu@36600000";
		hwspinlock = "/bus@100000/main-navss/spinlock@30e00000";
		mailbox0_cluster0 = "/bus@100000/main-navss/mailbox@31f80000";
		mbox_mcu_r5fss0_core0 = "/bus@100000/main-navss/mailbox@31f80000/mbox-mcu-r5fss0-core0";
		mbox_mcu_r5fss0_core1 = "/bus@100000/main-navss/mailbox@31f80000/mbox-mcu-r5fss0-core1";
		mailbox0_cluster1 = "/bus@100000/main-navss/mailbox@31f81000";
		mbox_main_r5fss0_core0 = "/bus@100000/main-navss/mailbox@31f81000/mbox-main-r5fss0-core0";
		mbox_main_r5fss0_core1 = "/bus@100000/main-navss/mailbox@31f81000/mbox-main-r5fss0-core1";
		mailbox0_cluster2 = "/bus@100000/main-navss/mailbox@31f82000";
		mbox_main_r5fss1_core0 = "/bus@100000/main-navss/mailbox@31f82000/mbox-main-r5fss1-core0";
		mbox_main_r5fss1_core1 = "/bus@100000/main-navss/mailbox@31f82000/mbox-main-r5fss1-core1";
		mailbox0_cluster3 = "/bus@100000/main-navss/mailbox@31f83000";
		mbox_c66_0 = "/bus@100000/main-navss/mailbox@31f83000/mbox-c66-0";
		mbox_c66_1 = "/bus@100000/main-navss/mailbox@31f83000/mbox-c66-1";
		mailbox0_cluster4 = "/bus@100000/main-navss/mailbox@31f84000";
		mbox_c71_0 = "/bus@100000/main-navss/mailbox@31f84000/mbox-c71-0";
		mailbox0_cluster5 = "/bus@100000/main-navss/mailbox@31f85000";
		mailbox0_cluster6 = "/bus@100000/main-navss/mailbox@31f86000";
		mailbox0_cluster7 = "/bus@100000/main-navss/mailbox@31f87000";
		mailbox0_cluster8 = "/bus@100000/main-navss/mailbox@31f88000";
		mailbox0_cluster9 = "/bus@100000/main-navss/mailbox@31f89000";
		mailbox0_cluster10 = "/bus@100000/main-navss/mailbox@31f8a000";
		mailbox0_cluster11 = "/bus@100000/main-navss/mailbox@31f8b000";
		main_ringacc = "/bus@100000/main-navss/ringacc@3c000000";
		main_udmap = "/bus@100000/main-navss/dma-controller@31150000";
		cpsw0 = "/bus@100000/ethernet@c000000";
		cpsw0_port1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
		cpsw0_port2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
		cpsw0_port3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
		cpsw0_port4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
		cpsw0_port5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
		cpsw0_port6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
		cpsw0_port7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
		cpsw0_port8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
		cpsw9g_mdio = "/bus@100000/ethernet@c000000/mdio@f00";
		main_crypto = "/bus@100000/crypto@4e00000";
		rng = "/bus@100000/crypto@4e00000/rng@4e10000";
		main_pmx0 = "/bus@100000/pinctrl@11c000";
		spi0_pins_default = "/bus@100000/pinctrl@11c000/spi0_pins_default";
		spi1_pins_default = "/bus@100000/pinctrl@11c000/spi1_pins_default";
		sw10_button_pins_default = "/bus@100000/pinctrl@11c000/sw10-button-pins-default";
		main_mmc1_pins_default = "/bus@100000/pinctrl@11c000/main-mmc1-pins-default";
		vdd_sd_dv_alt_pins_default = "/bus@100000/pinctrl@11c000/vdd-sd-dv-alt-pins-default";
		main_usbss0_pins_default = "/bus@100000/pinctrl@11c000/main-usbss0-pins-default";
		main_usbss1_pins_default = "/bus@100000/pinctrl@11c000/main-usbss1-pins-default";
		dp0_pins_default = "/bus@100000/pinctrl@11c000/dp0-pins-default";
		main_i2c0_pins_default = "/bus@100000/pinctrl@11c000/main-i2c0-pins-default";
		main_i2c1_pins_default = "/bus@100000/pinctrl@11c000/main-i2c1-pins-default";
		main_i2c3_pins_default = "/bus@100000/pinctrl@11c000/main-i2c3-pins-default";
		mcasp0_pins_default = "/bus@100000/pinctrl@11c000/mcasp0-pins-default";
		audi_ext_refclk2_pins_default = "/bus@100000/pinctrl@11c000/audi-ext-refclk2-pins-default";
		main_mcan0_pins_default = "/bus@100000/pinctrl@11c000/main-mcan0-pins-default";
		main_mcan2_pins_default = "/bus@100000/pinctrl@11c000/main-mcan2-pins-default";
		main_mcan2_gpio_pins_default = "/bus@100000/pinctrl@11c000/main-mcan2-gpio-pins-default";
		serdes_wiz0 = "/bus@100000/wiz@5000000";
		wiz0_pll0_refclk = "/bus@100000/wiz@5000000/pll0-refclk";
		wiz0_pll1_refclk = "/bus@100000/wiz@5000000/pll1-refclk";
		wiz0_refclk_dig = "/bus@100000/wiz@5000000/refclk-dig";
		wiz0_cmn_refclk_dig_div = "/bus@100000/wiz@5000000/cmn-refclk-dig-div";
		wiz0_cmn_refclk1_dig_div = "/bus@100000/wiz@5000000/cmn-refclk1-dig-div";
		serdes0 = "/bus@100000/wiz@5000000/serdes@5000000";
		serdes_wiz1 = "/bus@100000/wiz@5010000";
		wiz1_pll0_refclk = "/bus@100000/wiz@5010000/pll0-refclk";
		wiz1_pll1_refclk = "/bus@100000/wiz@5010000/pll1-refclk";
		wiz1_refclk_dig = "/bus@100000/wiz@5010000/refclk-dig";
		wiz1_cmn_refclk_dig_div = "/bus@100000/wiz@5010000/cmn-refclk-dig-div";
		wiz1_cmn_refclk1_dig_div = "/bus@100000/wiz@5010000/cmn-refclk1-dig-div";
		serdes1 = "/bus@100000/wiz@5010000/serdes@5010000";
		serdes_wiz2 = "/bus@100000/wiz@5020000";
		wiz2_pll0_refclk = "/bus@100000/wiz@5020000/pll0-refclk";
		wiz2_pll1_refclk = "/bus@100000/wiz@5020000/pll1-refclk";
		wiz2_refclk_dig = "/bus@100000/wiz@5020000/refclk-dig";
		wiz2_cmn_refclk_dig_div = "/bus@100000/wiz@5020000/cmn-refclk-dig-div";
		wiz2_cmn_refclk1_dig_div = "/bus@100000/wiz@5020000/cmn-refclk1-dig-div";
		serdes2 = "/bus@100000/wiz@5020000/serdes@5020000";
		serdes_wiz3 = "/bus@100000/wiz@5030000";
		wiz3_pll0_refclk = "/bus@100000/wiz@5030000/pll0-refclk";
		wiz3_pll1_refclk = "/bus@100000/wiz@5030000/pll1-refclk";
		wiz3_refclk_dig = "/bus@100000/wiz@5030000/refclk-dig";
		wiz3_cmn_refclk_dig_div = "/bus@100000/wiz@5030000/cmn-refclk-dig-div";
		wiz3_cmn_refclk1_dig_div = "/bus@100000/wiz@5030000/cmn-refclk1-dig-div";
		serdes3 = "/bus@100000/wiz@5030000/serdes@5030000";
		serdes3_usb_link = "/bus@100000/wiz@5030000/serdes@5030000/phy@0";
		pcie0_rc = "/bus@100000/pcie@2900000";
		pcie0_intc = "/bus@100000/pcie@2900000/interrupt-controller";
		pcie0_ep = "/bus@100000/pcie-ep@2900000";
		pcie1_rc = "/bus@100000/pcie@2910000";
		pcie1_intc = "/bus@100000/pcie@2910000/interrupt-controller";
		pcie1_ep = "/bus@100000/pcie-ep@2910000";
		pcie2_rc = "/bus@100000/pcie@2920000";
		pcie2_intc = "/bus@100000/pcie@2920000/interrupt-controller";
		pcie2_ep = "/bus@100000/pcie-ep@2920000";
		pcie3_rc = "/bus@100000/pcie@2930000";
		pcie3_intc = "/bus@100000/pcie@2930000/interrupt-controller";
		pcie3_ep = "/bus@100000/pcie-ep@2930000";
		serdes_wiz4 = "/bus@100000/wiz@5050000";
		wiz4_pll0_refclk = "/bus@100000/wiz@5050000/pll0-refclk";
		wiz4_pll1_refclk = "/bus@100000/wiz@5050000/pll1-refclk";
		wiz4_refclk_dig = "/bus@100000/wiz@5050000/refclk-dig";
		wiz4_cmn_refclk_dig_div = "/bus@100000/wiz@5050000/cmn-refclk-dig-div";
		wiz4_cmn_refclk1_dig_div = "/bus@100000/wiz@5050000/cmn-refclk1-dig-div";
		serdes4 = "/bus@100000/wiz@5050000/serdes@5050000";
		torrent_phy_dp = "/bus@100000/wiz@5050000/serdes@5050000/phy@0";
		main_uart0 = "/bus@100000/serial@2800000";
		main_uart1 = "/bus@100000/serial@2810000";
		main_uart2 = "/bus@100000/serial@2820000";
		main_uart3 = "/bus@100000/serial@2830000";
		main_uart4 = "/bus@100000/serial@2840000";
		main_uart5 = "/bus@100000/serial@2850000";
		main_uart6 = "/bus@100000/serial@2860000";
		main_uart7 = "/bus@100000/serial@2870000";
		main_uart8 = "/bus@100000/serial@2880000";
		main_uart9 = "/bus@100000/serial@2890000";
		main_gpio0 = "/bus@100000/gpio@600000";
		main_gpio1 = "/bus@100000/gpio@601000";
		main_gpio2 = "/bus@100000/gpio@610000";
		main_gpio3 = "/bus@100000/gpio@611000";
		main_gpio4 = "/bus@100000/gpio@620000";
		main_gpio5 = "/bus@100000/gpio@621000";
		main_gpio6 = "/bus@100000/gpio@630000";
		main_gpio7 = "/bus@100000/gpio@631000";
		main_sdhci0 = "/bus@100000/mmc@4f80000";
		main_sdhci1 = "/bus@100000/mmc@4fb0000";
		main_sdhci2 = "/bus@100000/mmc@4f98000";
		usbss0 = "/bus@100000/cdns-usb@4104000";
		usb0 = "/bus@100000/cdns-usb@4104000/usb@6000000";
		usbss1 = "/bus@100000/cdns-usb@4114000";
		usb1 = "/bus@100000/cdns-usb@4114000/usb@6400000";
		main_i2c0 = "/bus@100000/i2c@2000000";
		exp1 = "/bus@100000/i2c@2000000/gpio@20";
		exp2 = "/bus@100000/i2c@2000000/gpio@22";
		main_i2c1 = "/bus@100000/i2c@2010000";
		main_i2c2 = "/bus@100000/i2c@2020000";
		main_i2c3 = "/bus@100000/i2c@2030000";
		exp3 = "/bus@100000/i2c@2030000/gpio@20";
		pcm3168a_1 = "/bus@100000/i2c@2030000/audio-codec@44";
		main_i2c4 = "/bus@100000/i2c@2040000";
		main_i2c5 = "/bus@100000/i2c@2050000";
		main_i2c6 = "/bus@100000/i2c@2060000";
		d5520 = "/bus@100000/video-decoder@4300000";
		vxe384 = "/bus@100000/video-encoder@4200000";
		ufs_wrapper = "/bus@100000/ufs-wrapper@4e80000";
		mhdp = "/bus@100000/dp-bridge@a000000";
		dp0_ports = "/bus@100000/dp-bridge@a000000/ports";
		dp0_in = "/bus@100000/dp-bridge@a000000/ports/port@0/endpoint";
		dp0_out = "/bus@100000/dp-bridge@a000000/ports/port@4/endpoint";
		dss = "/bus@100000/dss@4a00000";
		dss_ports = "/bus@100000/dss@4a00000/ports";
		dpi0_out = "/bus@100000/dss@4a00000/ports/port@0/endpoint";
		mcasp0 = "/bus@100000/mcasp@2b00000";
		mcasp1 = "/bus@100000/mcasp@2b10000";
		mcasp2 = "/bus@100000/mcasp@2b20000";
		mcasp3 = "/bus@100000/mcasp@2b30000";
		mcasp4 = "/bus@100000/mcasp@2b40000";
		mcasp5 = "/bus@100000/mcasp@2b50000";
		mcasp6 = "/bus@100000/mcasp@2b60000";
		mcasp7 = "/bus@100000/mcasp@2b70000";
		mcasp8 = "/bus@100000/mcasp@2b80000";
		mcasp9 = "/bus@100000/mcasp@2b90000";
		mcasp10 = "/bus@100000/mcasp@2ba0000";
		mcasp11 = "/bus@100000/mcasp@2bb0000";
		watchdog0 = "/bus@100000/watchdog@2200000";
		watchdog1 = "/bus@100000/watchdog@2210000";
		main_r5fss0 = "/bus@100000/r5fss@5c00000";
		main_r5fss0_core0 = "/bus@100000/r5fss@5c00000/r5f@5c00000";
		main_r5fss0_core1 = "/bus@100000/r5fss@5c00000/r5f@5d00000";
		main_r5fss1 = "/bus@100000/r5fss@5e00000";
		main_r5fss1_core0 = "/bus@100000/r5fss@5e00000/r5f@5e00000";
		main_r5fss1_core1 = "/bus@100000/r5fss@5e00000/r5f@5f00000";
		c66_0 = "/bus@100000/dsp@4d80800000";
		c66_1 = "/bus@100000/dsp@4d81800000";
		c71_0 = "/bus@100000/dsp@64800000";
		icssg0 = "/bus@100000/icssg@b000000";
		icssg0_mem = "/bus@100000/icssg@b000000/memories@0";
		icssg0_cfg = "/bus@100000/icssg@b000000/cfg@26000";
		icssg0_coreclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/coreclk-mux@3c";
		icssg0_iepclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/iepclk-mux@30";
		icssg0_iep0 = "/bus@100000/icssg@b000000/iep@2e000";
		icssg0_iep1 = "/bus@100000/icssg@b000000/iep@2f000";
		icssg0_mii_rt = "/bus@100000/icssg@b000000/mii-rt@32000";
		icssg0_mii_g_rt = "/bus@100000/icssg@b000000/mii-g-rt@33000";
		icssg0_intc = "/bus@100000/icssg@b000000/interrupt-controller@20000";
		pru0_0 = "/bus@100000/icssg@b000000/pru@34000";
		rtu0_0 = "/bus@100000/icssg@b000000/rtu@4000";
		tx_pru0_0 = "/bus@100000/icssg@b000000/txpru@a000";
		pru0_1 = "/bus@100000/icssg@b000000/pru@38000";
		rtu0_1 = "/bus@100000/icssg@b000000/rtu@6000";
		tx_pru0_1 = "/bus@100000/icssg@b000000/txpru@c000";
		icssg0_mdio = "/bus@100000/icssg@b000000/mdio@32400";
		icssg1 = "/bus@100000/icssg@b100000";
		icssg1_mem = "/bus@100000/icssg@b100000/memories@b100000";
		icssg1_cfg = "/bus@100000/icssg@b100000/cfg@26000";
		icssg1_coreclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/coreclk-mux@3c";
		icssg1_iepclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/iepclk-mux@30";
		icssg1_iep0 = "/bus@100000/icssg@b100000/iep@2e000";
		icssg1_iep1 = "/bus@100000/icssg@b100000/iep@2f000";
		icssg1_mii_rt = "/bus@100000/icssg@b100000/mii-rt@32000";
		icssg1_mii_g_rt = "/bus@100000/icssg@b100000/mii-g-rt@33000";
		icssg1_intc = "/bus@100000/icssg@b100000/interrupt-controller@20000";
		pru1_0 = "/bus@100000/icssg@b100000/pru@34000";
		rtu1_0 = "/bus@100000/icssg@b100000/rtu@4000";
		tx_pru1_0 = "/bus@100000/icssg@b100000/txpru@a000";
		pru1_1 = "/bus@100000/icssg@b100000/pru@38000";
		rtu1_1 = "/bus@100000/icssg@b100000/rtu@6000";
		tx_pru1_1 = "/bus@100000/icssg@b100000/txpru@c000";
		icssg1_mdio = "/bus@100000/icssg@b100000/mdio@32400";
		timesync_router = "/bus@100000/timesync_router@A40000";
		gpu = "/bus@100000/gpu@4e20000000";
		main_mcan0 = "/bus@100000/can@2701000";
		main_mcan1 = "/bus@100000/can@2711000";
		main_mcan2 = "/bus@100000/can@2721000";
		main_mcan3 = "/bus@100000/can@2731000";
		main_mcan4 = "/bus@100000/can@2741000";
		main_mcan5 = "/bus@100000/can@2751000";
		main_mcan6 = "/bus@100000/can@2761000";
		main_mcan7 = "/bus@100000/can@2771000";
		main_mcan8 = "/bus@100000/can@2781000";
		main_mcan9 = "/bus@100000/can@2791000";
		main_mcan10 = "/bus@100000/can@27a1000";
		main_mcan11 = "/bus@100000/can@27b1000";
		main_mcan12 = "/bus@100000/can@27c1000";
		main_mcan13 = "/bus@100000/can@27d1000";
		ti_csi2rx0 = "/bus@100000/ticsi2rx@4500000";
		cdns_csi2rx0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000";
		csi0_port0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@0";
		csi0_port1 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@1";
		csi0_port2 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@2";
		csi0_port3 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@3";
		csi0_port4 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@4";
		ti_csi2rx1 = "/bus@100000/ticsi2rx@4510000";
		cdns_csi2rx1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000";
		csi1_port0 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@0";
		csi1_port1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@1";
		csi1_port2 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@2";
		csi1_port3 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@3";
		csi1_port4 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@4";
		dphy0 = "/bus@100000/phy@4580000";
		dphy1 = "/bus@100000/phy@4590000";
		cmn_refclk = "/clock-cmnrefclk";
		cmn_refclk1 = "/clock-cmnrefclk1";
		reserved_memory = "/reserved-memory";
		secure_ddr = "/reserved-memory/optee@9e800000";
		mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";
		mcu_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";
		mcu_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a1000000";
		mcu_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a1100000";
		main_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a2000000";
		main_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a2100000";
		main_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a3000000";
		main_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a3100000";
		main_r5fss1_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a4000000";
		main_r5fss1_core0_memory_region = "/reserved-memory/r5f-memory@a4100000";
		main_r5fss1_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a5000000";
		main_r5fss1_core1_memory_region = "/reserved-memory/r5f-memory@a5100000";
		c66_1_dma_memory_region = "/reserved-memory/c66-dma-memory@a6000000";
		c66_0_memory_region = "/reserved-memory/c66-memory@a6100000";
		c66_0_dma_memory_region = "/reserved-memory/c66-dma-memory@a7000000";
		c66_1_memory_region = "/reserved-memory/c66-memory@a7100000";
		c71_0_dma_memory_region = "/reserved-memory/c71-dma-memory@a8000000";
		c71_0_memory_region = "/reserved-memory/c71-memory@a8100000";
		rtos_ipc_memory_region = "/reserved-memory/ipc-memories@aa000000";
		main_r5fss0_core0_shared_memory_queue_region = "/reserved-memory/r5f-virtual-eth-queues@ac000000";
		main_r5fss0_core0_shared_memory_bufpool_region = "/reserved-memory/r5f-virtual-eth-buffers@ac200000";
		gpio_keys = "/gpio-keys";
		sw10 = "/gpio-keys/sw10";
		sw11 = "/gpio-keys/sw11";
		evm_12v0 = "/fixedregulator-evm12v0";
		vsys_3v3 = "/fixedregulator-vsys3v3";
		vsys_5v0 = "/fixedregulator-vsys5v0";
		vdd_mmc1 = "/fixedregulator-sd";
		vdd_sd_dv_alt = "/gpio-regulator-TLV71033";
		sound0 = "/sound@0";
		dp_pwr_3v3 = "/fixedregulator-dp-prw";
		dp0 = "/connector";
		dp_connector_in = "/connector/port/endpoint";
	};
};

In my original k3-j721e.dtsi, CPSW9G register is missing under cbass_main node. Now I have added it in.

Thank you!!

Best Regards,

Shawn

Hi,

shawn lin said:

In my original k3-j721e.dtsi, CPSW9G register is missing under cbass_main node. Now I have added it in.

What is the result after addition of above, can you please share boot log with above.

Best Regards,
Sudheer

Hello Sudheer,

After I added CPSW9G register in k3-j721e.dtsi, then copied the k3-j721e-common-proc-board.dtb to SD card. There is still no RGMII5 when I keyed in "ifconfig -a". The boot log as shown below:

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:34:29 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.5(release):08.01.00.006-dirty
NOTICE:  BL31: Built : 21:03:57, Mar 23 2022

U-Boot SPL 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Trying to boot from MMC2


U-Boot 2021.01-g44a87e3ab8 (Mar 23 2022 - 21:04:54 +0000)

SoC:   J721E SR1.1
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Net:   Could not get PHY for ethernet@46000000port@1: addr 0
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
pca953x gpio@22: Error reading output register
SD/MMC found on device 1
Failed to load 'boot.scr'
42 bytes read in 10 ms (3.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19278336 bytes read in 818 ms (22.5 MiB/s)
100486 bytes read in 19 ms (5 MiB/s)
3585 bytes read in 17 ms (205.1 KiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 000000008fee4000, end 000000008fffffff ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 5.10.100 (root@aep-COMPAL-SERVER) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Sun Dec 3 00:06:29 CST 2023
[    0.000000] Machine model: Texas Instruments K3 J721E SoC
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c66-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c66-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac000000, size 2 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-queues@ac000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ac200000, size 30 MiB
[    0.000000] OF: reserved mem: initialized node r5f-virtual-eth-buffers@ac200000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x00000008ffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000a8ffffff]
[    0.000000]   node   0: [mem 0x00000000a9000000-0x00000000a9ffffff]
[    0.000000]   node   0: [mem 0x00000000aa000000-0x00000000abbfffff]
[    0.000000]   node   0: [mem 0x00000000abc00000-0x00000000abffffff]
[    0.000000]   node   0: [mem 0x00000000ac000000-0x00000000adffffff]
[    0.000000]   node   0: [mem 0x00000000ae000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x00000008ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[    0.000000] cma: Reserved 512 MiB at 0x00000000e0000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 2 pages/cpu s49880 r8192 d73000 u131072
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: EL2 vector hardening
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 65472
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs) root=PARTUUID=5a8abaf6-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 6, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 5, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x00000000dc000000-0x00000000e0000000] (64MB)
[    0.000000] Memory: 3339136K/4194304K available (10880K kernel code, 1290K rwdata, 4352K rodata, 1856K init, 748K bss, 330880K reserved, 524288K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: 16 PPIs implemented
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: allocated 1048576 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x00000008800b0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008800c0000
[    0.000000] random: get_random_bytes called from start_kernel+0x31c/0x4c4 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008353] Console: colour dummy device 80x25
[    0.012912] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023582] pid_max: default: 32768 minimum: 301
[    0.028331] LSM: Security Framework initializing
[    0.033075] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.040641] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[    0.049579] rcu: Hierarchical SRCU implementation.
[    0.054635] Platform MSI: msi-controller@1820000 domain created
[    0.060865] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.070157] EFI services will not be available.
[    0.074903] smp: Bringing up secondary CPUs ...
[    0.080143] Detected PIPT I-cache on CPU1
[    0.080166] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.080176] GICv3: CPU1: using allocated LPI pending table @0x00000008800d0000
[    0.080209] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.080265] smp: Brought up 1 node, 2 CPUs
[    0.109610] SMP: Total of 2 processors activated.
[    0.114415] CPU features: detected: 32-bit EL0 Support
[    0.119669] CPU features: detected: CRC32 instructions
[    0.133399] CPU: All CPU(s) started at EL2
[    0.137595] alternatives: patching kernel code
[    0.142585] devtmpfs: initialized
[    0.150956] KASLR disabled due to lack of seed
[    0.155609] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.165573] futex hash table entries: 512 (order: -1, 32768 bytes, linear)
[    0.173209] pinctrl core: initialized pinctrl subsystem
[    0.178783] DMI not present or invalid.
[    0.182999] NET: Registered protocol family 16
[    0.190398] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.197702] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.205704] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.214009] thermal_sys: Registered thermal governor 'step_wise'
[    0.214011] thermal_sys: Registered thermal governor 'power_allocator'
[    0.220427] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.234066] ASID allocator initialised with 65536 entries
[    0.255437] HugeTLB registered 16.0 GiB page size, pre-allocated 0 pages
[    0.262293] HugeTLB registered 512 MiB page size, pre-allocated 0 pages
[    0.269050] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.276813] cryptd: max_cpu_qlen set to 1000
[    0.282836] k3-chipinfo 43000014.chipid: Family:J721E rev:SR2.0 JTAGID[0x1bb6402f] Detected
[    0.291659] vsys_3v3: supplied by evm_12v0
[    0.296023] vsys_5v0: supplied by evm_12v0
[    0.300337] vdd_mmc1: supplied by vsys_3v3
[    0.305041] iommu: Default domain type: Translated
[    0.310164] SCSI subsystem initialized
[    0.314271] mc: Linux media interface: v0.10
[    0.318647] videodev: Linux video capture interface: v2.00
[    0.324276] pps_core: LinuxPPS API ver. 1 registered
[    0.329346] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.338682] PTP clock support registered
[    0.342702] EDAC MC: Ver: 3.0.0
[    0.346425] FPGA manager framework
[    0.349936] Advanced Linux Sound Architecture Driver Initialized.
[    0.356518] clocksource: Switched to clocksource arch_sys_counter
[    0.362938] VFS: Disk quotas dquot_6.6.0
[    0.366980] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
[    0.376689] NET: Registered protocol family 2
[    0.381274] IP idents hash table entries: 65536 (order: 3, 524288 bytes, linear)
[    0.389894] tcp_listen_portaddr_hash hash table entries: 4096 (order: 0, 65536 bytes, linear)
[    0.398664] TCP established hash table entries: 32768 (order: 2, 262144 bytes, linear)
[    0.406860] TCP bind hash table entries: 32768 (order: 3, 524288 bytes, linear)
[    0.414655] TCP: Hash tables configured (established 32768 bind 32768)
[    0.421401] UDP hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.428293] UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes, linear)
[    0.435678] NET: Registered protocol family 1
[    0.440366] RPC: Registered named UNIX socket transport module.
[    0.446427] RPC: Registered udp transport module.
[    0.451232] RPC: Registered tcp transport module.
[    0.456034] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.462618] PCI: CLS 0 bytes, default 64
[    0.466950] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    0.477304] Initialise system trusted keyrings
[    0.481918] workingset: timestamp_bits=46 max_order=16 bucket_order=0
[    0.490223] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.496466] NFS: Registering the id_resolver key type
[    0.501650] Key type id_resolver registered
[    0.505920] Key type id_legacy registered
[    0.510037] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.516886] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.524529] 9p: Installing v9fs 9p2000 file system support
[    0.550072] Key type asymmetric registered
[    0.554259] Asymmetric key parser 'x509' registered
[    0.559256] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[    0.566815] io scheduler mq-deadline registered
[    0.571440] io scheduler kyber registered
[    0.576698] pinctrl-single 4301c000.pinctrl: 94 pins, size 376
[    0.582859] pinctrl-single 11c000.pinctrl: 173 pins, size 692
[    0.591266] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.597547] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.605341] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.613392] arm-smmu-v3 36600000.iommu: ias 48-bit, oas 48-bit (features 0x00001faf)
[    0.622355] arm-smmu-v3 36600000.iommu: allocated 524288 entries for cmdq
[    0.631172] arm-smmu-v3 36600000.iommu: allocated 524288 entries for evtq
[    0.638878] arm-smmu-v3 36600000.iommu: msi_domain absent - falling back to wired irqs
[    0.651720] brd: module loaded
[    0.657592] loop: module loaded
[    0.661399] megasas: 07.714.04.00-rc1
[    0.666833] tun: Universal TUN/TAP device driver, 1.6
[    0.672267] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.678676] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.684748] sky2: driver version 1.30
[    0.689006] VFIO - User Level meta-driver version: 0.3
[    0.694658] i2c /dev entries driver
[    0.698819] sdhci: Secure Digital Host Controller Interface driver
[    0.705142] sdhci: Copyright(c) Pierre Ossman
[    0.709768] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.716083] ledtrig-cpu: registered to indicate activity on CPUs
[    0.722382] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.729495] optee: probing for conduit method.
[    0.734053] optee: revision 3.12 (3d47a131)
[    0.734286] optee: initialized driver
[    0.743729] NET: Registered protocol family 17
[    0.748338] 9pnet: Installing 9P2000 support
[    0.752726] Key type dns_resolver registered
[    0.757170] Loading compiled-in X.509 certificates
[    0.766109] k3-ringacc 2b800000.ringacc: Failed to get MSI domain
[    0.772439] k3-ringacc 3c000000.ringacc: Failed to get MSI domain
[    0.780643] ti-sci 44083000.dmsc: ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
[    0.810183] random: fast init done
[    0.842255] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    0.848613] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    0.856610] omap_i2c 40b00000.i2c: bus 0 rev0.12 at 100 kHz
[    0.862681] omap_i2c 40b10000.i2c: bus 1 rev0.12 at 100 kHz
[    0.868754] omap_i2c 42120000.i2c: bus 2 rev0.12 at 100 kHz
[    0.874991] pca953x 3-0020: supply vcc not found, using dummy regulator
[    0.881807] pca953x 3-0020: using no AI
[    0.908562] pca953x 3-0020: failed writing register
[    0.913600] pca953x: probe of 3-0020 failed with error -121
[    0.919497] pca953x 3-0022: supply vcc not found, using dummy regulator
[    0.926294] pca953x 3-0022: using AI
[    0.929991] pca953x 3-0022: failed writing register
[    0.935013] pca953x: probe of 3-0022 failed with error -121
[    0.940751] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz
[    0.946786] omap_i2c 2010000.i2c: bus 4 rev0.12 at 400 kHz
[    0.952778] omap_i2c 2020000.i2c: bus 5 rev0.12 at 100 kHz
[    0.958895] pca953x 6-0020: supply vcc not found, using dummy regulator
[    0.965706] pca953x 6-0020: using no AI
[    0.992563] pca953x 6-0020: failed writing register
[    0.997591] pca953x: probe of 6-0020 failed with error -121
[    1.004564] omap_i2c 2030000.i2c: bus 6 rev0.12 at 400 kHz
[    1.010648] omap_i2c 2040000.i2c: bus 7 rev0.12 at 100 kHz
[    1.016690] omap_i2c 2050000.i2c: bus 8 rev0.12 at 100 kHz
[    1.022684] omap_i2c 2060000.i2c: bus 9 rev0.12 at 100 kHz
[    1.029094] ti-sci-intr bus@100000:bus@28380000:interrupt-controller2: Interrupt Router 137 domain created
[    1.039065] ti-sci-intr bus@100000:interrupt-controller0: Interrupt Router 131 domain created
[    1.047873] ti-sci-intr bus@100000:main-navss:interrupt-controller1: Interrupt Router 213 domain created
[    1.057714] ti-sci-inta 33d00000.interrupt-controller: Interrupt Aggregator domain 209 created
[    1.077423] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[    1.087304] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    1.094062] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.102984] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
[    1.113142] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    1.119900] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66346100, num_proxies:64
[    1.127854] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 15, base_baud = 6000000) is a 8250
[    1.137245] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 28, base_baud = 3000000) is a 8250
[    1.145988] printk: console [ttyS2] enabled
[    1.145988] printk: console [ttyS2] enabled
[    1.154425] printk: bootconsole [ns16550a0] disabled
[    1.154425] printk: bootconsole [ns16550a0] disabled
[    1.164874] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 29, base_baud = 3000000) is a 8250
[    1.173801] 2840000.serial: ttyS6 at MMIO 0x2840000 (irq = 30, base_baud = 3000000) is a 8250
[    1.184194] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    1.194705] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vcc-supply regulator, assuming enabled
[    1.204860] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq-supply regulator, assuming enabled
[    1.215099] cdns-ufshcd 4e84000.ufs: ufshcd_populate_vreg: Unable to find vccq2-supply regulator, assuming enabled
[    1.225978] scsi host0: ufshcd
[    1.272538] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.280609] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.287331] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.301156] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010a, freq:200000000, add_val:4 pps:0
[    1.309963] mmc0: CQHCI version 5.10
[    1.310244] mmc1: CQHCI version 5.10
[    1.317138] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.323310] j721e-audio sound@0: devm_snd_soc_register_card() failed: -517
[    1.335911] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc7100
[    1.342746] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc7100
[    1.349570] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fc7100
[    1.356380] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fc7100
[    1.360527] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    1.370379] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fc7100
[    1.380809] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    1.391274] ti-udma 31150000.dma-controller: Channels: 122 (tchan: 61, rchan: 61, gp-rflow: 16)
[    1.405538] spi-nor spi2.0: mt35xu512aba (65536 Kbytes)
[    1.410773] 8 cmdlinepart partitions found on MTD device 47040000.spi.0
[    1.417374] Creating 8 MTD partitions on "47040000.spi.0":
[    1.422847] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    1.428832] 0x000000080000-0x000000280000 : "ospi.tispl"
[    1.434535] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    1.440349] 0x000000680000-0x0000006c0000 : "ospi.env"
[    1.445840] 0x0000006c0000-0x0000007c0000 : "ospi.sysfw"
[    1.451553] 0x0000007c0000-0x000000800000 : "ospi.env.backup"
[    1.453954] mmc0: Command Queue Engine enabled
[    1.461747] mmc0: new HS200 MMC card at address 0001
[    1.467023] mmcblk0: mmc0:0001 S0J56X 14.8 GiB
[    1.467058] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    1.471658] mmcblk0boot0: mmc0:0001 S0J56X partition 1 31.5 MiB
[    1.477376] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
[    1.482965] mmcblk0boot1: mmc0:0001 S0J56X partition 2 31.5 MiB
[    1.494560] mmcblk0rpmb: mmc0:0001 S0J56X partition 3 4.00 MiB, chardev (237:0)
[    1.503856] spi-nor spi3.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
[    1.510746] spi-nor: probe of spi3.0 failed with error -2
[    1.556529] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.564599] mdio_bus 46000f00.mdio: MDIO device at address 0 is missing.
[    1.571326] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA00101, cpsw version 0x6BA80100 Ports: 2 quirks:00000000
[    1.584933] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    1.591953] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.599163] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.605493] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010a, freq:500000000, add_val:1 pps:0
[    1.615602] davinci-mcasp 2b00000.mcasp: IRQ common not found
[    1.630383] debugfs: Directory 'pd:27' with parent 'pm_genpd' already present!
[    1.637701] debugfs: Directory 'pd:26' with parent 'pm_genpd' already present!
[    1.644912] cdns-ufshcd 4e84000.ufs: link startup failed 1
[    1.644915] cdns-ufshcd 4e84000.ufs: UFS Host state=0
[    1.651334] debugfs: Directory 'pd:242' with parent 'pm_genpd' already present!
[    1.655438] cdns-ufshcd 4e84000.ufs: outstanding reqs=0x0 tasks=0x0
[    1.662727] debugfs: Directory 'pd:241' with parent 'pm_genpd' already present!
[    1.662750] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present!
[    1.668996] cdns-ufshcd 4e84000.ufs: saved_err=0x0, saved_uic_err=0x0
[    1.676279] debugfs: Directory 'pd:239' with parent 'pm_genpd' already present!
[    1.683566] cdns-ufshcd 4e84000.ufs: Device power mode=1, UIC link state=0
[    1.690944] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    1.697345] cdns-ufshcd 4e84000.ufs: PM in progress=0, sys. suspended=0
[    1.717453] cdns-ufshcd 4e84000.ufs: Auto BKOPS=0, Host self-block=0
[    1.718559] ALSA device list:
[    1.723790] cdns-ufshcd 4e84000.ufs: Clk gate=1
[    1.723793] cdns-ufshcd 4e84000.ufs: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0
[    1.723796] cdns-ufshcd 4e84000.ufs: last intr at 1537094 us, last intr status=0x404
[    1.726758]   #0: j721e-cpb
[    1.731266] cdns-ufshcd 4e84000.ufs: error handling flags=0x0, req. abort count=0
[    1.757386] cdns-ufshcd 4e84000.ufs: hba->ufs_version=0x210, Host capabilities=0x1587031f, caps=0x0
[    1.757390] cdns-ufshcd 4e84000.ufs: quirks=0x0, dev. quirks=0x0
[    1.772408] cdns-ufshcd 4e84000.ufs: clk: core_clk, rate: 250000000
[    1.778661] cdns-ufshcd 4e84000.ufs: clk: phy_clk, rate: 19200000
[    1.784743] cdns-ufshcd 4e84000.ufs: clk: ref_clk, rate: 19200000
[    1.790821] cdns-ufshcd 4e84000.ufs: ufshcd_print_pwr_info:[RX, TX]: gear=[0, 0], lane[0, 0], pwr[INVALID MODE, INVALID MODE], rate = 0
[    1.802982] host_regs: 00000000: 1587031f 00000000 00000210 00000000
[    1.809319] host_regs: 00000010: 00000000 00000000 00000000 00000000
[    1.815658] host_regs: 00000020: 00000000 00000470 00000000 00000000
[    1.821999] host_regs: 00000030: 00000008 00000001 00000000 00000000
[    1.828337] host_regs: 00000040: 00000000 00000000 00000000 00000000
[    1.834676] host_regs: 00000050: 00000000 00000000 00000000 00000000
[    1.841013] host_regs: 00000060: 00000000 00000000 00000000 00000000
[    1.847350] host_regs: 00000070: 00000000 00000000 00000000 00000000
[    1.853687] host_regs: 00000080: 00000000 00000000 00000000 00000000
[    1.860024] host_regs: 00000090: 00000000 00000000 00000000 00000000
[    1.866361] cdns-ufshcd 4e84000.ufs: No record of pa_err
[    1.871661] cdns-ufshcd 4e84000.ufs: No record of dl_err
[    1.876958] cdns-ufshcd 4e84000.ufs: No record of nl_err
[    1.882256] cdns-ufshcd 4e84000.ufs: No record of tl_err
[    1.887554] cdns-ufshcd 4e84000.ufs: No record of dme_err
[    1.892939] cdns-ufshcd 4e84000.ufs: No record of auto_hibern8_err
[    1.899103] cdns-ufshcd 4e84000.ufs: No record of fatal_err
[    1.904661] cdns-ufshcd 4e84000.ufs: link_startup_fail[0] = 0x1 at 1544397 us
[    1.911778] cdns-ufshcd 4e84000.ufs: No record of resume_fail
[    1.917508] cdns-ufshcd 4e84000.ufs: No record of suspend_fail
[    1.923326] cdns-ufshcd 4e84000.ufs: No record of dev_reset
[    1.928896] cdns-ufshcd 4e84000.ufs: No record of host_reset
[    1.934545] cdns-ufshcd 4e84000.ufs: No record of task_abort
[    2.377303] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    2.385750] Waiting for root device PARTUUID=5a8abaf6-02...
[    2.417896] mmc1: Problem switching card into high-speed mode!
[    2.423824] mmc1: new SDHC card at address 0001
[    2.428679] mmcblk1: mmc1:0001 ASTC 7.37 GiB
[    2.439624]  mmcblk1: p1 p2
[    2.510756] EXT4-fs (mmcblk1p2): recovery complete
[    2.519413] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[    2.527520] VFS: Mounted root (ext4 filesystem) on device 179:98.
[    2.548006] devtmpfs: mounted
[    2.551260] Freeing unused kernel memory: 1856K
[    2.555813] Run /sbin/init as init process
[    3.244820] systemd[1]: System time before build time, advancing clock.
[    3.323712] systemd[1]: systemd 244.5+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[    3.345515] systemd[1]: Detected architecture arm64.

Welcome to Arago 2021.09!

[    3.406196] systemd[1]: Set hostname to <j7-evm>.
[    3.903813] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    3.912720] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[    3.961746] systemd[1]: /lib/systemd/system/docker.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/docker.sock → /run/docker.sock; please update the unit file accordingly.
[    4.109910] random: systemd: uninitialized urandom read (16 bytes read)
[    4.116634] systemd[1]: system-getty.slice: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
[    4.128961] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
[    4.138844] systemd[1]: Created slice system-getty.slice.
[  OK  ] Created slice system-getty.slice.
[    4.160594] random: systemd: uninitialized urandom read (16 bytes read)
[    4.167841] systemd[1]: Created slice system-serial\x2dgetty.slice.
[  OK  ] Created slice system-serial\x2dgetty.slice.
[    4.188588] random: systemd: uninitialized urandom read (16 bytes read)
[    4.195724] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    4.216696] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password …ts to Console Directory Watch.
[    4.240631] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password R…uests to Wall Directory Watch.
[    4.264627] systemd[1]: Reached target Paths.
[  OK  ] Reached target Paths.
[    4.280575] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    4.300566] systemd[1]: Reached target Slices.
[  OK  ] Reached target Slices.
[    4.316572] systemd[1]: Reached target Swap.
[  OK  ] Reached target Swap.
[    4.343544] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    4.364591] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    4.388237] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[    4.408692] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    4.448242] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
[    4.456569] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    4.476792] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    4.492835] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    4.516743] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    4.536684] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    4.558853] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    4.578761] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    4.602737] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    4.624877] systemd[1]: Mounting Temporary Directory (/tmp)...
         Mounting Temporary Directory (/tmp)...
[    4.640769] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped.
[    4.654512] systemd[1]: Starting Start psplash boot splash screen...
         Starting Start psplash boot splash screen...
[    4.681871] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    4.696740] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[    4.709764] systemd[1]: Starting Journal Service...
         Starting Journal Service...
[    4.802594] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    4.818871] systemd[1]: Starting Remount Root and Kernel File Systems...
         Starting Remount Root and Kernel File Systems...
[    4.842676] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
[    4.850570] systemd[1]: Starting udev Coldplug all Devices...
         Starting udev Coldplug all Devices...
[    4.870888] systemd[1]: Started Journal Service.
[  OK  ] Started Journal Service.
[  OK  ] Started RPC Bind.
[  OK  ] Mounted Huge Pages File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[  OK  ] Started Remount Root and Kernel File Systems.
         Mounting Kernel Configuration File System...
         Starting Flush Journal to Persistent Storage...
[    5.103892] systemd-journald[175]: Received client request to flush runtime journal.
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Flush Journal to Persistent Storage.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create Static Device Nodes in /dev.
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram...
         Mounting /var/volatile...
         Starting udev Kernel Device Manager...
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Mounted /media/ram.
[  OK  ] Mounted /var/volatile.
         Starting udev Wait for Complete Device Initialization...
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Create Volatile Files and Directories.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target System Time Synchronized.
         Starting Update UTMP about System Boot/Shutdown...
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[  OK  ] Stopped Network Time Synchronization.
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
         Starting Start psplash boot splash screen...
         Starting Load Kernel Modules...
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[FAILED] Failed to start Start psplash boot splash screen.
See 'systemctl status psplash-start.service' for details.
[DEPEND] Dependency failed for Star…progress communication helper.
[FAILED] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[    7.776539] random: crng init done
[    7.779956] random: 7 urandom warning(s) missed due to ratelimiting
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Created slice system-systemd\x2dfsck.slice.
[  OK  ] Found device /dev/mmcblk1p1.
[  OK  ] Started udev Wait for Complete Device Initialization.
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target Timers.
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Docker Socket for the API.
[  OK  ] Listening on dropbear.socket.
         Starting Reboot and dump vmcore via kexec...
         Starting File System Check on /dev/mmcblk1p1...
[  OK  ] Listening on Docker Socket for the API.
[  OK  ] Started Reboot and dump vmcore via kexec.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
         Starting Save/Restore Sound Card State...
[  OK  ] Started Job spooling tools.
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started D-Bus System Message Bus.
         Starting Print notice about GPLv3 packages...
         Starting set host name as per compatible name...
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
[  OK  ] Started irqbalance daemon.
         Starting Telephony service...
         Starting rc.pvr.service...
         Starting startwlanap...
         Starting startwlansta...
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started TEE Supplicant.
         Starting Update weston ini… based on the platform name...
[  OK  ] Started Save/Restore Sound Card State.
[  OK  ] Reached target Sound Card.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Stopped Login Service.
[FAILED] Failed to start Login Service.
See 'systemctl status systemd-logind.service' for details.
[  OK  ] Started File System Check on /dev/mmcblk1p1.
[  OK  ] Started set host name as per compatible name.
[  OK  ] Started IPv6 Packet Filtering Framework.
[  OK  ] Started IPv4 Packet Filtering Framework.
[  OK  ] Started rc.pvr.service.
[  OK  ] Started startwlanap.
[  OK  ] Started startwlansta.
[  OK  ] Started Update weston ini …ge based on the platform name.
[  OK  ] Started Telephony service.
[  OK  ] Reached target Network (Pre).
         Mounting /run/media/mmcblk1p1...
         Starting Network Service...
         Starting weston.service...
[  OK  ] Started weston.service.
         Starting DEMO...
         Starting telnetd.service...
[  OK  ] Started DEMO.
[  OK  ] Started telnetd.service.
[  OK  ] Started Network Service.
         Starting Wait for Network to be Configured...
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Reached target Network.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Avahi mDNS/DNS-SD Stack...
         Starting Enable and configure wl18xx bluetooth stack...
[  OK  ] Started [    9.889391] am65-cpsw-nuss 46000000.ethernet: phy /bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0 not found on slave 1
NFS status monitor for NFSv2/3 locking..
         Starting Simple Network Ma…ent Protocol (SNMP) Daemon....
         Starting Permit User Sessions...
[  OK  ] Mounted /run/media/mmcblk1p1.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Enable and configure wl18xx bluetooth stack.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Stopped Network Name Resolution.
[FAILED] Failed to start Network Name Resolution.
See 'systemctl status systemd-resolved.service' for details.
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Serial Getty on ttyS3.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[  OK  ] Started Avahi mDNS/DNS-SD Stack.
[  OK  ] Started Simple Network Man…ement Protocol (SNMP) Daemon..
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
        autoconf
        bash-dev
        bash
        bc
        binutils
        cifs-utils
        coreutils-stdbuf
        coreutils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbserver
        gettext
        glmark2
        gstreamer1.0-libav-dev
        gstreamer1.0-libav
        gzip
        less
        libasm1
        libbfd
        libdw1
        libelf1
        libgdbm-compat4
        libgdbm-dev
        libgdbm6
        libgettextlib
        libgettextsrc
        libgmp-dev
        libgmp10
        libgmpxx4
        libidn2-0
        libidn2-dev
        libmpc3
        libmpfr6
        libreadline-dev
        libreadline8
        libunistring-dev
        libunistring2
        m4-dev
        m4
        make
        nettle-dev
        nettle
        parted
        python3-rfc3987
        python3-strict-rfc3339
        tar
        which
        zeromq

If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project http://arago-project.org j7-evm ttyS2

Arago 2021.09 j7-evm ttyS2

j7-evm login: root
root@j7-evm:~#
root@j7-evm:~#
root@j7-evm:~# ifconfig -a
eth0: flags=4098<BROADCAST,MULTICAST>  mtu 1500  metric 1
        ether 24:76:25:a1:a5:53  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536  metric 1
        inet 127.0.0.1  netmask 255.0.0.0
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 2  bytes 140 (140.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 2  bytes 140 (140.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

root@j7-evm:~#

And I convert the dtb (k3-j721e-common-proc-board.dtb) to dts again by the command:

# dtc -I dtb -O dts k3-j721e-common-proc-board.dtb > j721e-common-proc-board.dts

/dts-v1/;

/ {
	model = "Texas Instruments K3 J721E SoC";
	compatible = "ti,j721e";
	interrupt-parent = <0x1>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;

	aliases {
		serial0 = "/bus@100000/bus@28380000/serial@42300000";
		serial1 = "/bus@100000/bus@28380000/serial@40a00000";
		serial2 = "/bus@100000/serial@2800000";
		serial3 = "/bus@100000/serial@2810000";
		serial4 = "/bus@100000/serial@2820000";
		serial5 = "/bus@100000/serial@2830000";
		serial6 = "/bus@100000/serial@2840000";
		serial7 = "/bus@100000/serial@2850000";
		serial8 = "/bus@100000/serial@2860000";
		serial9 = "/bus@100000/serial@2870000";
		serial10 = "/bus@100000/serial@2880000";
		serial11 = "/bus@100000/serial@2890000";
		ethernet0 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
	};

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {

			cluster0 {
				phandle = <0x89>;

				core0 {
					cpu = <0x2>;
				};

				core1 {
					cpu = <0x3>;
				};
			};
		};

		cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x4>;
			phandle = <0x2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <0x40>;
			i-cache-sets = <0x100>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			d-cache-sets = <0x100>;
			next-level-cache = <0x4>;
			phandle = <0x3>;
		};
	};

	l2-cache0 {
		compatible = "cache";
		cache-level = <0x2>;
		cache-size = <0x100000>;
		cache-line-size = <0x40>;
		cache-sets = <0x400>;
		next-level-cache = <0x5>;
		phandle = <0x4>;
	};

	l3-cache0 {
		compatible = "cache";
		cache-level = <0x3>;
		phandle = <0x5>;
	};

	firmware {

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
			phandle = <0x8a>;
		};
	};

	timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
		phandle = <0x8b>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <0x1 0x7 0x4>;
		phandle = <0x8c>;
	};

	bus@100000 {
		compatible = "simple-bus";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges = <0x0 0x100000 0x0 0x100000 0x0 0x20000 0x0 0x600000 0x0 0x600000 0x0 0x31100 0x0 0x900000 0x0 0x900000 0x0 0x12000 0x0 0xa40000 0x0 0xa40000 0x0 0x800 0x0 0x6000000 0x0 0x6000000 0x0 0x400000 0x0 0x6400000 0x0 0x6400000 0x0 0x400000 0x0 0x1000000 0x0 0x1000000 0x0 0xaf02400 0x0 0xc000000 0x0 0xc000000 0x0 0xd000000 0x0 0x30000000 0x0 0x30000000 0x0 0xc400000 0x0 0xd000000 0x0 0xd000000 0x0 0x1800000 0x0 0xe000000 0x0 0xe000000 0x0 0x1800000 0x0 0x10000000 0x0 0x10000000 0x0 0x10000000 0x0 0x64800000 0x0 0x64800000 0x0 0x800000 0x44 0x0 0x44 0x0 0x0 0x8000000 0x44 0x10000000 0x44 0x10000000 0x0 0x8000000 0x4d 0x80800000 0x4d 0x80800000 0x0 0x800000 0x4d 0x81800000 0x4d 0x81800000 0x0 0x800000 0x4e 0x20000000 0x4e 0x20000000 0x0 0x80000 0x0 0x70000000 0x0 0x70000000 0x0 0x800000 0x0 0x28380000 0x0 0x28380000 0x0 0x3880000 0x0 0x40200000 0x0 0x40200000 0x0 0x998400 0x0 0x40f00000 0x0 0x40f00000 0x0 0x20000 0x0 0x41000000 0x0 0x41000000 0x0 0x20000 0x0 0x41400000 0x0 0x41400000 0x0 0x20000 0x0 0x41c00000 0x0 0x41c00000 0x0 0x100000 0x0 0x42040000 0x0 0x42040000 0x0 0x3ac2400 0x0 0x45100000 0x0 0x45100000 0x0 0xc24000 0x0 0x46000000 0x0 0x46000000 0x0 0x200000 0x0 0x47000000 0x0 0x47000000 0x0 0x68400 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000 0x5 0x0 0x5 0x0 0x1 0x0 0x7 0x0 0x7 0x0 0x1 0x0>;
		phandle = <0x8d>;

		bus@28380000 {
			compatible = "simple-bus";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges = <0x0 0x28380000 0x0 0x28380000 0x0 0x3880000 0x0 0x40200000 0x0 0x40200000 0x0 0x998400 0x0 0x40f00000 0x0 0x40f00000 0x0 0x20000 0x0 0x41000000 0x0 0x41000000 0x0 0x20000 0x0 0x41400000 0x0 0x41400000 0x0 0x20000 0x0 0x41c00000 0x0 0x41c00000 0x0 0x100000 0x0 0x42040000 0x0 0x42040000 0x0 0x3ac2400 0x0 0x45100000 0x0 0x45100000 0x0 0xc24000 0x0 0x46000000 0x0 0x46000000 0x0 0x200000 0x0 0x47000000 0x0 0x47000000 0x0 0x68400 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000 0x5 0x0 0x5 0x0 0x1 0x0 0x7 0x0 0x7 0x0 0x1 0x0>;
			phandle = <0x8e>;

			dmsc@44083000 {
				compatible = "ti,k2g-sci";
				ti,host-id = <0xc>;
				mbox-names = "rx", "tx";
				mboxes = <0x6 0xb 0x6 0xd>;
				reg-names = "debug_messages";
				reg = <0x0 0x44083000 0x0 0x1000>;
				phandle = <0xa>;

				power-controller {
					compatible = "ti,sci-pm-domain";
					#power-domain-cells = <0x2>;
					phandle = <0x8>;
				};

				clocks {
					compatible = "ti,k2g-sci-clk";
					#clock-cells = <0x2>;
					pinctrl-names = "default";
					pinctrl-0 = <0x7>;
					phandle = <0x9>;
				};

				reset-controller {
					compatible = "ti,sci-reset";
					#reset-cells = <0x2>;
					phandle = <0x17>;
				};
			};

			syscon@40f00000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x0 0x40f00000 0x0 0x20000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x0 0x40f00000 0x20000>;
				phandle = <0x14>;

				phy@4040 {
					compatible = "ti,am654-phy-gmii-sel";
					reg = <0x4040 0x4>;
					#phy-cells = <0x1>;
					phandle = <0x15>;
				};
			};

			chipid@43000014 {
				compatible = "ti,am654-chipid";
				reg = <0x0 0x43000014 0x0 0x4>;
			};

			pinctrl@4301c000 {
				compatible = "pinctrl-single";
				reg = <0x0 0x4301c000 0x0 0x178>;
				#pinctrl-cells = <0x1>;
				pinctrl-single,register-width = <0x20>;
				pinctrl-single,function-mask = <0xffffffff>;
				phandle = <0x8f>;

				wkup-i2c0-pins-default {
					pinctrl-single,pins = <0xf8 0x60000 0xfc 0x60000>;
					phandle = <0x90>;
				};

				mcu-fss0-ospi0-pins-default {
					pinctrl-single,pins = <0x0 0x10000 0x8 0x50000 0xc 0x50000 0x10 0x50000 0x14 0x50000 0x18 0x50000 0x1c 0x50000 0x20 0x50000 0x24 0x50000 0x28 0x50000 0x2c 0x10000>;
					phandle = <0xc>;
				};

				sw11-button-pins-default {
					pinctrl-single,pins = <0xcc 0x50007>;
					phandle = <0x80>;
				};

				mcu-fss0-ospi1-pins-default {
					pinctrl-single,pins = <0x34 0x10000 0x50 0x10000 0x40 0x50000 0x44 0x50000 0x48 0x50000 0x4c 0x50000 0x3c 0x50000 0x38 0x50000>;
					phandle = <0xd>;
				};

				mcu-cpsw-pins-default {
					pinctrl-single,pins = <0x58 0x10000 0x5c 0x50000 0x60 0x10000 0x64 0x10000 0x68 0x10000 0x6c 0x10000 0x78 0x50000 0x7c 0x50000 0x80 0x50000 0x84 0x50000 0x70 0x10000 0x74 0x50000>;
					phandle = <0x12>;
				};

				mcu-mdio1-pins-default {
					pinctrl-single,pins = <0x8c 0x10000 0x88 0x50000>;
					phandle = <0x13>;
				};

				mcu-mcan0-pins-default {
					pinctrl-single,pins = <0xac 0x50000 0xa8 0x10000>;
					phandle = <0x91>;
				};

				mcu-mcan0-gpio-pins-default {
					pinctrl-single,pins = <0xb0 0x50007 0x98 0x50007>;
					phandle = <0x92>;
				};

				mcu-mcan1-pins-default {
					pinctrl-single,pins = <0xc4 0x50000 0xc0 0x10000>;
					phandle = <0x93>;
				};

				mcu-mcan1-gpio-pins-default {
					pinctrl-single,pins = <0xb8 0x50007>;
					phandle = <0x94>;
				};
			};

			sram@41c00000 {
				compatible = "mmio-sram";
				reg = <0x0 0x41c00000 0x0 0x100000>;
				ranges = <0x0 0x0 0x41c00000 0x100000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				phandle = <0x95>;
			};

			serial@42300000 {
				compatible = "ti,j721e-uart", "ti,am654-uart";
				reg = <0x0 0x42300000 0x0 0x100>;
				reg-shift = <0x2>;
				reg-io-width = <0x4>;
				interrupts = <0x0 0x381 0x4>;
				clock-frequency = <0x2dc6c00>;
				current-speed = <0x1c200>;
				power-domains = <0x8 0x11f 0x1>;
				clocks = <0x9 0x11f 0x0>;
				clock-names = "fclk";
				status = "disabled";
				phandle = <0x96>;
			};

			serial@40a00000 {
				compatible = "ti,j721e-uart", "ti,am654-uart";
				reg = <0x0 0x40a00000 0x0 0x100>;
				reg-shift = <0x2>;
				reg-io-width = <0x4>;
				interrupts = <0x0 0x34e 0x4>;
				clock-frequency = <0x5b8d800>;
				current-speed = <0x1c200>;
				power-domains = <0x8 0x95 0x1>;
				clocks = <0x9 0x95 0x0>;
				clock-names = "fclk";
				phandle = <0x97>;
			};

			interrupt-controller2 {
				compatible = "ti,sci-intr";
				ti,intr-trigger-type = <0x1>;
				interrupt-controller;
				interrupt-parent = <0x1>;
				#interrupt-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0x89>;
				ti,interrupt-ranges = <0x10 0x3c0 0x10>;
				phandle = <0xb>;
			};

			gpio@42110000 {
				compatible = "ti,j721e-gpio", "ti,keystone-gpio";
				reg = <0x0 0x42110000 0x0 0x100>;
				gpio-controller;
				#gpio-cells = <0x2>;
				interrupt-parent = <0xb>;
				interrupts = <0x67 0x68 0x69 0x6a 0x6b 0x6c>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x0>;
				power-domains = <0x8 0x71 0x1>;
				clocks = <0x9 0x71 0x0>;
				clock-names = "gpio";
				phandle = <0x82>;
			};

			gpio@42100000 {
				compatible = "ti,j721e-gpio", "ti,keystone-gpio";
				reg = <0x0 0x42100000 0x0 0x100>;
				gpio-controller;
				#gpio-cells = <0x2>;
				interrupt-parent = <0xb>;
				interrupts = <0x70 0x71 0x72 0x73 0x74 0x75>;
				interrupt-controller;
				#interrupt-cells = <0x2>;
				ti,ngpio = <0x54>;
				ti,davinci-gpio-unbanked = <0x0>;
				power-domains = <0x8 0x72 0x1>;
				clocks = <0x9 0x72 0x0>;
				clock-names = "gpio";
				status = "disabled";
				phandle = <0x98>;
			};

			i2c@40b00000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x40b00000 0x0 0x100>;
				interrupts = <0x0 0x354 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc2 0x0>;
				power-domains = <0x8 0xc2 0x1>;
				phandle = <0x99>;
			};

			i2c@40b10000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x40b10000 0x0 0x100>;
				interrupts = <0x0 0x355 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc3 0x0>;
				power-domains = <0x8 0xc3 0x1>;
				phandle = <0x9a>;
			};

			i2c@42120000 {
				compatible = "ti,j721e-i2c", "ti,omap4-i2c";
				reg = <0x0 0x42120000 0x0 0x100>;
				interrupts = <0x0 0x380 0x4>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clock-names = "fck";
				clocks = <0x9 0xc5 0x0>;
				power-domains = <0x8 0xc5 0x0>;
				phandle = <0x9b>;
			};

			fss@47000000 {
				compatible = "simple-bus";
				reg = <0x0 0x47000000 0x0 0x100>;
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				ranges;
				phandle = <0x9c>;

				spi@47040000 {
					compatible = "ti,am654-ospi";
					reg = <0x0 0x47040000 0x0 0x100 0x5 0x0 0x1 0x0>;
					interrupts = <0x0 0x348 0x4>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x4>;
					cdns,trigger-address = <0x0>;
					clocks = <0x9 0x67 0x0>;
					assigned-clocks = <0x9 0x67 0x0>;
					assigned-clock-parents = <0x9 0x67 0x2>;
					assigned-clock-rates = <0x9ef21aa>;
					power-domains = <0x8 0x67 0x1>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0xc>;
					phandle = <0x9d>;

					flash@0 {
						compatible = "jedec,spi-nor";
						reg = <0x0>;
						spi-tx-bus-width = <0x8>;
						spi-rx-bus-width = <0x8>;
						spi-max-frequency = <0x17d7840>;
						cdns,tshsl-ns = <0x3c>;
						cdns,tsd2d-ns = <0x3c>;
						cdns,tchsh-ns = <0x3c>;
						cdns,tslch-ns = <0x3c>;
						cdns,read-delay = <0x0>;
						#address-cells = <0x1>;
						#size-cells = <0x1>;
					};
				};

				spi@47050000 {
					compatible = "ti,am654-ospi";
					reg = <0x0 0x47050000 0x0 0x100 0x7 0x0 0x1 0x0>;
					interrupts = <0x0 0x349 0x4>;
					cdns,fifo-depth = <0x100>;
					cdns,fifo-width = <0x4>;
					cdns,trigger-address = <0x0>;
					clocks = <0x9 0x68 0x0>;
					power-domains = <0x8 0x68 0x1>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					pinctrl-names = "default";
					pinctrl-0 = <0xd>;
					phandle = <0x9e>;

					flash@0 {
						compatible = "jedec,spi-nor";
						reg = <0x0>;
						spi-tx-bus-width = <0x1>;
						spi-rx-bus-width = <0x4>;
						spi-max-frequency = <0x2625a00>;
						cdns,tshsl-ns = <0x3c>;
						cdns,tsd2d-ns = <0x3c>;
						cdns,tchsh-ns = <0x3c>;
						cdns,tslch-ns = <0x3c>;
						cdns,read-delay = <0x2>;
						#address-cells = <0x1>;
						#size-cells = <0x1>;
					};
				};
			};

			tscadc@40200000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x0 0x40200000 0x0 0x1000>;
				interrupts = <0x0 0x35c 0x4>;
				power-domains = <0x8 0x0 0x1>;
				clocks = <0x9 0x0 0x1>;
				assigned-clocks = <0x9 0x0 0x3>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "adc_tsc_fck";
				dmas = <0xe 0x7400 0xe 0x7401>;
				dma-names = "fifo0", "fifo1";
				phandle = <0x9f>;

				adc {
					#io-channel-cells = <0x1>;
					compatible = "ti,am3359-adc";
				};
			};

			tscadc@40210000 {
				compatible = "ti,am3359-tscadc";
				reg = <0x0 0x40210000 0x0 0x1000>;
				interrupts = <0x0 0x35d 0x4>;
				power-domains = <0x8 0x1 0x1>;
				clocks = <0x9 0x1 0x1>;
				assigned-clocks = <0x9 0x1 0x3>;
				assigned-clock-rates = <0x3938700>;
				clock-names = "adc_tsc_fck";
				dmas = <0xe 0x7402 0xe 0x7403>;
				dma-names = "fifo0", "fifo1";
				phandle = <0xa0>;

				adc {
					#io-channel-cells = <0x1>;
					compatible = "ti,am3359-adc";
				};
			};

			mcu-navss {
				compatible = "simple-mfd";
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				ranges;
				dma-coherent;
				dma-ranges;
				ti,sci-dev-id = <0xe8>;

				ringacc@2b800000 {
					compatible = "ti,am654-navss-ringacc";
					reg = <0x0 0x2b800000 0x0 0x400000 0x0 0x2b000000 0x0 0x400000 0x0 0x28590000 0x0 0x100 0x0 0x2a500000 0x0 0x40000>;
					reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
					ti,num-rings = <0x11e>;
					ti,sci-rm-range-gp-rings = <0x1>;
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xeb>;
					msi-parent = <0xf>;
					phandle = <0x10>;
				};

				dma-controller@285c0000 {
					compatible = "ti,j721e-navss-mcu-udmap";
					reg = <0x0 0x285c0000 0x0 0x100 0x0 0x2a800000 0x0 0x40000 0x0 0x2aa00000 0x0 0x40000>;
					reg-names = "gcfg", "rchanrt", "tchanrt";
					msi-parent = <0xf>;
					#dma-cells = <0x1>;
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xec>;
					ti,ringacc = <0x10>;
					ti,sci-rm-range-tchan = <0xd 0xf>;
					ti,sci-rm-range-rchan = <0xa 0xb>;
					ti,sci-rm-range-rflow = <0x0>;
					phandle = <0x11>;
				};
			};

			ethernet@46000000 {
				compatible = "ti,j721e-cpsw-nuss";
				#address-cells = <0x2>;
				#size-cells = <0x2>;
				reg = <0x0 0x46000000 0x0 0x200000>;
				reg-names = "cpsw_nuss";
				ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
				dma-coherent;
				clocks = <0x9 0x12 0x16>;
				clock-names = "fck";
				power-domains = <0x8 0x12 0x1>;
				dmas = <0x11 0xf000 0x11 0xf001 0x11 0xf002 0x11 0xf003 0x11 0xf004 0x11 0xf005 0x11 0xf006 0x11 0xf007 0x11 0x7000>;
				dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <0x12 0x13>;
				phandle = <0xa1>;

				ethernet-ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@1 {
						reg = <0x1>;
						ti,mac-only;
						label = "port1";
						ti,syscon-efuse = <0x14 0x200>;
						phys = <0x15 0x1>;
						phy-mode = "rgmii-rxid";
						phy-handle = <0x16>;
						phandle = <0xa2>;
					};
				};

				mdio@f00 {
					compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
					reg = <0x0 0xf00 0x0 0x100>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0x9 0x12 0x16>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					phandle = <0xa3>;

					ethernet-phy@0 {
						reg = <0x0>;
						ti,rx-internal-delay = <0x7>;
						ti,fifo-depth = <0x1>;
						phandle = <0x16>;
					};
				};

				cpts@3d000 {
					compatible = "ti,am65-cpts";
					reg = <0x0 0x3d000 0x0 0x400>;
					clocks = <0x9 0x12 0x2>;
					clock-names = "cpts";
					interrupts-extended = <0x1 0x0 0x35a 0x4>;
					interrupt-names = "cpts";
					ti,cpts-ext-ts-inputs = <0x4>;
					ti,cpts-periodic-outputs = <0x2>;
				};
			};

			r5fss@41000000 {
				compatible = "ti,j721e-r5fss";
				ti,cluster-mode = <0x1>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x41000000 0x0 0x41000000 0x20000 0x41400000 0x0 0x41400000 0x20000>;
				power-domains = <0x8 0xf9 0x1>;
				phandle = <0xa4>;

				r5f@41000000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41000000 0x8000 0x41010000 0x8000>;
					reg-names = "atcm", "btcm";
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xfa>;
					ti,sci-proc-ids = <0x1 0xff>;
					resets = <0x17 0xfa 0x1>;
					firmware-name = "j7-mcu-r5f0_0-fw";
					ti,atcm-enable = <0x1>;
					ti,btcm-enable = <0x1>;
					ti,loczrama = <0x1>;
					mboxes = <0x18 0x19>;
					memory-region = <0x1a 0x1b>;
					phandle = <0xa5>;
				};

				r5f@41400000 {
					compatible = "ti,j721e-r5f";
					reg = <0x41400000 0x8000 0x41410000 0x8000>;
					reg-names = "atcm", "btcm";
					ti,sci = <0xa>;
					ti,sci-dev-id = <0xfb>;
					ti,sci-proc-ids = <0x2 0xff>;
					resets = <0x17 0xfb 0x1>;
					firmware-name = "j7-mcu-r5f0_1-fw";
					ti,atcm-enable = <0x1>;
					ti,btcm-enable = <0x1>;
					ti,loczrama = <0x1>;
					mboxes = <0x18 0x1c>;
					memory-region = <0x1d 0x1e>;
					phandle = <0xa6>;
				};
			};

			can@40528000 {
				compatible = "bosch,m_can";
				reg = <0x0 0x40528000 0x0 0x200 0x0 0x40500000 0x0 0x8000>;
				reg-names = "m_can", "message_ram";
				power-domains = <0x8 0xac 0x1>;
				clocks = <0x9 0xac 0x0 0x9 0xac 0x1>;
				clock-names = "hclk", "cclk";
				interrupts = <0x0 0x340 0x4 0x0 0x341 0x4>;
				interrupt-names = "int0", "int1";
				bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xa7>;
			};

			can@40568000 {
				compatible = "bosch,m_can";
				reg = <0x0 0x40568000 0x0 0x200 0x0 0x40540000 0x0 0x8000>;
				reg-names = "m_can", "message_ram";
				power-domains = <0x8 0xad 0x1>;
				clocks = <0x9 0xad 0x0 0x9 0xad 0x1>;
				clock-names = "hclk", "cclk";
				interrupts = <0x0 0x343 0x4 0x0 0x344 0x4>;
				interrupt-names = "int0", "int1";
				bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
				status = "disabled";
				phandle = <0xa8>;
			};
		};

		spi@2100000 {
			compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
			reg = <0x0 0x2100000 0x0 0x400>;
			interrupts = <0x0 0xb8 0x4>;
			clocks = <0x9 0x10a 0x1>;
			power-domains = <0x8 0x10a 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x1f>;
			status = "okay";
			phandle = <0xa9>;

			spidev@0 {
				spi-max-frequency = <0x16e3600>;
				reg = <0x0>;
				compatible = "linux,spidev";
			};
		};

		spi@2110000 {
			compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
			reg = <0x0 0x2110000 0x0 0x400>;
			interrupts = <0x0 0xb9 0x4>;
			clocks = <0x9 0x10b 0x1>;
			power-domains = <0x8 0x10b 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x20>;
			status = "okay";
			phandle = <0xaa>;

			spidev@0 {
				spi-max-frequency = <0x16e3600>;
				reg = <0x0>;
				compatible = "linux,spidev";
			};
		};

		sram@70000000 {
			compatible = "mmio-sram";
			reg = <0x0 0x70000000 0x0 0x800000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0x70000000 0x800000>;
			phandle = <0xab>;

			atf-sram@0 {
				reg = <0x0 0x20000>;
			};
		};

		scm-conf@100000 {
			compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
			reg = <0x0 0x100000 0x0 0x1c000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0x100000 0x1c000>;
			phandle = <0x3f>;

			mux@4080 {
				compatible = "mmio-mux";
				reg = <0x4080 0x50>;
				#mux-control-cells = <0x1>;
				mux-reg-masks = <0x4080 0x3 0x4084 0x3 0x4090 0x3 0x4094 0x3 0x40a0 0x3 0x40a4 0x3 0x40b0 0x3 0x40b4 0x3 0x40c0 0x3 0x40c4 0x3 0x40c8 0x3 0x40cc 0x3>;
				idle-states = <0x1 0x0 0x1 0x1 0x1 0x1 0x2 0x2 0x0 0x0 0x0 0x0>;
				phandle = <0xac>;
			};

			phy@4044 {
				compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
				ti,qsgmii-main-ports = <0x2 0x1>;
				reg = <0x4044 0x20>;
				#phy-cells = <0x1>;
				phandle = <0xad>;
			};

			mux-controller@4000 {
				compatible = "mmio-mux";
				#mux-control-cells = <0x1>;
				mux-reg-masks = <0x4000 0x8000000 0x4010 0x8000000>;
				idle-states = <0x1 0x0>;
				phandle = <0xae>;
			};

			clock@4140 {
				compatible = "ti,am654-ehrpwm-tbclk", "syscon";
				reg = <0x4140 0x18>;
				#clock-cells = <0x1>;
				phandle = <0x21>;
			};
		};

		pwm@3000000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3000000 0x0 0x100>;
			power-domains = <0x8 0x53 0x1>;
			clocks = <0x21 0x0 0x9 0x53 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xaf>;
		};

		pwm@3010000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3010000 0x0 0x100>;
			power-domains = <0x8 0x54 0x1>;
			clocks = <0x21 0x1 0x9 0x54 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb0>;
		};

		pwm@3020000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3020000 0x0 0x100>;
			power-domains = <0x8 0x55 0x1>;
			clocks = <0x21 0x2 0x9 0x55 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb1>;
		};

		pwm@3030000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3030000 0x0 0x100>;
			power-domains = <0x8 0x56 0x1>;
			clocks = <0x21 0x3 0x9 0x56 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb2>;
		};

		pwm@3040000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3040000 0x0 0x100>;
			power-domains = <0x8 0x57 0x1>;
			clocks = <0x21 0x4 0x9 0x57 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb3>;
		};

		pwm@3050000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <0x3>;
			reg = <0x0 0x3050000 0x0 0x100>;
			power-domains = <0x8 0x58 0x1>;
			clocks = <0x21 0x5 0x9 0x58 0x0>;
			clock-names = "tbclk", "fck";
			status = "disabled";
			phandle = <0xb4>;
		};

		interrupt-controller@1800000 {
			compatible = "arm,gic-v3";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			#interrupt-cells = <0x3>;
			interrupt-controller;
			reg = <0x0 0x1800000 0x0 0x10000 0x0 0x1900000 0x0 0x100000>;
			interrupts = <0x1 0x9 0x4>;
			phandle = <0x1>;

			msi-controller@1820000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x1820000 0x0 0x10000>;
				socionext,synquacer-pre-its = <0x1000000 0x400000>;
				msi-controller;
				#msi-cells = <0x1>;
				phandle = <0x40>;
			};
		};

		interrupt-controller0 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <0x1>;
			interrupt-controller;
			interrupt-parent = <0x1>;
			#interrupt-cells = <0x1>;
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x83>;
			ti,interrupt-ranges = <0x8 0x188 0x38>;
			phandle = <0x49>;
		};

		main-navss {
			compatible = "simple-mfd";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			dma-coherent;
			dma-ranges;
			ti,sci-dev-id = <0xc7>;

			interrupt-controller1 {
				compatible = "ti,sci-intr";
				ti,intr-trigger-type = <0x4>;
				interrupt-controller;
				interrupt-parent = <0x1>;
				#interrupt-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd5>;
				ti,interrupt-ranges = <0x0 0x40 0x40 0x40 0x1c0 0x40 0x80 0x2a0 0x40>;
				phandle = <0x22>;
			};

			interrupt-controller@33d00000 {
				compatible = "ti,sci-inta";
				reg = <0x0 0x33d00000 0x0 0x100000>;
				interrupt-controller;
				interrupt-parent = <0x22>;
				msi-controller;
				#interrupt-cells = <0x0>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd1>;
				ti,interrupt-ranges = <0x0 0x0 0x100>;
				phandle = <0xf>;
			};

			mailbox@32c00000 {
				compatible = "ti,am654-secure-proxy";
				#mbox-cells = <0x1>;
				reg-names = "target_data", "rt", "scfg";
				reg = <0x0 0x32c00000 0x0 0x100000 0x0 0x32400000 0x0 0x100000 0x0 0x32800000 0x0 0x100000>;
				interrupt-names = "rx_011";
				interrupts = <0x0 0x25 0x4>;
				phandle = <0x6>;
			};

			iommu@36600000 {
				compatible = "arm,smmu-v3";
				reg = <0x0 0x36600000 0x0 0x100000>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x304 0x1 0x0 0x300 0x1>;
				interrupt-names = "eventq", "gerror";
				#iommu-cells = <0x1>;
				phandle = <0xb5>;
			};

			spinlock@30e00000 {
				compatible = "ti,am654-hwspinlock";
				reg = <0x0 0x30e00000 0x0 0x1000>;
				#hwlock-cells = <0x1>;
				phandle = <0xb6>;
			};

			mailbox@31f80000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f80000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1b4>;
				phandle = <0x18>;

				mbox-mcu-r5fss0-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x19>;
				};

				mbox-mcu-r5fss0-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x1c>;
				};
			};

			mailbox@31f81000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f81000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1b0>;
				phandle = <0x5c>;

				mbox-main-r5fss0-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x5d>;
				};

				mbox-main-r5fss0-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x62>;
				};
			};

			mailbox@31f82000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f82000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1ac>;
				phandle = <0x65>;

				mbox-main-r5fss1-core0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x66>;
				};

				mbox-main-r5fss1-core1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x69>;
				};
			};

			mailbox@31f83000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f83000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1a8>;
				phandle = <0x6c>;

				mbox-c66-0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x6d>;
				};

				mbox-c66-1 {
					ti,mbox-rx = <0x2 0x0 0x0>;
					ti,mbox-tx = <0x3 0x0 0x0>;
					phandle = <0x70>;
				};
			};

			mailbox@31f84000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f84000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				interrupts = <0x1a4>;
				phandle = <0x73>;

				mbox-c71-0 {
					ti,mbox-rx = <0x0 0x0 0x0>;
					ti,mbox-tx = <0x1 0x0 0x0>;
					phandle = <0x74>;
				};
			};

			mailbox@31f85000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f85000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb7>;
			};

			mailbox@31f86000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f86000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb8>;
			};

			mailbox@31f87000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f87000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xb9>;
			};

			mailbox@31f88000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f88000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xba>;
			};

			mailbox@31f89000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f89000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbb>;
			};

			mailbox@31f8a000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f8a000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbc>;
			};

			mailbox@31f8b000 {
				compatible = "ti,am654-mailbox";
				reg = <0x0 0x31f8b000 0x0 0x200>;
				#mbox-cells = <0x1>;
				ti,mbox-num-users = <0x4>;
				ti,mbox-num-fifos = <0x10>;
				interrupt-parent = <0x22>;
				status = "disabled";
				phandle = <0xbd>;
			};

			ringacc@3c000000 {
				compatible = "ti,am654-navss-ringacc";
				reg = <0x0 0x3c000000 0x0 0x400000 0x0 0x38000000 0x0 0x400000 0x0 0x31120000 0x0 0x100 0x0 0x33000000 0x0 0x40000>;
				reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
				ti,num-rings = <0x400>;
				ti,sci-rm-range-gp-rings = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd3>;
				msi-parent = <0xf>;
				phandle = <0x23>;
			};

			dma-controller@31150000 {
				compatible = "ti,j721e-navss-main-udmap";
				reg = <0x0 0x31150000 0x0 0x100 0x0 0x34000000 0x0 0x100000 0x0 0x35000000 0x0 0x100000>;
				reg-names = "gcfg", "rchanrt", "tchanrt";
				msi-parent = <0xf>;
				#dma-cells = <0x1>;
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xd4>;
				ti,ringacc = <0x23>;
				ti,sci-rm-range-tchan = <0xd 0xf 0x10>;
				ti,sci-rm-range-rchan = <0xa 0xb 0xc>;
				ti,sci-rm-range-rflow = <0x0>;
				phandle = <0xe>;
			};

			cpts@310d0000 {
				compatible = "ti,j721e-cpts";
				reg = <0x0 0x310d0000 0x0 0x400>;
				reg-names = "cpts";
				clocks = <0x9 0xc9 0x1>;
				clock-names = "cpts";
				interrupts-extended = <0x22 0x187>;
				interrupt-names = "cpts";
				ti,cpts-periodic-outputs = <0x6>;
				ti,cpts-ext-ts-inputs = <0x8>;
			};
		};

		ethernet@c000000 {
			compatible = "ti,j721e-cpswxg-nuss";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			reg = <0x0 0xc000000 0x0 0x200000>;
			reg-names = "cpsw_nuss";
			ranges = <0x0 0x0 0x0 0xc000000 0x0 0x200000>;
			clocks = <0x9 0x13 0x59>;
			clock-names = "fck";
			power-domains = <0x8 0x13 0x1>;
			dmas = <0xe 0xca00 0xe 0xca01 0xe 0xca02 0xe 0xca03 0xe 0xca04 0xe 0xca05 0xe 0xca06 0xe 0xca07 0xe 0x4a00>;
			dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx";
			phandle = <0xbe>;

			ethernet-ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@1 {
					reg = <0x1>;
					ti,mac-only;
					label = "port1";
					phandle = <0xbf>;
				};

				port@2 {
					reg = <0x2>;
					ti,mac-only;
					label = "port2";
					phandle = <0xc0>;
				};

				port@3 {
					reg = <0x3>;
					ti,mac-only;
					label = "port3";
					phandle = <0xc1>;
				};

				port@4 {
					reg = <0x4>;
					ti,mac-only;
					label = "port4";
					phandle = <0xc2>;
				};

				port@5 {
					reg = <0x5>;
					ti,mac-only;
					label = "port5";
					phandle = <0xc3>;
				};

				port@6 {
					reg = <0x6>;
					ti,mac-only;
					label = "port6";
					phandle = <0xc4>;
				};

				port@7 {
					reg = <0x7>;
					ti,mac-only;
					label = "port7";
					phandle = <0xc5>;
				};

				port@8 {
					reg = <0x8>;
					ti,mac-only;
					label = "port8";
					phandle = <0xc6>;
				};
			};

			mdio@f00 {
				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
				reg = <0x0 0xf00 0x0 0x100>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				clocks = <0x9 0x13 0x59>;
				clock-names = "fck";
				bus_freq = <0xf4240>;
				phandle = <0xc7>;
			};

			cpts@3d000 {
				compatible = "ti,j721e-cpts";
				reg = <0x0 0x3d000 0x0 0x400>;
				clocks = <0x9 0x13 0x10>;
				clock-names = "cpts";
				interrupts-extended = <0x1 0x0 0x10 0x4>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <0x4>;
				ti,cpts-periodic-outputs = <0x2>;
			};
		};

		crypto@4e00000 {
			compatible = "ti,j721e-sa2ul";
			reg = <0x0 0x4e00000 0x0 0x1200>;
			power-domains = <0x8 0x108 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges = <0x0 0x4e00000 0x0 0x4e00000 0x0 0x30000>;
			dmas = <0xe 0xc000 0xe 0x4000 0xe 0x4001>;
			dma-names = "tx", "rx1", "rx2";
			dma-coherent;
			phandle = <0xc8>;

			rng@4e10000 {
				compatible = "inside-secure,safexcel-eip76";
				reg = <0x0 0x4e10000 0x0 0x7d>;
				interrupts = <0x0 0xb 0x4>;
				clocks = <0x9 0x108 0x1>;
				phandle = <0xc9>;
			};
		};

		pinctrl@11c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0x11c000 0x0 0x2b4>;
			#pinctrl-cells = <0x1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0xffffffff>;
			phandle = <0xca>;

			spi0_pins_default {
				pinctrl-single,pins = <0x1c8 0x50000 0x1c0 0x50000 0x1c4 0x50000 0x1cc 0x50000 0x1d0 0x50000>;
				phandle = <0x1f>;
			};

			spi1_pins_default {
				pinctrl-single,pins = <0x1dc 0x50000 0x1d4 0x50000 0x1e0 0x50000 0x1e4 0x50000>;
				phandle = <0x20>;
			};

			sw10-button-pins-default {
				pinctrl-single,pins = <0x0 0x50007>;
				phandle = <0x7f>;
			};

			main-mmc1-pins-default {
				pinctrl-single,pins = <0x254 0x50000 0x250 0x50000 0x2ac 0x50000 0x24c 0x50000 0x248 0x50000 0x244 0x50000 0x240 0x50000 0x258 0x50000 0x25c 0x50000>;
				phandle = <0x4c>;
			};

			vdd-sd-dv-alt-pins-default {
				pinctrl-single,pins = <0x210 0x50007>;
				phandle = <0x84>;
			};

			main-usbss0-pins-default {
				pinctrl-single,pins = <0x290 0x10000 0x210 0x50007>;
				phandle = <0x4d>;
			};

			main-usbss1-pins-default {
				pinctrl-single,pins = <0x214 0x10004>;
				phandle = <0x4f>;
			};

			dp0-pins-default {
				pinctrl-single,pins = <0x1c4 0x50005>;
				phandle = <0x57>;
			};

			main-i2c0-pins-default {
				pinctrl-single,pins = <0x220 0x60000 0x224 0x60000>;
				phandle = <0x50>;
			};

			main-i2c1-pins-default {
				pinctrl-single,pins = <0x228 0x60000 0x22c 0x60000>;
				phandle = <0x51>;
			};

			main-i2c3-pins-default {
				pinctrl-single,pins = <0x270 0x60004 0x274 0x60004>;
				phandle = <0x52>;
			};

			mcasp0-pins-default {
				pinctrl-single,pins = <0xd4 0xc 0xd8 0xc 0xb0 0xc 0xb4 0x4000c>;
				phandle = <0x5b>;
			};

			audi-ext-refclk2-pins-default {
				pinctrl-single,pins = <0x1a4 0x10003>;
				phandle = <0x7>;
			};

			main-mcan0-pins-default {
				pinctrl-single,pins = <0x208 0x50000 0x20c 0x10000>;
				phandle = <0xcb>;
			};

			main-mcan2-pins-default {
				pinctrl-single,pins = <0x1f0 0x50003 0x1f4 0x10003>;
				phandle = <0xcc>;
			};

			main-mcan2-gpio-pins-default {
				pinctrl-single,pins = <0x200 0x50007>;
				phandle = <0xcd>;
			};
		};

		wiz@5000000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x124 0x1>;
			clocks = <0x9 0x124 0x5 0x9 0x124 0xb 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x124 0xb 0x9 0x124 0x0>;
			assigned-clock-parents = <0x9 0x124 0xf 0x9 0x124 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5000000 0x0 0x5000000 0x10000>;
			phandle = <0x29>;

			pll0-refclk {
				clocks = <0x9 0x124 0xb 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x25>;
				assigned-clock-parents = <0x9 0x124 0xb>;
				phandle = <0x25>;
			};

			pll1-refclk {
				clocks = <0x9 0x124 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x27>;
				assigned-clock-parents = <0x26>;
				phandle = <0x27>;
			};

			refclk-dig {
				clocks = <0x9 0x124 0xb 0x9 0x124 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x28>;
				assigned-clock-parents = <0x26>;
				phandle = <0x28>;
			};

			cmn-refclk-dig-div {
				clocks = <0x28>;
				#clock-cells = <0x0>;
				phandle = <0x2a>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x27>;
				#clock-cells = <0x0>;
				phandle = <0x2b>;
			};

			serdes@5000000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5000000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x29 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x2a 0x2b 0x25 0x27>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xce>;
			};
		};

		wiz@5010000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x125 0x1>;
			clocks = <0x9 0x125 0x5 0x9 0x125 0xd 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x125 0xd 0x9 0x125 0x0>;
			assigned-clock-parents = <0x9 0x125 0x11 0x9 0x125 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5010000 0x0 0x5010000 0x10000>;
			phandle = <0x2f>;

			pll0-refclk {
				clocks = <0x9 0x125 0xd 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2c>;
				assigned-clock-parents = <0x9 0x125 0xd>;
				phandle = <0x2c>;
			};

			pll1-refclk {
				clocks = <0x9 0x125 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2d>;
				assigned-clock-parents = <0x26>;
				phandle = <0x2d>;
			};

			refclk-dig {
				clocks = <0x9 0x125 0xd 0x9 0x125 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x2e>;
				assigned-clock-parents = <0x26>;
				phandle = <0x2e>;
			};

			cmn-refclk-dig-div {
				clocks = <0x2e>;
				#clock-cells = <0x0>;
				phandle = <0x30>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x2d>;
				#clock-cells = <0x0>;
				phandle = <0x31>;
			};

			serdes@5010000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5010000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x2f 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x30 0x31 0x2c 0x2d>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xcf>;
			};
		};

		wiz@5020000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x126 0x1>;
			clocks = <0x9 0x126 0x5 0x9 0x126 0xb 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x126 0xb 0x9 0x126 0x0>;
			assigned-clock-parents = <0x9 0x126 0xf 0x9 0x126 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5020000 0x0 0x5020000 0x10000>;
			phandle = <0x35>;

			pll0-refclk {
				clocks = <0x9 0x126 0xb 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x32>;
				assigned-clock-parents = <0x9 0x126 0xb>;
				phandle = <0x32>;
			};

			pll1-refclk {
				clocks = <0x9 0x126 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x33>;
				assigned-clock-parents = <0x26>;
				phandle = <0x33>;
			};

			refclk-dig {
				clocks = <0x9 0x126 0xb 0x9 0x126 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x34>;
				assigned-clock-parents = <0x26>;
				phandle = <0x34>;
			};

			cmn-refclk-dig-div {
				clocks = <0x34>;
				#clock-cells = <0x0>;
				phandle = <0x36>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x33>;
				#clock-cells = <0x0>;
				phandle = <0x37>;
			};

			serdes@5020000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5020000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x35 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x36 0x37 0x32 0x33>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xd0>;
			};
		};

		wiz@5030000 {
			compatible = "ti,j721e-wiz-16g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x127 0x1>;
			clocks = <0x9 0x127 0x5 0x9 0x127 0x9 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x127 0x9 0x9 0x127 0x0>;
			assigned-clock-parents = <0x9 0x127 0xd 0x9 0x127 0x4>;
			num-lanes = <0x2>;
			#reset-cells = <0x1>;
			ranges = <0x5030000 0x0 0x5030000 0x10000>;
			typec-dir-gpios = <0x38 0x3 0x0>;
			typec-dir-debounce-ms = <0x2bc>;
			phandle = <0x3c>;

			pll0-refclk {
				clocks = <0x9 0x127 0x9 0x24>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x39>;
				assigned-clock-parents = <0x9 0x127 0x9>;
				phandle = <0x39>;
			};

			pll1-refclk {
				clocks = <0x9 0x127 0x0 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x3a>;
				assigned-clock-parents = <0x9 0x127 0x0>;
				phandle = <0x3a>;
			};

			refclk-dig {
				clocks = <0x9 0x127 0x9 0x9 0x127 0x0 0x24 0x26>;
				#clock-cells = <0x0>;
				assigned-clocks = <0x3b>;
				assigned-clock-parents = <0x9 0x127 0x9>;
				phandle = <0x3b>;
			};

			cmn-refclk-dig-div {
				clocks = <0x3b>;
				#clock-cells = <0x0>;
				phandle = <0x3d>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x3a>;
				#clock-cells = <0x0>;
				phandle = <0x3e>;
			};

			serdes@5030000 {
				compatible = "ti,sierra-phy-t0";
				reg-names = "serdes";
				reg = <0x5030000 0x10000>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				resets = <0x3c 0x0>;
				reset-names = "sierra_reset";
				clocks = <0x3d 0x3e 0x39 0x3a>;
				clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
				phandle = <0xd1>;

				phy@0 {
					reg = <0x0>;
					cdns,num-lanes = <0x2>;
					#phy-cells = <0x0>;
					cdns,phy-type = <0x4>;
					resets = <0x3c 0x1 0x3c 0x2>;
					phandle = <0x4e>;
				};
			};
		};

		pcie@2900000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2900000 0x0 0x1000 0x0 0x2907000 0x0 0x400 0x0 0xd000000 0x0 0x800000 0x0 0x10000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x13e 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4070>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xef 0x1>;
			clocks = <0x9 0xef 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x0 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x10001000 0x0 0x10001000 0x0 0x10000 0x2000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x41 0x0 0x0 0x0 0x0 0x2 0x41 0x0 0x0 0x0 0x0 0x3 0x41 0x0 0x0 0x0 0x0 0x4 0x41 0x0>;
			status = "disabled";
			phandle = <0xd2>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x1>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x138 0x1>;
				phandle = <0x41>;
			};
		};

		pcie-ep@2900000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2900000 0x0 0x1000 0x0 0x2907000 0x0 0x400 0x0 0xd000000 0x0 0x800000 0x0 0x10000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x13e 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4070>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xef 0x1>;
			clocks = <0x9 0xef 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd3>;
		};

		pcie@2910000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2910000 0x0 0x1000 0x0 0x2917000 0x0 0x400 0x0 0xd800000 0x0 0x800000 0x0 0x18000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x14a 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4074>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf0 0x1>;
			clocks = <0x9 0xf0 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x10000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x18001000 0x0 0x18001000 0x0 0x10000 0x2000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x42 0x0 0x0 0x0 0x0 0x2 0x42 0x0 0x0 0x0 0x0 0x3 0x42 0x0 0x0 0x0 0x0 0x4 0x42 0x0>;
			status = "disabled";
			phandle = <0xd4>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x144 0x1>;
				phandle = <0x42>;
			};
		};

		pcie-ep@2910000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2910000 0x0 0x1000 0x0 0x2917000 0x0 0x400 0x0 0xd800000 0x0 0x800000 0x0 0x18000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x14a 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4074>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf0 0x1>;
			clocks = <0x9 0xf0 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd5>;
		};

		pcie@2920000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2920000 0x0 0x1000 0x0 0x2927000 0x0 0x400 0x0 0xe000000 0x0 0x800000 0x44 0x0 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x156 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x4078>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf1 0x1>;
			clocks = <0x9 0xf1 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x20000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x1000 0x44 0x1000 0x0 0x10000 0x2000000 0x0 0x11000 0x44 0x11000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x43 0x0 0x0 0x0 0x0 0x2 0x43 0x0 0x0 0x0 0x0 0x3 0x43 0x0 0x0 0x0 0x0 0x4 0x43 0x0>;
			status = "disabled";
			phandle = <0xd6>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x150 0x1>;
				phandle = <0x43>;
			};
		};

		pcie-ep@2920000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2920000 0x0 0x1000 0x0 0x2927000 0x0 0x400 0x0 0xe000000 0x0 0x800000 0x44 0x0 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x156 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x4078>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf1 0x1>;
			clocks = <0x9 0xf1 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			status = "disabled";
			phandle = <0xd7>;
		};

		pcie@2930000 {
			compatible = "ti,j721e-pcie-host";
			reg = <0x0 0x2930000 0x0 0x1000 0x0 0x2937000 0x0 0x400 0x0 0xe800000 0x0 0x800000 0x44 0x10000000 0x0 0x1000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
			interrupt-names = "link_state";
			interrupts = <0x0 0x162 0x1>;
			device_type = "pci";
			ti,syscon-pcie-ctrl = <0x3f 0x407c>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf2 0x1>;
			clocks = <0x9 0xf2 0x1>;
			clock-names = "fck";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x104c>;
			device-id = <0xb00d>;
			msi-map = <0x0 0x40 0x30000 0x10000>;
			dma-coherent;
			ranges = <0x1000000 0x0 0x1000 0x44 0x10001000 0x0 0x10000 0x2000000 0x0 0x11000 0x44 0x10011000 0x0 0x7fef000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
			#interrupt-cells = <0x1>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x44 0x0 0x0 0x0 0x0 0x2 0x44 0x0 0x0 0x0 0x0 0x3 0x44 0x0 0x0 0x0 0x0 0x4 0x44 0x0>;
			status = "disabled";
			phandle = <0xd8>;

			interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <0x2>;
				interrupt-parent = <0x1>;
				interrupts = <0x0 0x15c 0x1>;
				phandle = <0x44>;
			};
		};

		pcie-ep@2930000 {
			compatible = "ti,j721e-pcie-ep";
			reg = <0x0 0x2930000 0x0 0x1000 0x0 0x2937000 0x0 0x400 0x0 0xe800000 0x0 0x800000 0x44 0x10000000 0x0 0x8000000>;
			reg-names = "intd_cfg", "user_cfg", "reg", "mem";
			interrupt-names = "link_state";
			interrupts = <0x0 0x162 0x1>;
			ti,syscon-pcie-ctrl = <0x3f 0x407c>;
			max-link-speed = <0x3>;
			num-lanes = <0x2>;
			power-domains = <0x8 0xf2 0x1>;
			clocks = <0x9 0xf2 0x1>;
			clock-names = "fck";
			max-functions = [06];
			max-virtual-functions = [04 04 04 04 00 00];
			dma-coherent;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			status = "disabled";
			phandle = <0xd9>;
		};

		wiz@5050000 {
			compatible = "ti,j721e-wiz-10g";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			power-domains = <0x8 0x129 0x1>;
			clocks = <0x9 0x129 0x1 0x9 0x129 0x9 0x24>;
			clock-names = "fck", "core_ref_clk", "ext_ref_clk";
			assigned-clocks = <0x9 0x129 0x9>;
			assigned-clock-parents = <0x9 0x129 0xa>;
			assigned-clock-rates = <0x124f800>;
			num-lanes = <0x4>;
			#reset-cells = <0x1>;
			ranges = <0x5050000 0x0 0x5050000 0x10000 0xa030a00 0x0 0xa030a00 0x40>;
			phandle = <0x48>;

			pll0-refclk {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_pll0_refclk";
				#clock-cells = <0x0>;
				assigned-clocks = <0x45>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x45>;
			};

			pll1-refclk {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_pll1_refclk";
				#clock-cells = <0x0>;
				assigned-clocks = <0x46>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x46>;
			};

			refclk-dig {
				clocks = <0x9 0x129 0x9 0x24>;
				clock-output-names = "wiz4_refclk_dig";
				#clock-cells = <0x0>;
				assigned-clocks = <0x47>;
				assigned-clock-parents = <0x9 0x129 0x9>;
				phandle = <0x47>;
			};

			cmn-refclk-dig-div {
				clocks = <0x47>;
				#clock-cells = <0x0>;
				phandle = <0xda>;
			};

			cmn-refclk1-dig-div {
				clocks = <0x46>;
				#clock-cells = <0x0>;
				phandle = <0xdb>;
			};

			serdes@5050000 {
				compatible = "ti,j721e-serdes-10g";
				reg = <0x5050000 0x10000 0xa030a00 0x40>;
				reg-names = "torrent_phy", "dptx_phy";
				resets = <0x48 0x0>;
				reset-names = "torrent_reset";
				clocks = <0x45>;
				clock-names = "refclk";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0xdc>;

				phy@0 {
					reg = <0x0>;
					resets = <0x48 0x1>;
					cdns,phy-type = <0x6>;
					cdns,num-lanes = <0x4>;
					cdns,max-bit-rate = <0x1518>;
					#phy-cells = <0x0>;
					phandle = <0x56>;
				};
			};
		};

		serial@2800000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2800000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc0 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x92 0x0>;
			clocks = <0x9 0x92 0x0>;
			clock-names = "fclk";
			phandle = <0xdd>;
		};

		serial@2810000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2810000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc1 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x116 0x1>;
			clocks = <0x9 0x116 0x0>;
			clock-names = "fclk";
			phandle = <0xde>;
		};

		serial@2820000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2820000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc2 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x117 0x1>;
			clocks = <0x9 0x117 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xdf>;
		};

		serial@2830000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2830000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc3 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x118 0x1>;
			clocks = <0x9 0x118 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe0>;
		};

		serial@2840000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2840000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc4 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x119 0x1>;
			clocks = <0x9 0x119 0x0>;
			clock-names = "fclk";
			phandle = <0xe1>;
		};

		serial@2850000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2850000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc5 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11a 0x1>;
			clocks = <0x9 0x11a 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe2>;
		};

		serial@2860000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2860000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc6 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11b 0x1>;
			clocks = <0x9 0x11b 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe3>;
		};

		serial@2870000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2870000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xc7 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11c 0x1>;
			clocks = <0x9 0x11c 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe4>;
		};

		serial@2880000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2880000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xf8 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11d 0x1>;
			clocks = <0x9 0x11d 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe5>;
		};

		serial@2890000 {
			compatible = "ti,j721e-uart", "ti,am654-uart";
			reg = <0x0 0x2890000 0x0 0x100>;
			reg-shift = <0x2>;
			reg-io-width = <0x4>;
			interrupts = <0x0 0xf9 0x4>;
			clock-frequency = <0x2dc6c00>;
			current-speed = <0x1c200>;
			power-domains = <0x8 0x11e 0x1>;
			clocks = <0x9 0x11e 0x0>;
			clock-names = "fclk";
			status = "disabled";
			phandle = <0xe6>;
		};

		gpio@600000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x600000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x69 0x1>;
			clocks = <0x9 0x69 0x0>;
			clock-names = "gpio";
			phandle = <0x81>;
		};

		gpio@601000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x601000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x120 0x121 0x122>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6a 0x1>;
			clocks = <0x9 0x6a 0x0>;
			clock-names = "gpio";
			phandle = <0x38>;
		};

		gpio@610000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x610000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x108 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6b 0x1>;
			clocks = <0x9 0x6b 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe7>;
		};

		gpio@611000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x611000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x124 0x125 0x126>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6c 0x1>;
			clocks = <0x9 0x6c 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe8>;
		};

		gpio@620000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x620000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6d 0x1>;
			clocks = <0x9 0x6d 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xe9>;
		};

		gpio@621000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x621000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x128 0x129 0x12a>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6e 0x1>;
			clocks = <0x9 0x6e 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xea>;
		};

		gpio@630000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x630000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x118 0x119 0x11a 0x11b 0x11c 0x11d 0x11e 0x11f>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x80>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x6f 0x1>;
			clocks = <0x9 0x6f 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xeb>;
		};

		gpio@631000 {
			compatible = "ti,j721e-gpio", "ti,keystone-gpio";
			reg = <0x0 0x631000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-parent = <0x49>;
			interrupts = <0x12c 0x12d 0x12e>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,ngpio = <0x24>;
			ti,davinci-gpio-unbanked = <0x0>;
			power-domains = <0x8 0x70 0x1>;
			clocks = <0x9 0x70 0x0>;
			clock-names = "gpio";
			status = "disabled";
			phandle = <0xec>;
		};

		mmc@4f80000 {
			compatible = "ti,j721e-sdhci-8bit";
			reg = <0x0 0x4f80000 0x0 0x1000 0x0 0x4f88000 0x0 0x400>;
			interrupts = <0x0 0x3 0x4>;
			power-domains = <0x8 0x5b 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5b 0x0 0x9 0x5b 0x1>;
			assigned-clocks = <0x9 0x5b 0x1>;
			assigned-clock-parents = <0x9 0x5b 0x2>;
			bus-width = <0x8>;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
			ti,otap-del-sel-legacy = <0xf>;
			ti,otap-del-sel-mmc-hs = <0xf>;
			ti,otap-del-sel-ddr52 = <0x5>;
			ti,otap-del-sel-hs200 = <0x6>;
			ti,otap-del-sel-hs400 = <0x0>;
			ti,itap-del-sel-legacy = <0x10>;
			ti,itap-del-sel-mmc-hs = <0xa>;
			ti,itap-del-sel-ddr52 = <0x3>;
			ti,trm-icp = <0x8>;
			ti,strobe-sel = <0x77>;
			dma-coherent;
			non-removable;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			phandle = <0xed>;
		};

		mmc@4fb0000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x0 0x4fb0000 0x0 0x1000 0x0 0x4fb8000 0x0 0x400>;
			interrupts = <0x0 0x4 0x4>;
			power-domains = <0x8 0x5c 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5c 0x5 0x9 0x5c 0x0>;
			assigned-clocks = <0x9 0x5c 0x0>;
			assigned-clock-parents = <0x9 0x5c 0x1>;
			ti,otap-del-sel-legacy = <0x0>;
			ti,otap-del-sel-sd-hs = <0xf>;
			ti,otap-del-sel-sdr12 = <0xf>;
			ti,otap-del-sel-sdr25 = <0xf>;
			ti,otap-del-sel-sdr50 = <0xc>;
			ti,otap-del-sel-ddr50 = <0xc>;
			ti,itap-del-sel-legacy = <0x0>;
			ti,itap-del-sel-sd-hs = <0x0>;
			ti,itap-del-sel-sdr12 = <0x0>;
			ti,itap-del-sel-sdr25 = <0x0>;
			ti,itap-del-sel-ddr50 = <0x2>;
			ti,trm-icp = <0x8>;
			ti,clkbuf-sel = <0x7>;
			dma-coherent;
			sdhci-caps-mask = <0x2 0x0>;
			vmmc-supply = <0x4a>;
			vqmmc-supply = <0x4b>;
			pinctrl-names = "default";
			pinctrl-0 = <0x4c>;
			ti,driver-strength-ohm = <0x32>;
			disable-wp;
			phandle = <0xee>;
		};

		mmc@4f98000 {
			compatible = "ti,j721e-sdhci-4bit";
			reg = <0x0 0x4f98000 0x0 0x1000 0x0 0x4f90000 0x0 0x400>;
			interrupts = <0x0 0x5 0x4>;
			power-domains = <0x8 0x5d 0x1>;
			clock-names = "clk_ahb", "clk_xin";
			clocks = <0x9 0x5d 0x5 0x9 0x5d 0x0>;
			assigned-clocks = <0x9 0x5d 0x0>;
			assigned-clock-parents = <0x9 0x5d 0x1>;
			ti,otap-del-sel-legacy = <0x0>;
			ti,otap-del-sel-sd-hs = <0xf>;
			ti,otap-del-sel-sdr12 = <0xf>;
			ti,otap-del-sel-sdr25 = <0xf>;
			ti,otap-del-sel-sdr50 = <0xc>;
			ti,otap-del-sel-ddr50 = <0xc>;
			ti,itap-del-sel-legacy = <0x0>;
			ti,itap-del-sel-sd-hs = <0x0>;
			ti,itap-del-sel-sdr12 = <0x0>;
			ti,itap-del-sel-sdr25 = <0x0>;
			ti,itap-del-sel-ddr50 = <0x2>;
			ti,trm-icp = <0x8>;
			ti,clkbuf-sel = <0x7>;
			dma-coherent;
			sdhci-caps-mask = <0x2 0x0>;
			status = "disabled";
			phandle = <0xef>;
		};

		cdns-usb@4104000 {
			compatible = "ti,j721e-usb";
			reg = <0x0 0x4104000 0x0 0x100>;
			dma-coherent;
			power-domains = <0x8 0x120 0x1>;
			clocks = <0x9 0x120 0xf 0x9 0x120 0x3>;
			clock-names = "ref", "lpm";
			assigned-clocks = <0x9 0x120 0xf>;
			assigned-clock-parents = <0x9 0x120 0x10>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <0x4d>;
			ti,vbus-divider;
			phandle = <0xf0>;

			usb@6000000 {
				compatible = "cdns,usb3";
				reg = <0x0 0x6000000 0x0 0x10000 0x0 0x6010000 0x0 0x10000 0x0 0x6020000 0x0 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <0x0 0x60 0x4 0x0 0x66 0x4 0x0 0x78 0x4>;
				interrupt-names = "host", "peripheral", "otg";
				maximum-speed = "super-speed";
				dr_mode = "otg";
				phys = <0x4e>;
				phy-names = "cdns3,usb3-phy";
				phandle = <0xf1>;
			};
		};

		cdns-usb@4114000 {
			compatible = "ti,j721e-usb";
			reg = <0x0 0x4114000 0x0 0x100>;
			dma-coherent;
			power-domains = <0x8 0x121 0x1>;
			clocks = <0x9 0x121 0xf 0x9 0x121 0x3>;
			clock-names = "ref", "lpm";
			assigned-clocks = <0x9 0x121 0xf>;
			assigned-clock-parents = <0x9 0x121 0x10>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <0x4f>;
			ti,usb2-only;
			phandle = <0xf2>;

			usb@6400000 {
				compatible = "cdns,usb3";
				reg = <0x0 0x6400000 0x0 0x10000 0x0 0x6410000 0x0 0x10000 0x0 0x6420000 0x0 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <0x0 0x68 0x4 0x0 0x6e 0x4 0x0 0x79 0x4>;
				interrupt-names = "host", "peripheral", "otg";
				maximum-speed = "high-speed";
				dr_mode = "host";
				phandle = <0xf3>;
			};
		};

		i2c@2000000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2000000 0x0 0x100>;
			interrupts = <0x0 0xc8 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbb 0x0>;
			power-domains = <0x8 0xbb 0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x50>;
			clock-frequency = <0x61a80>;
			phandle = <0xf4>;

			gpio@20 {
				compatible = "ti,tca6416";
				reg = <0x20>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0xf5>;
			};

			gpio@22 {
				compatible = "ti,tca6424";
				reg = <0x22>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0xf6>;

				p08-hog {
					gpio-hog;
					gpios = <0x8 0x0>;
					output-high;
					line-name = "CTRL_PM_I2C_OE";
				};

				p09-hog {
					gpio-hog;
					gpios = <0x9 0x0>;
					output-low;
					line-name = "MCASP/TRACE_MUX_S0";
				};

				p10-hog {
					gpio-hog;
					gpios = <0xa 0x0>;
					output-high;
					line-name = "MCASP/TRACE_MUX_S1";
				};
			};
		};

		i2c@2010000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2010000 0x0 0x100>;
			interrupts = <0x0 0xc9 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbc 0x0>;
			power-domains = <0x8 0xbc 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x51>;
			clock-frequency = <0x61a80>;
			phandle = <0xf7>;
		};

		i2c@2020000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2020000 0x0 0x100>;
			interrupts = <0x0 0xca 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbd 0x0>;
			power-domains = <0x8 0xbd 0x1>;
			phandle = <0xf8>;
		};

		i2c@2030000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2030000 0x0 0x100>;
			interrupts = <0x0 0xcb 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbe 0x0>;
			power-domains = <0x8 0xbe 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x52>;
			clock-frequency = <0x61a80>;
			phandle = <0xf9>;

			gpio@20 {
				compatible = "ti,tca6408";
				reg = <0x20>;
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0x53>;
			};

			audio-codec@44 {
				compatible = "ti,pcm3168a";
				reg = <0x44>;
				#sound-dai-cells = <0x1>;
				reset-gpios = <0x53 0x0 0x1>;
				clocks = <0x9 0x9d 0x173>;
				clock-names = "scki";
				assigned-clocks = <0x9 0x9d 0x173>;
				assigned-clock-parents = <0x9 0x9d 0x190>;
				assigned-clock-rates = <0x1770000>;
				VDD1-supply = <0x54>;
				VDD2-supply = <0x54>;
				VCCAD1-supply = <0x55>;
				VCCAD2-supply = <0x55>;
				VCCDA1-supply = <0x55>;
				VCCDA2-supply = <0x55>;
				phandle = <0x86>;
			};
		};

		i2c@2040000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2040000 0x0 0x100>;
			interrupts = <0x0 0xcc 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xbf 0x0>;
			power-domains = <0x8 0xbf 0x1>;
			phandle = <0xfa>;
		};

		i2c@2050000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2050000 0x0 0x100>;
			interrupts = <0x0 0xcd 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xc0 0x0>;
			power-domains = <0x8 0xc0 0x1>;
			phandle = <0xfb>;
		};

		i2c@2060000 {
			compatible = "ti,j721e-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2060000 0x0 0x100>;
			interrupts = <0x0 0xce 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "fck";
			clocks = <0x9 0xc1 0x0>;
			power-domains = <0x8 0xc1 0x1>;
			phandle = <0xfc>;
		};

		video-decoder@4300000 {
			compatible = "img,d5500-vxd";
			reg = <0x0 0x4300000 0x0 0x100000>;
			power-domains = <0x8 0x90 0x1>;
			interrupts = <0x0 0xb4 0x4>;
			phandle = <0xfd>;
		};

		video-encoder@4200000 {
			compatible = "img,vxe384";
			reg = <0x0 0x4200000 0x0 0x100000>;
			power-domains = <0x8 0x99 0x1>;
			interrupts = <0x0 0xb5 0x4>;
			phandle = <0xfe>;
		};

		ufs-wrapper@4e80000 {
			compatible = "ti,j721e-ufs";
			reg = <0x0 0x4e80000 0x0 0x100>;
			power-domains = <0x8 0x115 0x1>;
			clocks = <0x9 0x115 0x1>;
			assigned-clocks = <0x9 0x115 0x1>;
			assigned-clock-parents = <0x9 0x115 0x4>;
			ranges;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			phandle = <0xff>;

			ufs@4e84000 {
				compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
				reg = <0x0 0x4e84000 0x0 0x10000>;
				interrupts = <0x0 0x11 0x4>;
				freq-table-hz = <0xee6b280 0xee6b280 0x124f800 0x124f800 0x124f800 0x124f800>;
				clocks = <0x9 0x115 0x0 0x9 0x115 0x1 0x9 0x115 0x1>;
				clock-names = "core_clk", "phy_clk", "ref_clk";
				dma-coherent;
			};
		};

		dp-bridge@a000000 {
			compatible = "ti,j721e-mhdp8546";
			reg = <0x0 0xa000000 0x0 0x30a00 0x0 0x4f40000 0x0 0x20>;
			reg-names = "mhdptx", "j721e-intg";
			clocks = <0x9 0x97 0x24>;
			phys = <0x56>;
			phy-names = "dpphy";
			interrupt-parent = <0x1>;
			interrupts = <0x0 0x266 0x4>;
			power-domains = <0x8 0x97 0x1>;
			pinctrl-names = "default";
			pinctrl-0 = <0x57>;
			phandle = <0x100>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x101>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x58>;
						phandle = <0x5a>;
					};
				};

				port@4 {
					reg = <0x4>;

					endpoint {
						remote-endpoint = <0x59>;
						phandle = <0x88>;
					};
				};
			};
		};

		dss@4a00000 {
			compatible = "ti,j721e-dss";
			reg = <0x0 0x4a00000 0x0 0x10000 0x0 0x4a10000 0x0 0x10000 0x0 0x4b00000 0x0 0x10000 0x0 0x4b10000 0x0 0x10000 0x0 0x4a20000 0x0 0x10000 0x0 0x4a30000 0x0 0x10000 0x0 0x4a50000 0x0 0x10000 0x0 0x4a60000 0x0 0x10000 0x0 0x4a70000 0x0 0x10000 0x0 0x4a90000 0x0 0x10000 0x0 0x4ab0000 0x0 0x10000 0x0 0x4ad0000 0x0 0x10000 0x0 0x4a80000 0x0 0x10000 0x0 0x4aa0000 0x0 0x10000 0x0 0x4ac0000 0x0 0x10000 0x0 0x4ae0000 0x0 0x10000 0x0 0x4af0000 0x0 0x10000>;
			reg-names = "common_m", "common_s0", "common_s1", "common_s2", "vidl1", "vidl2", "vid1", "vid2", "ovr1", "ovr2", "ovr3", "ovr4", "vp1", "vp2", "vp3", "vp4", "wb";
			clocks = <0x9 0x98 0x0 0x9 0x98 0x1 0x9 0x98 0x4 0x9 0x98 0x9 0x9 0x98 0xd>;
			clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
			power-domains = <0x8 0x98 0x1>;
			interrupts = <0x0 0x25a 0x4 0x0 0x25b 0x4 0x0 0x25c 0x4 0x0 0x25d 0x4>;
			interrupt-names = "common_m", "common_s0", "common_s1", "common_s2";
			assigned-clocks = <0x9 0x98 0x1 0x9 0x98 0x4 0x9 0x98 0x9 0x9 0x98 0xd>;
			assigned-clock-parents = <0x9 0x98 0x2 0x9 0x98 0x6 0x9 0x98 0xb 0x9 0x98 0x12>;
			phandle = <0x102>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				phandle = <0x103>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0x5a>;
						phandle = <0x58>;
					};
				};
			};
		};

		mcasp@2b00000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b00000 0x0 0x2000 0x0 0x2b08000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x220 0x4 0x0 0x221 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc400 0xe 0x4400>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xae 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xae 0x1>;
			#sound-dai-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x5b>;
			op-mode = <0x0>;
			tdm-slots = <0x8>;
			auxclk-fs-ratio = <0x100>;
			serial-dir = <0x1 0x2 0x0 0x0 0x0 0x0 0x0 0x0>;
			tx-num-evt = <0x8>;
			rx-num-evt = <0x8>;
			phandle = <0x85>;
		};

		mcasp@2b10000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b10000 0x0 0x2000 0x0 0x2b18000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x222 0x4 0x0 0x223 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc401 0xe 0x4401>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xaf 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xaf 0x1>;
			status = "disabled";
			phandle = <0x104>;
		};

		mcasp@2b20000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b20000 0x0 0x2000 0x0 0x2b28000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x224 0x4 0x0 0x225 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc402 0xe 0x4402>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb0 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb0 0x1>;
			status = "disabled";
			phandle = <0x105>;
		};

		mcasp@2b30000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b30000 0x0 0x2000 0x0 0x2b38000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x226 0x4 0x0 0x227 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc500 0xe 0x4500>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb1 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb1 0x1>;
			status = "disabled";
			phandle = <0x106>;
		};

		mcasp@2b40000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b40000 0x0 0x2000 0x0 0x2b48000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x228 0x4 0x0 0x229 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc501 0xe 0x4501>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb2 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb2 0x1>;
			status = "disabled";
			phandle = <0x107>;
		};

		mcasp@2b50000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b50000 0x0 0x2000 0x0 0x2b58000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22a 0x4 0x0 0x22b 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc502 0xe 0x4502>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb3 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb3 0x1>;
			status = "disabled";
			phandle = <0x108>;
		};

		mcasp@2b60000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b60000 0x0 0x2000 0x0 0x2b68000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22c 0x4 0x0 0x22d 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc503 0xe 0x4503>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb4 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb4 0x1>;
			status = "disabled";
			phandle = <0x109>;
		};

		mcasp@2b70000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b70000 0x0 0x2000 0x0 0x2b78000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x22e 0x4 0x0 0x22f 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc504 0xe 0x4504>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb5 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb5 0x1>;
			status = "disabled";
			phandle = <0x10a>;
		};

		mcasp@2b80000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b80000 0x0 0x2000 0x0 0x2b88000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x230 0x4 0x0 0x231 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc505 0xe 0x4505>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb6 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb6 0x1>;
			status = "disabled";
			phandle = <0x10b>;
		};

		mcasp@2b90000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2b90000 0x0 0x2000 0x0 0x2b98000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x232 0x4 0x0 0x233 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc506 0xe 0x4506>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb7 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb7 0x1>;
			status = "disabled";
			phandle = <0x10c>;
		};

		mcasp@2ba0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2ba0000 0x0 0x2000 0x0 0x2ba8000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x234 0x4 0x0 0x235 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc507 0xe 0x4507>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb8 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb8 0x1>;
			status = "disabled";
			phandle = <0x10d>;
		};

		mcasp@2bb0000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x2bb0000 0x0 0x2000 0x0 0x2bb8000 0x0 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x236 0x4 0x0 0x237 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xe 0xc508 0xe 0x4508>;
			dma-names = "tx", "rx";
			clocks = <0x9 0xb9 0x1>;
			clock-names = "fck";
			power-domains = <0x8 0xb9 0x1>;
			status = "disabled";
			phandle = <0x10e>;
		};

		watchdog@2200000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x0 0x2200000 0x0 0x100>;
			clocks = <0x9 0xfc 0x1>;
			power-domains = <0x8 0xfc 0x1>;
			assigned-clocks = <0x9 0xfc 0x1>;
			assigned-clock-parents = <0x9 0xfc 0x5>;
			phandle = <0x10f>;
		};

		watchdog@2210000 {
			compatible = "ti,j7-rti-wdt";
			reg = <0x0 0x2210000 0x0 0x100>;
			clocks = <0x9 0xfd 0x1>;
			power-domains = <0x8 0xfd 0x1>;
			assigned-clocks = <0x9 0xfd 0x1>;
			assigned-clock-parents = <0x9 0xfd 0x5>;
			phandle = <0x110>;
		};

		r5fss@5c00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x0>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x5c00000 0x0 0x5c00000 0x20000 0x5d00000 0x0 0x5d00000 0x20000>;
			power-domains = <0x8 0xf3 0x1>;
			phandle = <0x111>;

			r5f@5c00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5c00000 0x8000 0x5c10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf5>;
				ti,sci-proc-ids = <0x6 0xff>;
				resets = <0x17 0xf5 0x1>;
				firmware-name = "j7-main-r5f0_0-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x5c 0x5d>;
				memory-region = <0x5e 0x5f 0x60 0x61>;
				phandle = <0x112>;
			};

			r5f@5d00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5d00000 0x8000 0x5d10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf6>;
				ti,sci-proc-ids = <0x7 0xff>;
				resets = <0x17 0xf6 0x1>;
				firmware-name = "j7-main-r5f0_1-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x5c 0x62>;
				memory-region = <0x63 0x64>;
				phandle = <0x113>;
			};
		};

		r5fss@5e00000 {
			compatible = "ti,j721e-r5fss";
			ti,cluster-mode = <0x0>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x5e00000 0x0 0x5e00000 0x20000 0x5f00000 0x0 0x5f00000 0x20000>;
			power-domains = <0x8 0xf4 0x1>;
			phandle = <0x114>;

			r5f@5e00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5e00000 0x8000 0x5e10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf7>;
				ti,sci-proc-ids = <0x8 0xff>;
				resets = <0x17 0xf7 0x1>;
				firmware-name = "j7-main-r5f1_0-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x65 0x66>;
				memory-region = <0x67 0x68>;
				phandle = <0x115>;
			};

			r5f@5f00000 {
				compatible = "ti,j721e-r5f";
				reg = <0x5f00000 0x8000 0x5f10000 0x8000>;
				reg-names = "atcm", "btcm";
				ti,sci = <0xa>;
				ti,sci-dev-id = <0xf8>;
				ti,sci-proc-ids = <0x9 0xff>;
				resets = <0x17 0xf8 0x1>;
				firmware-name = "j7-main-r5f1_1-fw";
				ti,atcm-enable = <0x1>;
				ti,btcm-enable = <0x1>;
				ti,loczrama = <0x1>;
				mboxes = <0x65 0x69>;
				memory-region = <0x6a 0x6b>;
				phandle = <0x116>;
			};
		};

		dsp@4d80800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x80800000 0x0 0x48000 0x4d 0x80e00000 0x0 0x8000 0x4d 0x80f00000 0x0 0x8000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x8e>;
			ti,sci-proc-ids = <0x3 0xff>;
			resets = <0x17 0x8e 0x1>;
			firmware-name = "j7-c66_0-fw";
			mboxes = <0x6c 0x6d>;
			memory-region = <0x6e 0x6f>;
			phandle = <0x117>;
		};

		dsp@4d81800000 {
			compatible = "ti,j721e-c66-dsp";
			reg = <0x4d 0x81800000 0x0 0x48000 0x4d 0x81e00000 0x0 0x8000 0x4d 0x81f00000 0x0 0x8000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0x8f>;
			ti,sci-proc-ids = <0x4 0xff>;
			resets = <0x17 0x8f 0x1>;
			firmware-name = "j7-c66_1-fw";
			mboxes = <0x6c 0x70>;
			memory-region = <0x71 0x72>;
			phandle = <0x118>;
		};

		dsp@64800000 {
			compatible = "ti,j721e-c71-dsp";
			reg = <0x0 0x64800000 0x0 0x80000 0x0 0x64e00000 0x0 0xc000>;
			reg-names = "l2sram", "l1dram";
			ti,sci = <0xa>;
			ti,sci-dev-id = <0xf>;
			ti,sci-proc-ids = <0x30 0xff>;
			resets = <0x17 0xf 0x1>;
			firmware-name = "j7-c71_0-fw";
			mboxes = <0x73 0x74>;
			memory-region = <0x75 0x76>;
			phandle = <0x119>;
		};

		icssg@b000000 {
			compatible = "ti,j721e-icssg";
			reg = <0x0 0xb000000 0x0 0x80000>;
			power-domains = <0x8 0x77 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0xb000000 0x100000>;
			phandle = <0x11a>;

			memories@0 {
				reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0", "dram1", "shrdram2";
				phandle = <0x11b>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg", "syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x26000 0x2000>;
				phandle = <0x11c>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x77 0x18 0x9 0x77 0x1>;
						assigned-clocks = <0x77>;
						assigned-clock-parents = <0x9 0x77 0x1>;
						phandle = <0x77>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x77 0x3 0x77>;
						assigned-clocks = <0x78>;
						assigned-clock-parents = <0x77>;
						phandle = <0x78>;
					};
				};
			};

			iep@2e000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2e000 0x1000>;
				clocks = <0x78>;
				phandle = <0x11d>;
			};

			iep@2f000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2f000 0x1000>;
				clocks = <0x78>;
				phandle = <0x11e>;
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii", "syscon";
				reg = <0x32000 0x100>;
				phandle = <0x11f>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g", "syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x120>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x3>;
				interrupts = <0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4 0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4 0x0 0x105 0x4>;
				interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7";
				phandle = <0x79>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x3000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru0_0-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x10 0x2 0x2>;
				interrupt-names = "vring";
				phandle = <0x121>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu0_0-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x14 0x4 0x4>;
				interrupt-names = "vring";
				phandle = <0x122>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru0_0-fw";
				phandle = <0x123>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x3000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru0_1-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x12 0x3 0x3>;
				interrupt-names = "vring";
				phandle = <0x124>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu0_1-fw";
				interrupt-parent = <0x79>;
				interrupts = <0x16 0x5 0x5>;
				interrupt-names = "vring";
				phandle = <0x125>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru0_1-fw";
				phandle = <0x126>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x9 0x77 0x1>;
				clock-names = "fck";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x127>;
			};
		};

		icssg@b100000 {
			compatible = "ti,j721e-icssg";
			reg = <0x0 0xb100000 0x0 0x80000>;
			power-domains = <0x8 0x78 0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x0 0xb100000 0x100000>;
			phandle = <0x128>;

			memories@b100000 {
				reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x10000>;
				reg-names = "dram0", "dram1", "shrdram2";
				phandle = <0x129>;
			};

			cfg@26000 {
				compatible = "ti,pruss-cfg", "syscon";
				reg = <0x26000 0x200>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x26000 0x2000>;
				phandle = <0x12a>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					coreclk-mux@3c {
						reg = <0x3c>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x78 0x36 0x9 0x78 0x4>;
						assigned-clocks = <0x7a>;
						assigned-clock-parents = <0x9 0x78 0x4>;
						phandle = <0x7a>;
					};

					iepclk-mux@30 {
						reg = <0x30>;
						#clock-cells = <0x0>;
						clocks = <0x9 0x78 0x9 0x7a>;
						assigned-clocks = <0x7b>;
						assigned-clock-parents = <0x7a>;
						phandle = <0x7b>;
					};
				};
			};

			iep@2e000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2e000 0x1000>;
				clocks = <0x7b>;
				phandle = <0x12b>;
			};

			iep@2f000 {
				compatible = "ti,am654-icss-iep";
				reg = <0x2f000 0x1000>;
				clocks = <0x7b>;
				phandle = <0x12c>;
			};

			mii-rt@32000 {
				compatible = "ti,pruss-mii", "syscon";
				reg = <0x32000 0x100>;
				phandle = <0x12d>;
			};

			mii-g-rt@33000 {
				compatible = "ti,pruss-mii-g", "syscon";
				reg = <0x33000 0x1000>;
				phandle = <0x12e>;
			};

			interrupt-controller@20000 {
				compatible = "ti,icssg-intc";
				reg = <0x20000 0x2000>;
				interrupt-controller;
				#interrupt-cells = <0x3>;
				interrupts = <0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4 0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4 0x0 0x10d 0x4>;
				interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", "host_intr6", "host_intr7";
				phandle = <0x7c>;
			};

			pru@34000 {
				compatible = "ti,j721e-pru";
				reg = <0x34000 0x4000 0x22000 0x100 0x22400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru1_0-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x10 0x2 0x2>;
				interrupt-names = "vring";
				phandle = <0x12f>;
			};

			rtu@4000 {
				compatible = "ti,j721e-rtu";
				reg = <0x4000 0x2000 0x23000 0x100 0x23400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu1_0-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x14 0x4 0x4>;
				interrupt-names = "vring";
				phandle = <0x130>;
			};

			txpru@a000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xa000 0x1800 0x25000 0x100 0x25400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru1_0-fw";
				phandle = <0x131>;
			};

			pru@38000 {
				compatible = "ti,j721e-pru";
				reg = <0x38000 0x4000 0x24000 0x100 0x24400 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-pru1_1-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x12 0x3 0x3>;
				interrupt-names = "vring";
				phandle = <0x132>;
			};

			rtu@6000 {
				compatible = "ti,j721e-rtu";
				reg = <0x6000 0x2000 0x23800 0x100 0x23c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-rtu1_1-fw";
				interrupt-parent = <0x7c>;
				interrupts = <0x16 0x5 0x5>;
				interrupt-names = "vring";
				phandle = <0x133>;
			};

			txpru@c000 {
				compatible = "ti,j721e-tx-pru";
				reg = <0xc000 0x1800 0x25800 0x100 0x25c00 0x100>;
				reg-names = "iram", "control", "debug";
				firmware-name = "j7-txpru1_1-fw";
				phandle = <0x134>;
			};

			mdio@32400 {
				compatible = "ti,davinci_mdio";
				reg = <0x32400 0x100>;
				clocks = <0x9 0x78 0x4>;
				clock-names = "fck";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				bus_freq = <0xf4240>;
				status = "disabled";
				phandle = <0x135>;
			};
		};

		timesync_router@A40000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xa40000 0x0 0x800>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			#pinctrl-cells = <0x1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x107ff>;
			status = "disabled";
			phandle = <0x136>;
		};

		gpu@4e20000000 {
			compatible = "ti,j721e-pvr", "img,pvr-ge8430";
			reg = <0x4e 0x20000000 0x0 0x80000>;
			reg-names = "gpu_regs";
			interrupts = <0x0 0x18 0x4>;
			power-domains = <0x8 0x7d 0x1 0x8 0x7e 0x1>;
			power-domain-names = "gpu_0", "gpucore_0";
			clocks = <0x9 0x7d 0x0>;
			clock-names = "ctrl";
			phandle = <0x137>;
		};

		can@2701000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2701000 0x0 0x200 0x0 0x2708000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0x9c 0x1>;
			clocks = <0x9 0x9c 0x0 0x9 0x9c 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x7c 0x4 0x0 0x7d 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x138>;
		};

		can@2711000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2711000 0x0 0x200 0x0 0x2718000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0x9e 0x1>;
			clocks = <0x9 0x9e 0x0 0x9 0x9e 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x7f 0x4 0x0 0x80 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x139>;
		};

		can@2721000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2721000 0x0 0x200 0x0 0x2728000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa0 0x1>;
			clocks = <0x9 0xa0 0x0 0x9 0xa0 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x82 0x4 0x0 0x83 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13a>;
		};

		can@2731000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2731000 0x0 0x200 0x0 0x2738000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa1 0x1>;
			clocks = <0x9 0xa1 0x0 0x9 0xa1 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x85 0x4 0x0 0x86 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13b>;
		};

		can@2741000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2741000 0x0 0x200 0x0 0x2748000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa2 0x1>;
			clocks = <0x9 0xa2 0x0 0x9 0xa2 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x88 0x4 0x0 0x89 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13c>;
		};

		can@2751000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2751000 0x0 0x200 0x0 0x2758000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa3 0x1>;
			clocks = <0x9 0xa3 0x0 0x9 0xa3 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x8b 0x4 0x0 0x8c 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13d>;
		};

		can@2761000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2761000 0x0 0x200 0x0 0x2768000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa4 0x1>;
			clocks = <0x9 0xa4 0x0 0x9 0xa4 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x8e 0x4 0x0 0x8f 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13e>;
		};

		can@2771000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2771000 0x0 0x200 0x0 0x2778000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa5 0x1>;
			clocks = <0x9 0xa5 0x0 0x9 0xa5 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x91 0x4 0x0 0x92 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x13f>;
		};

		can@2781000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2781000 0x0 0x200 0x0 0x2788000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa6 0x1>;
			clocks = <0x9 0xa6 0x0 0x9 0xa6 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x240 0x4 0x0 0x241 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x140>;
		};

		can@2791000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x2791000 0x0 0x200 0x0 0x2798000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa7 0x1>;
			clocks = <0x9 0xa7 0x0 0x9 0xa7 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x243 0x4 0x0 0x244 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x141>;
		};

		can@27a1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27a1000 0x0 0x200 0x0 0x27a8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa8 0x1>;
			clocks = <0x9 0xa8 0x0 0x9 0xa8 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x246 0x4 0x0 0x247 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x142>;
		};

		can@27b1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27b1000 0x0 0x200 0x0 0x27b8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xa9 0x1>;
			clocks = <0x9 0xa9 0x0 0x9 0xa9 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x249 0x4 0x0 0x24a 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x143>;
		};

		can@27c1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27c1000 0x0 0x200 0x0 0x27c8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xaa 0x1>;
			clocks = <0x9 0xaa 0x0 0x9 0xaa 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x24c 0x4 0x0 0x24d 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x144>;
		};

		can@27d1000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x27d1000 0x0 0x200 0x0 0x27d8000 0x0 0x8000>;
			reg-names = "m_can", "message_ram";
			power-domains = <0x8 0xab 0x1>;
			clocks = <0x9 0xab 0x0 0x9 0xab 0x1>;
			clock-names = "hclk", "cclk";
			interrupts = <0x0 0x24f 0x4 0x0 0x250 0x4>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
			status = "disabled";
			phandle = <0x145>;
		};

		ticsi2rx@4500000 {
			compatible = "ti,j721e-csi2rx";
			dmas = <0xe 0x4940 0xe 0x4941 0xe 0x4942 0xe 0x4943 0xe 0x4944 0xe 0x4945 0xe 0x4946 0xe 0x4947 0xe 0x4948 0xe 0x4949 0xe 0x494a 0xe 0x494b 0xe 0x494c 0xe 0x494d 0xe 0x494e 0xe 0x494f>;
			dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
			reg = <0x0 0x4500000 0x0 0x1000>;
			power-domains = <0x8 0x1a 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			phandle = <0x146>;

			csi-bridge@4504000 {
				compatible = "cdns,csi2rx";
				reg = <0x0 0x4504000 0x0 0x1000>;
				clocks = <0x9 0x1a 0x2 0x9 0x1a 0x0 0x9 0x1a 0x2 0x9 0x1a 0x2 0x9 0x1a 0x3 0x9 0x1a 0x3>;
				clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
				phys = <0x7d>;
				phy-names = "dphy";
				power-domains = <0x8 0x1a 0x1>;
				phandle = <0x147>;

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;
						status = "disabled";
						phandle = <0x148>;
					};

					port@1 {
						reg = <0x1>;
						status = "disabled";
						phandle = <0x149>;
					};

					port@2 {
						reg = <0x2>;
						status = "disabled";
						phandle = <0x14a>;
					};

					port@3 {
						reg = <0x3>;
						status = "disabled";
						phandle = <0x14b>;
					};

					port@4 {
						reg = <0x4>;
						status = "disabled";
						phandle = <0x14c>;
					};
				};
			};
		};

		ticsi2rx@4510000 {
			compatible = "ti,j721e-csi2rx";
			dmas = <0xe 0x4960 0xe 0x4961 0xe 0x4962 0xe 0x4963 0xe 0x4964 0xe 0x4965 0xe 0x4966 0xe 0x4967 0xe 0x4968 0xe 0x4969 0xe 0x496a 0xe 0x496b 0xe 0x496c 0xe 0x496d 0xe 0x496e 0xe 0x496f>;
			dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
			reg = <0x0 0x4510000 0x0 0x1000>;
			power-domains = <0x8 0x1b 0x1>;
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges;
			phandle = <0x14d>;

			csi-bridge@4514000 {
				compatible = "cdns,csi2rx";
				reg = <0x0 0x4514000 0x0 0x1000>;
				clocks = <0x9 0x1b 0x2 0x9 0x1b 0x0 0x9 0x1b 0x2 0x9 0x1b 0x2 0x9 0x1b 0x3 0x9 0x1b 0x3>;
				clock-names = "sys_clk", "p_clk", "pixel_if0_clk", "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
				phys = <0x7e>;
				phy-names = "dphy";
				power-domains = <0x8 0x1b 0x1>;
				phandle = <0x14e>;

				ports {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					port@0 {
						reg = <0x0>;
						phandle = <0x14f>;
					};

					port@1 {
						reg = <0x1>;
						phandle = <0x150>;
					};

					port@2 {
						reg = <0x2>;
						phandle = <0x151>;
					};

					port@3 {
						reg = <0x3>;
						phandle = <0x152>;
					};

					port@4 {
						reg = <0x4>;
						phandle = <0x153>;
					};
				};
			};
		};

		phy@4580000 {
			compatible = "ti,j721e-dphy", "cdns,dphy";
			reg = <0x0 0x4580000 0x0 0x1100>;
			#phy-cells = <0x0>;
			power-domains = <0x8 0x93 0x1>;
			phandle = <0x7d>;
		};

		phy@4590000 {
			compatible = "ti,j721e-dphy", "cdns,dphy";
			reg = <0x0 0x4590000 0x0 0x1100>;
			#phy-cells = <0x0>;
			power-domains = <0x8 0x94 0x1>;
			phandle = <0x7e>;
		};
	};

	clock-cmnrefclk {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x0>;
		phandle = <0x24>;
	};

	clock-cmnrefclk1 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x5f5e100>;
		phandle = <0x26>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000 0x8 0x80000000 0x0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		phandle = <0x154>;

		optee@9e800000 {
			reg = <0x0 0x9e800000 0x0 0x1800000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x155>;
		};

		r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa0000000 0x0 0x100000>;
			no-map;
			phandle = <0x1a>;
		};

		r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa0100000 0x0 0xf00000>;
			no-map;
			phandle = <0x1b>;
		};

		r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa1000000 0x0 0x100000>;
			no-map;
			phandle = <0x1d>;
		};

		r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa1100000 0x0 0xf00000>;
			no-map;
			phandle = <0x1e>;
		};

		r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa2000000 0x0 0x100000>;
			no-map;
			phandle = <0x5e>;
		};

		r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa2100000 0x0 0xf00000>;
			no-map;
			phandle = <0x5f>;
		};

		r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa3000000 0x0 0x100000>;
			no-map;
			phandle = <0x63>;
		};

		r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa3100000 0x0 0xf00000>;
			no-map;
			phandle = <0x64>;
		};

		r5f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa4000000 0x0 0x100000>;
			no-map;
			phandle = <0x67>;
		};

		r5f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa4100000 0x0 0xf00000>;
			no-map;
			phandle = <0x68>;
		};

		r5f-dma-memory@a5000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa5000000 0x0 0x100000>;
			no-map;
			phandle = <0x6a>;
		};

		r5f-memory@a5100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa5100000 0x0 0xf00000>;
			no-map;
			phandle = <0x6b>;
		};

		c66-dma-memory@a6000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa6000000 0x0 0x100000>;
			no-map;
			phandle = <0x71>;
		};

		c66-memory@a6100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa6100000 0x0 0xf00000>;
			no-map;
			phandle = <0x6f>;
		};

		c66-dma-memory@a7000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa7000000 0x0 0x100000>;
			no-map;
			phandle = <0x6e>;
		};

		c66-memory@a7100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa7100000 0x0 0xf00000>;
			no-map;
			phandle = <0x72>;
		};

		c71-dma-memory@a8000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa8000000 0x0 0x100000>;
			no-map;
			phandle = <0x75>;
		};

		c71-memory@a8100000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xa8100000 0x0 0xf00000>;
			no-map;
			phandle = <0x76>;
		};

		ipc-memories@aa000000 {
			reg = <0x0 0xaa000000 0x0 0x1c00000>;
			alignment = <0x1000>;
			no-map;
			phandle = <0x156>;
		};

		r5f-virtual-eth-queues@ac000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xac000000 0x0 0x200000>;
			no-map;
			phandle = <0x60>;
		};

		r5f-virtual-eth-buffers@ac200000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xac200000 0x0 0x1e00000>;
			no-map;
			phandle = <0x61>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <0x7f 0x80>;
		phandle = <0x157>;

		sw10 {
			label = "GPIO Key USER1";
			linux,code = <0x100>;
			gpios = <0x81 0x0 0x1>;
			phandle = <0x158>;
		};

		sw11 {
			label = "GPIO Key USER2";
			linux,code = <0x101>;
			gpios = <0x82 0x7 0x1>;
			phandle = <0x159>;
		};
	};

	fixedregulator-evm12v0 {
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x83>;
	};

	fixedregulator-vsys3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0x83>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x54>;
	};

	fixedregulator-vsys5v0 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x83>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x55>;
	};

	fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <0x54>;
		phandle = <0x4a>;
	};

	gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <0x84>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-boot-on;
		vin-supply = <0x55>;
		states = <0x325aa0 0x0 0x325aa0 0x1>;
		phandle = <0x4b>;
	};

	sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";
		ti,cpb-mcasp = <0x85>;
		ti,cpb-codec = <0x86>;
		clocks = <0x9 0xb8 0x1 0x9 0xb8 0x2 0x9 0xb8 0x4 0x9 0x9d 0x173 0x9 0x9d 0x190 0x9 0x9d 0x191>;
		clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", "cpb-codec-scki", "cpb-codec-scki-48000", "cpb-codec-scki-44100";
		phandle = <0x15a>;
	};

	fixedregulator-dp-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		enable-active-high;
		regulator-always-on;
		phandle = <0x87>;
	};

	connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <0x87>;
		phandle = <0x15b>;

		port {

			endpoint {
				remote-endpoint = <0x88>;
				phandle = <0x59>;
			};
		};
	};

	__symbols__ {
		cluster0 = "/cpus/cpu-map/cluster0";
		cpu0 = "/cpus/cpu@0";
		cpu1 = "/cpus/cpu@1";
		L2_0 = "/l2-cache0";
		msmc_l3 = "/l3-cache0";
		psci = "/firmware/psci";
		a72_timer0 = "/timer-cl0-cpu0";
		pmu = "/pmu";
		cbass_main = "/bus@100000";
		cbass_mcu_wakeup = "/bus@100000/bus@28380000";
		dmsc = "/bus@100000/bus@28380000/dmsc@44083000";
		k3_pds = "/bus@100000/bus@28380000/dmsc@44083000/power-controller";
		k3_clks = "/bus@100000/bus@28380000/dmsc@44083000/clocks";
		k3_reset = "/bus@100000/bus@28380000/dmsc@44083000/reset-controller";
		mcu_conf = "/bus@100000/bus@28380000/syscon@40f00000";
		phy_gmii_sel = "/bus@100000/bus@28380000/syscon@40f00000/phy@4040";
		wkup_pmx0 = "/bus@100000/bus@28380000/pinctrl@4301c000";
		wkup_i2c0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/wkup-i2c0-pins-default";
		mcu_fss0_ospi0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-ospi0-pins-default";
		sw11_button_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/sw11-button-pins-default";
		mcu_fss0_ospi1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-fss0-ospi1-pins-default";
		mcu_cpsw_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-cpsw-pins-default";
		mcu_mdio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mdio1-pins-default";
		mcu_mcan0_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-pins-default";
		mcu_mcan0_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan0-gpio-pins-default";
		mcu_mcan1_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-pins-default";
		mcu_mcan1_gpio_pins_default = "/bus@100000/bus@28380000/pinctrl@4301c000/mcu-mcan1-gpio-pins-default";
		mcu_ram = "/bus@100000/bus@28380000/sram@41c00000";
		wkup_uart0 = "/bus@100000/bus@28380000/serial@42300000";
		mcu_uart0 = "/bus@100000/bus@28380000/serial@40a00000";
		wkup_gpio_intr = "/bus@100000/bus@28380000/interrupt-controller2";
		wkup_gpio0 = "/bus@100000/bus@28380000/gpio@42110000";
		wkup_gpio1 = "/bus@100000/bus@28380000/gpio@42100000";
		mcu_i2c0 = "/bus@100000/bus@28380000/i2c@40b00000";
		mcu_i2c1 = "/bus@100000/bus@28380000/i2c@40b10000";
		wkup_i2c0 = "/bus@100000/bus@28380000/i2c@42120000";
		fss = "/bus@100000/bus@28380000/fss@47000000";
		ospi0 = "/bus@100000/bus@28380000/fss@47000000/spi@47040000";
		ospi1 = "/bus@100000/bus@28380000/fss@47000000/spi@47050000";
		tscadc0 = "/bus@100000/bus@28380000/tscadc@40200000";
		tscadc1 = "/bus@100000/bus@28380000/tscadc@40210000";
		mcu_ringacc = "/bus@100000/bus@28380000/mcu-navss/ringacc@2b800000";
		mcu_udmap = "/bus@100000/bus@28380000/mcu-navss/dma-controller@285c0000";
		mcu_cpsw = "/bus@100000/bus@28380000/ethernet@46000000";
		cpsw_port1 = "/bus@100000/bus@28380000/ethernet@46000000/ethernet-ports/port@1";
		davinci_mdio = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00";
		phy0 = "/bus@100000/bus@28380000/ethernet@46000000/mdio@f00/ethernet-phy@0";
		mcu_r5fss0 = "/bus@100000/bus@28380000/r5fss@41000000";
		mcu_r5fss0_core0 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41000000";
		mcu_r5fss0_core1 = "/bus@100000/bus@28380000/r5fss@41000000/r5f@41400000";
		mcu_mcan0 = "/bus@100000/bus@28380000/can@40528000";
		mcu_mcan1 = "/bus@100000/bus@28380000/can@40568000";
		main_spi0 = "/bus@100000/spi@2100000";
		main_spi1 = "/bus@100000/spi@2110000";
		msmc_ram = "/bus@100000/sram@70000000";
		scm_conf = "/bus@100000/scm-conf@100000";
		serdes_ln_ctrl = "/bus@100000/scm-conf@100000/mux@4080";
		cpsw0_phy_gmii_sel = "/bus@100000/scm-conf@100000/phy@4044";
		usb_serdes_mux = "/bus@100000/scm-conf@100000/mux-controller@4000";
		ehrpwm_tbclk = "/bus@100000/scm-conf@100000/clock@4140";
		main_ehrpwm0 = "/bus@100000/pwm@3000000";
		main_ehrpwm1 = "/bus@100000/pwm@3010000";
		main_ehrpwm2 = "/bus@100000/pwm@3020000";
		main_ehrpwm3 = "/bus@100000/pwm@3030000";
		main_ehrpwm4 = "/bus@100000/pwm@3040000";
		main_ehrpwm5 = "/bus@100000/pwm@3050000";
		gic500 = "/bus@100000/interrupt-controller@1800000";
		gic_its = "/bus@100000/interrupt-controller@1800000/msi-controller@1820000";
		main_gpio_intr = "/bus@100000/interrupt-controller0";
		main_navss_intr = "/bus@100000/main-navss/interrupt-controller1";
		main_udmass_inta = "/bus@100000/main-navss/interrupt-controller@33d00000";
		secure_proxy_main = "/bus@100000/main-navss/mailbox@32c00000";
		smmu0 = "/bus@100000/main-navss/iommu@36600000";
		hwspinlock = "/bus@100000/main-navss/spinlock@30e00000";
		mailbox0_cluster0 = "/bus@100000/main-navss/mailbox@31f80000";
		mbox_mcu_r5fss0_core0 = "/bus@100000/main-navss/mailbox@31f80000/mbox-mcu-r5fss0-core0";
		mbox_mcu_r5fss0_core1 = "/bus@100000/main-navss/mailbox@31f80000/mbox-mcu-r5fss0-core1";
		mailbox0_cluster1 = "/bus@100000/main-navss/mailbox@31f81000";
		mbox_main_r5fss0_core0 = "/bus@100000/main-navss/mailbox@31f81000/mbox-main-r5fss0-core0";
		mbox_main_r5fss0_core1 = "/bus@100000/main-navss/mailbox@31f81000/mbox-main-r5fss0-core1";
		mailbox0_cluster2 = "/bus@100000/main-navss/mailbox@31f82000";
		mbox_main_r5fss1_core0 = "/bus@100000/main-navss/mailbox@31f82000/mbox-main-r5fss1-core0";
		mbox_main_r5fss1_core1 = "/bus@100000/main-navss/mailbox@31f82000/mbox-main-r5fss1-core1";
		mailbox0_cluster3 = "/bus@100000/main-navss/mailbox@31f83000";
		mbox_c66_0 = "/bus@100000/main-navss/mailbox@31f83000/mbox-c66-0";
		mbox_c66_1 = "/bus@100000/main-navss/mailbox@31f83000/mbox-c66-1";
		mailbox0_cluster4 = "/bus@100000/main-navss/mailbox@31f84000";
		mbox_c71_0 = "/bus@100000/main-navss/mailbox@31f84000/mbox-c71-0";
		mailbox0_cluster5 = "/bus@100000/main-navss/mailbox@31f85000";
		mailbox0_cluster6 = "/bus@100000/main-navss/mailbox@31f86000";
		mailbox0_cluster7 = "/bus@100000/main-navss/mailbox@31f87000";
		mailbox0_cluster8 = "/bus@100000/main-navss/mailbox@31f88000";
		mailbox0_cluster9 = "/bus@100000/main-navss/mailbox@31f89000";
		mailbox0_cluster10 = "/bus@100000/main-navss/mailbox@31f8a000";
		mailbox0_cluster11 = "/bus@100000/main-navss/mailbox@31f8b000";
		main_ringacc = "/bus@100000/main-navss/ringacc@3c000000";
		main_udmap = "/bus@100000/main-navss/dma-controller@31150000";
		cpsw0 = "/bus@100000/ethernet@c000000";
		cpsw0_port1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
		cpsw0_port2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
		cpsw0_port3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
		cpsw0_port4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
		cpsw0_port5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
		cpsw0_port6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
		cpsw0_port7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
		cpsw0_port8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
		cpsw9g_mdio = "/bus@100000/ethernet@c000000/mdio@f00";
		main_crypto = "/bus@100000/crypto@4e00000";
		rng = "/bus@100000/crypto@4e00000/rng@4e10000";
		main_pmx0 = "/bus@100000/pinctrl@11c000";
		spi0_pins_default = "/bus@100000/pinctrl@11c000/spi0_pins_default";
		spi1_pins_default = "/bus@100000/pinctrl@11c000/spi1_pins_default";
		sw10_button_pins_default = "/bus@100000/pinctrl@11c000/sw10-button-pins-default";
		main_mmc1_pins_default = "/bus@100000/pinctrl@11c000/main-mmc1-pins-default";
		vdd_sd_dv_alt_pins_default = "/bus@100000/pinctrl@11c000/vdd-sd-dv-alt-pins-default";
		main_usbss0_pins_default = "/bus@100000/pinctrl@11c000/main-usbss0-pins-default";
		main_usbss1_pins_default = "/bus@100000/pinctrl@11c000/main-usbss1-pins-default";
		dp0_pins_default = "/bus@100000/pinctrl@11c000/dp0-pins-default";
		main_i2c0_pins_default = "/bus@100000/pinctrl@11c000/main-i2c0-pins-default";
		main_i2c1_pins_default = "/bus@100000/pinctrl@11c000/main-i2c1-pins-default";
		main_i2c3_pins_default = "/bus@100000/pinctrl@11c000/main-i2c3-pins-default";
		mcasp0_pins_default = "/bus@100000/pinctrl@11c000/mcasp0-pins-default";
		audi_ext_refclk2_pins_default = "/bus@100000/pinctrl@11c000/audi-ext-refclk2-pins-default";
		main_mcan0_pins_default = "/bus@100000/pinctrl@11c000/main-mcan0-pins-default";
		main_mcan2_pins_default = "/bus@100000/pinctrl@11c000/main-mcan2-pins-default";
		main_mcan2_gpio_pins_default = "/bus@100000/pinctrl@11c000/main-mcan2-gpio-pins-default";
		serdes_wiz0 = "/bus@100000/wiz@5000000";
		wiz0_pll0_refclk = "/bus@100000/wiz@5000000/pll0-refclk";
		wiz0_pll1_refclk = "/bus@100000/wiz@5000000/pll1-refclk";
		wiz0_refclk_dig = "/bus@100000/wiz@5000000/refclk-dig";
		wiz0_cmn_refclk_dig_div = "/bus@100000/wiz@5000000/cmn-refclk-dig-div";
		wiz0_cmn_refclk1_dig_div = "/bus@100000/wiz@5000000/cmn-refclk1-dig-div";
		serdes0 = "/bus@100000/wiz@5000000/serdes@5000000";
		serdes_wiz1 = "/bus@100000/wiz@5010000";
		wiz1_pll0_refclk = "/bus@100000/wiz@5010000/pll0-refclk";
		wiz1_pll1_refclk = "/bus@100000/wiz@5010000/pll1-refclk";
		wiz1_refclk_dig = "/bus@100000/wiz@5010000/refclk-dig";
		wiz1_cmn_refclk_dig_div = "/bus@100000/wiz@5010000/cmn-refclk-dig-div";
		wiz1_cmn_refclk1_dig_div = "/bus@100000/wiz@5010000/cmn-refclk1-dig-div";
		serdes1 = "/bus@100000/wiz@5010000/serdes@5010000";
		serdes_wiz2 = "/bus@100000/wiz@5020000";
		wiz2_pll0_refclk = "/bus@100000/wiz@5020000/pll0-refclk";
		wiz2_pll1_refclk = "/bus@100000/wiz@5020000/pll1-refclk";
		wiz2_refclk_dig = "/bus@100000/wiz@5020000/refclk-dig";
		wiz2_cmn_refclk_dig_div = "/bus@100000/wiz@5020000/cmn-refclk-dig-div";
		wiz2_cmn_refclk1_dig_div = "/bus@100000/wiz@5020000/cmn-refclk1-dig-div";
		serdes2 = "/bus@100000/wiz@5020000/serdes@5020000";
		serdes_wiz3 = "/bus@100000/wiz@5030000";
		wiz3_pll0_refclk = "/bus@100000/wiz@5030000/pll0-refclk";
		wiz3_pll1_refclk = "/bus@100000/wiz@5030000/pll1-refclk";
		wiz3_refclk_dig = "/bus@100000/wiz@5030000/refclk-dig";
		wiz3_cmn_refclk_dig_div = "/bus@100000/wiz@5030000/cmn-refclk-dig-div";
		wiz3_cmn_refclk1_dig_div = "/bus@100000/wiz@5030000/cmn-refclk1-dig-div";
		serdes3 = "/bus@100000/wiz@5030000/serdes@5030000";
		serdes3_usb_link = "/bus@100000/wiz@5030000/serdes@5030000/phy@0";
		pcie0_rc = "/bus@100000/pcie@2900000";
		pcie0_intc = "/bus@100000/pcie@2900000/interrupt-controller";
		pcie0_ep = "/bus@100000/pcie-ep@2900000";
		pcie1_rc = "/bus@100000/pcie@2910000";
		pcie1_intc = "/bus@100000/pcie@2910000/interrupt-controller";
		pcie1_ep = "/bus@100000/pcie-ep@2910000";
		pcie2_rc = "/bus@100000/pcie@2920000";
		pcie2_intc = "/bus@100000/pcie@2920000/interrupt-controller";
		pcie2_ep = "/bus@100000/pcie-ep@2920000";
		pcie3_rc = "/bus@100000/pcie@2930000";
		pcie3_intc = "/bus@100000/pcie@2930000/interrupt-controller";
		pcie3_ep = "/bus@100000/pcie-ep@2930000";
		serdes_wiz4 = "/bus@100000/wiz@5050000";
		wiz4_pll0_refclk = "/bus@100000/wiz@5050000/pll0-refclk";
		wiz4_pll1_refclk = "/bus@100000/wiz@5050000/pll1-refclk";
		wiz4_refclk_dig = "/bus@100000/wiz@5050000/refclk-dig";
		wiz4_cmn_refclk_dig_div = "/bus@100000/wiz@5050000/cmn-refclk-dig-div";
		wiz4_cmn_refclk1_dig_div = "/bus@100000/wiz@5050000/cmn-refclk1-dig-div";
		serdes4 = "/bus@100000/wiz@5050000/serdes@5050000";
		torrent_phy_dp = "/bus@100000/wiz@5050000/serdes@5050000/phy@0";
		main_uart0 = "/bus@100000/serial@2800000";
		main_uart1 = "/bus@100000/serial@2810000";
		main_uart2 = "/bus@100000/serial@2820000";
		main_uart3 = "/bus@100000/serial@2830000";
		main_uart4 = "/bus@100000/serial@2840000";
		main_uart5 = "/bus@100000/serial@2850000";
		main_uart6 = "/bus@100000/serial@2860000";
		main_uart7 = "/bus@100000/serial@2870000";
		main_uart8 = "/bus@100000/serial@2880000";
		main_uart9 = "/bus@100000/serial@2890000";
		main_gpio0 = "/bus@100000/gpio@600000";
		main_gpio1 = "/bus@100000/gpio@601000";
		main_gpio2 = "/bus@100000/gpio@610000";
		main_gpio3 = "/bus@100000/gpio@611000";
		main_gpio4 = "/bus@100000/gpio@620000";
		main_gpio5 = "/bus@100000/gpio@621000";
		main_gpio6 = "/bus@100000/gpio@630000";
		main_gpio7 = "/bus@100000/gpio@631000";
		main_sdhci0 = "/bus@100000/mmc@4f80000";
		main_sdhci1 = "/bus@100000/mmc@4fb0000";
		main_sdhci2 = "/bus@100000/mmc@4f98000";
		usbss0 = "/bus@100000/cdns-usb@4104000";
		usb0 = "/bus@100000/cdns-usb@4104000/usb@6000000";
		usbss1 = "/bus@100000/cdns-usb@4114000";
		usb1 = "/bus@100000/cdns-usb@4114000/usb@6400000";
		main_i2c0 = "/bus@100000/i2c@2000000";
		exp1 = "/bus@100000/i2c@2000000/gpio@20";
		exp2 = "/bus@100000/i2c@2000000/gpio@22";
		main_i2c1 = "/bus@100000/i2c@2010000";
		main_i2c2 = "/bus@100000/i2c@2020000";
		main_i2c3 = "/bus@100000/i2c@2030000";
		exp3 = "/bus@100000/i2c@2030000/gpio@20";
		pcm3168a_1 = "/bus@100000/i2c@2030000/audio-codec@44";
		main_i2c4 = "/bus@100000/i2c@2040000";
		main_i2c5 = "/bus@100000/i2c@2050000";
		main_i2c6 = "/bus@100000/i2c@2060000";
		d5520 = "/bus@100000/video-decoder@4300000";
		vxe384 = "/bus@100000/video-encoder@4200000";
		ufs_wrapper = "/bus@100000/ufs-wrapper@4e80000";
		mhdp = "/bus@100000/dp-bridge@a000000";
		dp0_ports = "/bus@100000/dp-bridge@a000000/ports";
		dp0_in = "/bus@100000/dp-bridge@a000000/ports/port@0/endpoint";
		dp0_out = "/bus@100000/dp-bridge@a000000/ports/port@4/endpoint";
		dss = "/bus@100000/dss@4a00000";
		dss_ports = "/bus@100000/dss@4a00000/ports";
		dpi0_out = "/bus@100000/dss@4a00000/ports/port@0/endpoint";
		mcasp0 = "/bus@100000/mcasp@2b00000";
		mcasp1 = "/bus@100000/mcasp@2b10000";
		mcasp2 = "/bus@100000/mcasp@2b20000";
		mcasp3 = "/bus@100000/mcasp@2b30000";
		mcasp4 = "/bus@100000/mcasp@2b40000";
		mcasp5 = "/bus@100000/mcasp@2b50000";
		mcasp6 = "/bus@100000/mcasp@2b60000";
		mcasp7 = "/bus@100000/mcasp@2b70000";
		mcasp8 = "/bus@100000/mcasp@2b80000";
		mcasp9 = "/bus@100000/mcasp@2b90000";
		mcasp10 = "/bus@100000/mcasp@2ba0000";
		mcasp11 = "/bus@100000/mcasp@2bb0000";
		watchdog0 = "/bus@100000/watchdog@2200000";
		watchdog1 = "/bus@100000/watchdog@2210000";
		main_r5fss0 = "/bus@100000/r5fss@5c00000";
		main_r5fss0_core0 = "/bus@100000/r5fss@5c00000/r5f@5c00000";
		main_r5fss0_core1 = "/bus@100000/r5fss@5c00000/r5f@5d00000";
		main_r5fss1 = "/bus@100000/r5fss@5e00000";
		main_r5fss1_core0 = "/bus@100000/r5fss@5e00000/r5f@5e00000";
		main_r5fss1_core1 = "/bus@100000/r5fss@5e00000/r5f@5f00000";
		c66_0 = "/bus@100000/dsp@4d80800000";
		c66_1 = "/bus@100000/dsp@4d81800000";
		c71_0 = "/bus@100000/dsp@64800000";
		icssg0 = "/bus@100000/icssg@b000000";
		icssg0_mem = "/bus@100000/icssg@b000000/memories@0";
		icssg0_cfg = "/bus@100000/icssg@b000000/cfg@26000";
		icssg0_coreclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/coreclk-mux@3c";
		icssg0_iepclk_mux = "/bus@100000/icssg@b000000/cfg@26000/clocks/iepclk-mux@30";
		icssg0_iep0 = "/bus@100000/icssg@b000000/iep@2e000";
		icssg0_iep1 = "/bus@100000/icssg@b000000/iep@2f000";
		icssg0_mii_rt = "/bus@100000/icssg@b000000/mii-rt@32000";
		icssg0_mii_g_rt = "/bus@100000/icssg@b000000/mii-g-rt@33000";
		icssg0_intc = "/bus@100000/icssg@b000000/interrupt-controller@20000";
		pru0_0 = "/bus@100000/icssg@b000000/pru@34000";
		rtu0_0 = "/bus@100000/icssg@b000000/rtu@4000";
		tx_pru0_0 = "/bus@100000/icssg@b000000/txpru@a000";
		pru0_1 = "/bus@100000/icssg@b000000/pru@38000";
		rtu0_1 = "/bus@100000/icssg@b000000/rtu@6000";
		tx_pru0_1 = "/bus@100000/icssg@b000000/txpru@c000";
		icssg0_mdio = "/bus@100000/icssg@b000000/mdio@32400";
		icssg1 = "/bus@100000/icssg@b100000";
		icssg1_mem = "/bus@100000/icssg@b100000/memories@b100000";
		icssg1_cfg = "/bus@100000/icssg@b100000/cfg@26000";
		icssg1_coreclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/coreclk-mux@3c";
		icssg1_iepclk_mux = "/bus@100000/icssg@b100000/cfg@26000/clocks/iepclk-mux@30";
		icssg1_iep0 = "/bus@100000/icssg@b100000/iep@2e000";
		icssg1_iep1 = "/bus@100000/icssg@b100000/iep@2f000";
		icssg1_mii_rt = "/bus@100000/icssg@b100000/mii-rt@32000";
		icssg1_mii_g_rt = "/bus@100000/icssg@b100000/mii-g-rt@33000";
		icssg1_intc = "/bus@100000/icssg@b100000/interrupt-controller@20000";
		pru1_0 = "/bus@100000/icssg@b100000/pru@34000";
		rtu1_0 = "/bus@100000/icssg@b100000/rtu@4000";
		tx_pru1_0 = "/bus@100000/icssg@b100000/txpru@a000";
		pru1_1 = "/bus@100000/icssg@b100000/pru@38000";
		rtu1_1 = "/bus@100000/icssg@b100000/rtu@6000";
		tx_pru1_1 = "/bus@100000/icssg@b100000/txpru@c000";
		icssg1_mdio = "/bus@100000/icssg@b100000/mdio@32400";
		timesync_router = "/bus@100000/timesync_router@A40000";
		gpu = "/bus@100000/gpu@4e20000000";
		main_mcan0 = "/bus@100000/can@2701000";
		main_mcan1 = "/bus@100000/can@2711000";
		main_mcan2 = "/bus@100000/can@2721000";
		main_mcan3 = "/bus@100000/can@2731000";
		main_mcan4 = "/bus@100000/can@2741000";
		main_mcan5 = "/bus@100000/can@2751000";
		main_mcan6 = "/bus@100000/can@2761000";
		main_mcan7 = "/bus@100000/can@2771000";
		main_mcan8 = "/bus@100000/can@2781000";
		main_mcan9 = "/bus@100000/can@2791000";
		main_mcan10 = "/bus@100000/can@27a1000";
		main_mcan11 = "/bus@100000/can@27b1000";
		main_mcan12 = "/bus@100000/can@27c1000";
		main_mcan13 = "/bus@100000/can@27d1000";
		ti_csi2rx0 = "/bus@100000/ticsi2rx@4500000";
		cdns_csi2rx0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000";
		csi0_port0 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@0";
		csi0_port1 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@1";
		csi0_port2 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@2";
		csi0_port3 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@3";
		csi0_port4 = "/bus@100000/ticsi2rx@4500000/csi-bridge@4504000/ports/port@4";
		ti_csi2rx1 = "/bus@100000/ticsi2rx@4510000";
		cdns_csi2rx1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000";
		csi1_port0 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@0";
		csi1_port1 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@1";
		csi1_port2 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@2";
		csi1_port3 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@3";
		csi1_port4 = "/bus@100000/ticsi2rx@4510000/csi-bridge@4514000/ports/port@4";
		dphy0 = "/bus@100000/phy@4580000";
		dphy1 = "/bus@100000/phy@4590000";
		cmn_refclk = "/clock-cmnrefclk";
		cmn_refclk1 = "/clock-cmnrefclk1";
		reserved_memory = "/reserved-memory";
		secure_ddr = "/reserved-memory/optee@9e800000";
		mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";
		mcu_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";
		mcu_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a1000000";
		mcu_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a1100000";
		main_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a2000000";
		main_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a2100000";
		main_r5fss0_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a3000000";
		main_r5fss0_core1_memory_region = "/reserved-memory/r5f-memory@a3100000";
		main_r5fss1_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a4000000";
		main_r5fss1_core0_memory_region = "/reserved-memory/r5f-memory@a4100000";
		main_r5fss1_core1_dma_memory_region = "/reserved-memory/r5f-dma-memory@a5000000";
		main_r5fss1_core1_memory_region = "/reserved-memory/r5f-memory@a5100000";
		c66_1_dma_memory_region = "/reserved-memory/c66-dma-memory@a6000000";
		c66_0_memory_region = "/reserved-memory/c66-memory@a6100000";
		c66_0_dma_memory_region = "/reserved-memory/c66-dma-memory@a7000000";
		c66_1_memory_region = "/reserved-memory/c66-memory@a7100000";
		c71_0_dma_memory_region = "/reserved-memory/c71-dma-memory@a8000000";
		c71_0_memory_region = "/reserved-memory/c71-memory@a8100000";
		rtos_ipc_memory_region = "/reserved-memory/ipc-memories@aa000000";
		main_r5fss0_core0_shared_memory_queue_region = "/reserved-memory/r5f-virtual-eth-queues@ac000000";
		main_r5fss0_core0_shared_memory_bufpool_region = "/reserved-memory/r5f-virtual-eth-buffers@ac200000";
		gpio_keys = "/gpio-keys";
		sw10 = "/gpio-keys/sw10";
		sw11 = "/gpio-keys/sw11";
		evm_12v0 = "/fixedregulator-evm12v0";
		vsys_3v3 = "/fixedregulator-vsys3v3";
		vsys_5v0 = "/fixedregulator-vsys5v0";
		vdd_mmc1 = "/fixedregulator-sd";
		vdd_sd_dv_alt = "/gpio-regulator-TLV71033";
		sound0 = "/sound@0";
		dp_pwr_3v3 = "/fixedregulator-dp-prw";
		dp0 = "/connector";
		dp_connector_in = "/connector/port/endpoint";
	};
};

Please help to check, thank you very much!!

Best Regards,

Shawn

Hello Sudheer,

I switched to J7 SDK version 8.6, then the issue was solved.

Thank you for your help and instructions!

Best Regards,

Shawn