TDA4VM: SDL_RTI example

Hi Shine,

Shine said:

Customer is using TDA4VM ECO device. He is running SDL examples/rti/UC1 example in ti-processor-sdk-rtos-j721s2-evm-08_06_01_03.

If you are using the TDA4VM device, you must use the ti-processor-sdk-rtos-j721e-evm-08_06_01_03 SDK. 

Shine said:

Enable watchdog, the watchdog timer doesn't exceed 10s, but the WD is triggered. It prompted "RTI DWWD proper servicing test failed." 

Is this just the standard standalone SDL example or has the customer made any changes?

Regards,

Josiitaa

Hi:

I am using TDA4VE88TGAALZRQ1 device.

This is the standard standalone SDL example，I did not modify the code。

Hi,

Shine said:

Have TI tested the example?

These are the test logs from TI validation:

RTI Example Test Application

RTI_Test_init: Init MCU ESM complete

RTI Example code UC-1 started
DWWD configured to 100 percent window size
DWWD is configured for 10000 ms time-out

RTI DWWD proper servicing test running.
Please wait for max 10000 ms.

RTI DWWD proper s
  Interrupt is generated to ESM
ESM Call back function called : instType 0x2, intType 0x1, grpChannel 0x3, index 0x8, intSrc 0x68
  Take action
ervicing test successful.


RTI permanent failure test running.
DWWD will generate interrupt after 10 seconds
Wait for 10 sec for interrupt to be generated by DWWD.

RTI Window End time violation test successful.

Test Name: RTI EXAMPLE TEST PASSED

 All tests have passed.

Regards,

Josiitaa

As shown in the log provided by TI, why did an interrupt occur?

Hi,

The interrupt is being triggered as a part of the example test case.

Please refer to the following user guides about the RTI module and example test case scenarios:

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j721s2/08_06_01_03/exports/docs/sdl/sdl_docs/userguide/j721s2/modules/rti.html

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j721s2/08_06_01_03/exports/docs/sdl/sdl_docs/userguide/j721s2/examples/rti.html

Regards,

Josiitaa

Hi:

    The log in the following link you provided is shown in the figure below, but it did not trigger an interrupt event.Why are the results different from the test logs verified by TI?

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j721s2/08_06_01_03/exports/docs/sdl/sdl_docs/userguide/j721s2/examples/rti.html

Hi,

It seems like the logs for the expected interrupt is printed earlier. I will verify this with the internal experts and get back to you by Friday(Dec-8) EOD.

Regards,

Josiitaa

Look forward to your soonest reply.

Regards

Hi,

1.Can I access this link?  ‘Link for internal tracking: PROC_SDL-7059’

2.Could you please also pay attention to my second question that I initially raised：

Modify the  int32_t SDL_RTI_exampleTest(void) in sdl/examples/rti/UC1/sdl_rti_example.c as below

pConfig.SDL_RTI_dwwdReaction   = RTI_DWWD_REACTION_GENERATE_NMI;------->pConfig.SDL_RTI_dwwdReaction   = RTI_DWWD_REACTION_GENERATE_RESET;

The mcu is not reset. 

Configure pConfig.SDL_RTI_dwwdReaction   = RTI_DWWD_REACTION_GENERATE_RESET; will the watchdog reset the MCU? Is there some configurations missed?

Thanks.

Hi,

zhangjun1 said:

Can I access this link?  ‘Link for internal tracking: PROC_SDL-7059’

This link is meant for TI's internal tracking purpose. The development team is working on fixing the issue. If any updates, I shall let you know.

zhangjun1 said:

.Could you please also pay attention to my second question that I initially raised：

I will check with the internal team and provide an update by mid of next week.

Regards,

Josiitaa

Look forward to your soonest reply.

Regards

Hi,

The RTI does not reset SOC, it just gives interrupt and how to handle this interrupt, its up to the code. When RTI counter expires, an ESM event is triggered. So, one option is that SOC reset can be generated by using ESM error pin for this error event from RTI. External monitor can do the reset based on the error pin.

If you are looking at resetting the SoC from SW on MCU R5F when you get the interrupt, you can use this TISCI API.

https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html#tisci-msg-sys-reset 

You can reset just the MAIN domain or the full SoC using this API.

Regards,

Josiitaa

Hi,

The RTI does not reset SOC, what is the difference between  ‘pConfig.SDL_RTI_dwwdReaction = RTI_DWWD_REACTION_GENERATE_RESET’ and  ‘pConfig.SDL_RTI_dwwdReaction = RTI_DWWD_REACTION_GENERATE_NMI’?

Hi,

We have the macro defined for both RTI_DWWD_REACTION_GENERATE_RESET and RTI_DWWD_REACTION_GENERATE_NMI, but only interrupt generation is validated as per metadata received from IP team. If you wish to reset the SOC, you will have to do it as a part of the ESM error monitoring feature.

Regards,

Josiitaa

Hi,

Thank you, due to your guidance, I have learned how to reset the chip. Currently, my question is what  the difference between  ‘pConfig.SDL_RTI_dwwdReaction = RTI_DWWD_REACTION_GENERATE_RESET’ and  ‘pConfig.SDL_RTI_dwwdReaction = RTI_DWWD_REACTION_GENERATE_NMI’ is? What is the purpose of defining RTI_DWWD_REACTION_GENERATE_RESET by the TI team?

Hi,

The RTI_DWWD_REACTION_GENERATE_RESET is merely just a macro defined in the metadata. The RTI_DWWD_REACTION_GENERATE_NMI (Non Masked Interrupt) is what is being used throughout the code. You can verify the configuration APIs in SDL where only RTI_DWWD_REACTION_GENERATE_NMI is used.

Regards,

Josiitaa

Hi,

I can understand that RTI_DWWD_REACTION_GENERATE_RESET  is useless, right?

Yes, it has not been implemented in the code sequence.

Regards,

Josiitaa

Hi，

thank you. Have you made any progress with the “Link for internal tracking: PROC_SDL-7059”you mentioned earlier?

Hi, 

The development team is still looking into it. I will post an update if there are any findings.

Regards,

Josiitaa

Is there a temporary measure in version 08.06 that can solve this bug at present?

Hi,

The development team is still looking into issue. There is not fix available as of now.

Regards,

Josiitaa