TDA4VM: DSI Display exception with 1280*800

Hi Gary,

Sorry what's the exception that you are seeing? 

Also are the pixel clock and lane speed setup correctly ? It shows only 7.5fps with display node taking around 58ms to display a frame.. 

Regards,

Brijesh

Hi Brijesh,

I modified the timing, and I can initially see the image, but the image is not clear.

This is my latest config and TIDL output:

dsi_params.numOfLanes = 4;
dsi_params.laneSpeedInKbps = 464880U;

1.Is this related to the color mode? How do I change the color mode in TIDL so that it displays properly?

2. Why is my output only 7.5FPS? How should I adjust the TIDL_demo code to output 60FPS?

please tell me thank you ,Looking forward to your reply

Regards,

Barry

Hi Brigesh,

How should we solve this abnormal display problem? Please give us support. We look forward to your reply.

Regards,

Barry

Hi Barry,

Are you sure that input images are correctly read in the demo? Because it looks like the only the input images are incorrect. TI logo and other text seems to be correct. So doubting on the input images. 

Regards,

Brijesh

Hi Brigesh

I did not change the input image of TIDL demo.

I have not changed the input image under test_data. My modifications to the DSI output are listed above. We now suspect that the TIDL output does not match the screen color mode. The LVDS interface of this screen is VESA24. How should I change the color mode in TIDL? ?

Please support us in solving this problem and look forward to your quick reply, thank you

Regards,

Barry

Hi Barry,

Is there any other demo, which can be enabled here? I dont think this is related to VESA24 format, but it might be input color format issue. So wondering if any other demo is working fine. Lets say do you have input camera, then can you check single camera demo? 

Regards,

Brijesh

Hi Brigesh，

As with the modifications I provided above, we verified that only the output resolution of TIDL was modified, and other TIDL codes were not modified. Unfortunately, we do not have a camera and can only verify the demo output;

In addition, I did a test. When I changed the photo under test_data/psdkra/app_tidl/ to a 16-bit color bmp image, the LCD display was consistent with the original image under test_data. It can be determined that the color mode caused this problem. Do we need to change the output format of TIDL? Can you tell me how to change it now?

Looking forward to your reply.

Regards,

Barry

Hi Brigesh，

We want to output TIDL demo in RGB565, what should we do? Can you reply to us? Thanks

Regards,

Barry

Hi Barry,

Did not get it. Have you changed TIDL output format already? or input images for this demo? Is the original demo working fine? 

Which exactly binary that you are running? Can you please share it? 

Regards,

Brijesh  

1.No changes! The TIDL output format and input image have not been changed!

2.When we run ./run_app_tidl.sh, the output image displays abnormally. I suspect it is a color mode problem. Can you directly tell me how to solve this problem? ?

My output when neither the TIDL output format nor the input image has been changed:

root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]      3.866388 s: CIO: Init ... Done !!!
[MCU2_0]      3.866459 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      3.866501 s: CPU is running FreeRTOS
[MCU2_0]      3.866527 s: APP: Init ... !!!
[MCU2_0]      3.866550 s: SCICLIENT: Init ... !!!
[MCU2_0]      3.866798 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]      3.866847 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]      3.866880 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      3.866918 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      3.866946 s: UDMA: Init ... !!!
[MCU2_0]      3.868261 s: UDMA: Init ... Done !!!
[MCU2_0]      3.868322 s: MEM: Init ... !!!
[MCU2_0]      3.868367 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
[MCU2_0]      3.868443 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]      3.868505 s: MEM: Init ... Done !!!
[MCU2_0]      3.868531 s: IPC: Init ... !!!
[MCU2_0]      3.868589 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]      3.868636 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     13.597598 s: IPC: HLOS is ready !!!
[MCU2_0]     13.612987 s: IPC: Init ... Done !!!
[MCU2_0]     13.613057 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]     13.799959 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]     13.800185 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     13.801728 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     13.801794 s: FVID2: Init ... !!!
[MCU2_0]     13.801866 s: FVID2: Init ... Done !!!
[MCU2_0]     13.801917 s: DSS: Init ... !!!
[MCU2_0]     13.801944 s: DSS: Display type is DSI !!!
[MCU2_0]     13.801972 s: DSS: M2M Path is enabled !!!
[MCU2_0]     13.802000 s: DSS: SoC init ... !!!
[MCU2_0]     13.802024 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]     13.802634 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.802676 s: SCICLIENT: Sciclient_pmSetModuleState module=150 state=2
[MCU2_0]     13.803176 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.803214 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]     13.803746 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.803778 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]     13.804263 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]     13.804300 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=9 freq=77480000
[MCU2_0]     13.805842 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     13.805876 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=9 state=2 flag=0
[MCU2_0]     13.806433 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]     13.806468 s: DSS: SoC init ... Done !!!
[MCU2_0]     13.810198 s: DSS: Init ... Done !!!
[MCU2_0]     13.810268 s: VHWA: VPAC Init ... !!!
[MCU2_0]     13.810297 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]     13.810619 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.810657 s: VHWA: LDC Init ... !!!
[MCU2_0]     13.815744 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     13.815804 s: VHWA: MSC Init ... !!!
[MCU2_0]     13.828480 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     13.828547 s: VHWA: NF Init ... !!!
[MCU2_0]     13.830311 s: VHWA: NF Init ... Done !!!
[MCU2_0]     13.830365 s: VHWA: VISS Init ... !!!
[MCU2_0]     13.840803 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     13.840865 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     13.840911 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     13.840942 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     13.840969 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     13.842361 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]     13.842631 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]     13.842870 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]     13.843138 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]     13.843391 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]     13.843762 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]     13.844039 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]     13.844296 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]     13.844579 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]     13.844848 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]     13.845086 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]     13.845371 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]     13.845636 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]     13.845901 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]     13.846167 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]     13.846449 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]     13.846718 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]     13.846968 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]     13.847202 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]     13.847462 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]     13.847700 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]     13.847761 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     13.847798 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     13.870382 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     13.870441 s: CSI2RX: Init ... !!!
[MCU2_0]     13.870469 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]     13.870612 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.870651 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]     13.870797 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.870829 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]     13.870957 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.870988 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]     13.871081 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.871112 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]     13.871195 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     13.871427 s: CSI2RX: Init ... Done !!!
[MCU2_0]     13.871472 s: ISS: Init ... !!!
[MCU2_0]     13.871506 s: Found sensor IMX390-UB953_D3 at location 0 
[MCU2_0]     13.871547 s: Found sensor AR0233-UB953_MARS at location 1 
[MCU2_0]     13.871584 s: Found sensor AR0820-UB953_LI at location 2 
[MCU2_0]     13.871620 s: Found sensor UB9xxx_RAW12_TESTPATTERN at location 3 
[MCU2_0]     13.871659 s: Found sensor UB96x_UYVY_TESTPATTERN at location 4 
[MCU2_0]     13.871696 s: Found sensor GW_AR0233_UYVY at location 5 
[MCU2_0]     13.871730 s: IssSensor_Init ... Done !!!
[MCU2_0]     13.871806 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     13.871843 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     13.871909 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     13.871942 s: UDMA Copy: Init ... !!!
[MCU2_0]     13.873790 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     13.873891 s: APP: Init ... Done !!!
[MCU2_0]     13.873930 s: APP: Run ... !!!
[MCU2_0]     13.873955 s: IPC: Starting echo test ...
[MCU2_0]     13.876588 s: APP: Run ... Done !!!
[MCU2_0]     13.878115 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.878232 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]     13.878326 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]     13.878410 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]      3.873703 s: CIO: Init ... Done !!!
[MCU2_1]      3.873774 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]      3.873816 s: CPU is running FreeRTOS
[MCU2_1]      3.873842 s: APP: Init ... !!!
[MCU2_1]      3.873864 s: SCICLIENT: Init ... !!!
[MCU2_1]      3.874114 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]      3.874163 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]      3.874214 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]      3.874256 s: SCICLIENT: Init ... Done !!!
[MCU2_1]      3.874285 s: UDMA: Init ... !!!
[MCU2_1]      3.875637 s: UDMA: Init ... Done !!!
[MCU2_1]      3.875698 s: MEM: Init ... !!!
[MCU2_1]      3.875740 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 16777216 bytes !!!
[MCU2_1]      3.875815 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]      3.875876 s: MEM: Init ... Done !!!
[MCU2_1]      3.875902 s: IPC: Init ... !!!
[MCU2_1]      3.875964 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_1]      3.876015 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]     13.784533 s: IPC: HLOS is ready !!!
[MCU2_1]     13.799845 s: IPC: Init ... Done !!!
[MCU2_1]     13.799913 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_1]     13.799958 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_1]     13.799994 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]     13.801755 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]     13.801825 s: FVID2: Init ... !!!
[MCU2_1]     13.801899 s: FVID2: Init ... Done !!!
[MCU2_1]     13.801929 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]     13.801954 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]     13.802314 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.802355 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]     13.802908 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]     13.802950 s: VHWA: DOF Init ... !!!
[MCU2_1]     13.813853 s: VHWA: DOF Init ... Done !!!
[MCU2_1]     13.813917 s: VHWA: SDE Init ... !!!
[MCU2_1]     13.817063 s: VHWA: SDE Init ... Done !!!
[MCU2_1]     13.817128 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]     13.817175 s:  VX_ZONE_INIT:Enabled
[MCU2_1]     13.817208 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]     13.817239 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]     13.818666 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]     13.818926 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]     13.819163 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]     13.819220 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]     13.819256 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]     13.819533 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]     13.819576 s: UDMA Copy: Init ... !!!
[MCU2_1]     13.822174 s: UDMA Copy: Init ... Done !!!
[MCU2_1]     13.822244 s: APP: Init ... Done !!!
[MCU2_1]     13.822279 s: APP: Run ... !!!
[MCU2_1]     13.822305 s: IPC: Starting echo test ...
[MCU2_1]     13.824873 s: APP: Run ... Done !!!
[MCU2_1]     13.826025 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]     13.826139 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]     13.826231 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]     13.877420 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]      3.932054 s: CIO: Init ... Done !!!
[C6x_1 ]      3.932078 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]      3.932087 s: CPU is running FreeRTOS
[C6x_1 ]      3.932095 s: APP: Init ... !!!
[C6x_1 ]      3.932102 s: SCICLIENT: Init ... !!!
[C6x_1 ]      3.932304 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]      3.932316 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]      3.932325 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]      3.932334 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]      3.932344 s: UDMA: Init ... !!!
[C6x_1 ]      3.933842 s: UDMA: Init ... Done !!!
[C6x_1 ]      3.933860 s: MEM: Init ... !!!
[C6x_1 ]      3.933872 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 16777216 bytes !!!
[C6x_1 ]      3.933889 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]      3.933904 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331648 bytes !!!
[C6x_1 ]      3.933920 s: MEM: Init ... Done !!!
[C6x_1 ]      3.933928 s: IPC: Init ... !!!
[C6x_1 ]      3.933948 s: IPC: 6 CPUs participating in IPC !!!
[C6x_1 ]      3.933962 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]     12.500601 s: IPC: HLOS is ready !!!
[C6x_1 ]     12.504290 s: IPC: Init ... Done !!!
[C6x_1 ]     12.504316 s: APP: Syncing with 5 CPUs ... !!!
[C6x_1 ]     13.799958 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_1 ]     13.799971 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]     13.800622 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]     13.800660 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]     13.800670 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]     13.800679 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]     13.801456 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]     13.801469 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]     13.801730 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]     13.801745 s: UDMA Copy: Init ... !!!
[C6x_1 ]     13.806752 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]     13.806774 s: APP: Init ... Done !!!
[C6x_1 ]     13.806783 s: APP: Run ... !!!
[C6x_1 ]     13.806791 s: IPC: Starting echo test ...
[C6x_1 ]     13.807935 s: APP: Run ... Done !!!
[C6x_1 ]     13.808239 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]     13.808708 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.825402 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]     13.877270 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]      4.015096 s: CIO: Init ... Done !!!
[C6x_2 ]      4.015121 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]      4.015131 s: CPU is running FreeRTOS
[C6x_2 ]      4.015139 s: APP: Init ... !!!
[C6x_2 ]      4.015147 s: SCICLIENT: Init ... !!!
[C6x_2 ]      4.015350 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]      4.015362 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]      4.015371 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]      4.015381 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]      4.015391 s: UDMA: Init ... !!!
[C6x_2 ]      4.016877 s: UDMA: Init ... Done !!!
[C6x_2 ]      4.016895 s: MEM: Init ... !!!
[C6x_2 ]      4.016908 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 16777216 bytes !!!
[C6x_2 ]      4.016925 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]      4.016940 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331648 bytes !!!
[C6x_2 ]      4.016957 s: MEM: Init ... Done !!!
[C6x_2 ]      4.016965 s: IPC: Init ... !!!
[C6x_2 ]      4.016986 s: IPC: 6 CPUs participating in IPC !!!
[C6x_2 ]      4.017000 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]     12.701836 s: IPC: HLOS is ready !!!
[C6x_2 ]     12.705400 s: IPC: Init ... Done !!!
[C6x_2 ]     12.705427 s: APP: Syncing with 5 CPUs ... !!!
[C6x_2 ]     13.799959 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_2 ]     13.799972 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]     13.800644 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]     13.800677 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]     13.800686 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]     13.800696 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]     13.801472 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]     13.801485 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]     13.801742 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]     13.801756 s: UDMA Copy: Init ... !!!
[C6x_2 ]     13.807073 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]     13.807097 s: APP: Init ... Done !!!
[C6x_2 ]     13.807106 s: APP: Run ... !!!
[C6x_2 ]     13.807115 s: IPC: Starting echo test ...
[C6x_2 ]     13.808339 s: APP: Run ... Done !!!
[C6x_2 ]     13.808643 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]     13.808707 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.825425 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]     13.877313 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]      4.239183 s: CIO: Init ... Done !!!
[C7x_1 ]      4.239196 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]      4.239208 s: CPU is running FreeRTOS
[C7x_1 ]      4.239216 s: APP: Init ... !!!
[C7x_1 ]      4.239224 s: SCICLIENT: Init ... !!!
[C7x_1 ]      4.239426 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]      4.239441 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]      4.239451 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]      4.239462 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      4.239471 s: UDMA: Init ... !!!
[C7x_1 ]      4.240598 s: UDMA: Init ... Done !!!
[C7x_1 ]      4.240610 s: MEM: Init ... !!!
[C7x_1 ]      4.240621 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435456 bytes !!!
[C7x_1 ]      4.240642 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]      4.240660 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ]      4.240678 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]      4.240695 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 385875968 bytes !!!
[C7x_1 ]      4.240713 s: MEM: Init ... Done !!!
[C7x_1 ]      4.240721 s: IPC: Init ... !!!
[C7x_1 ]      4.240735 s: IPC: 6 CPUs participating in IPC !!!
[C7x_1 ]      4.240749 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     13.223183 s: IPC: HLOS is ready !!!
[C7x_1 ]     13.225258 s: IPC: Init ... Done !!!
[C7x_1 ]     13.225272 s: APP: Syncing with 5 CPUs ... !!!
[C7x_1 ]     13.799960 s: APP: Syncing with 5 CPUs ... Done !!!
[C7x_1 ]     13.799977 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     13.800134 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     13.800156 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     13.800166 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     13.800176 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     13.800335 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]     13.800431 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     13.800530 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     13.800598 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     13.800670 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     13.800768 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     13.800859 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     13.800926 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     13.800947 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]     13.800959 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     13.801098 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     13.801112 s: APP: Init ... Done !!!
[C7x_1 ]     13.801121 s: APP: Run ... !!!
[C7x_1 ]     13.801129 s: IPC: Starting echo test ...
[C7x_1 ]     13.801278 s: APP: Run ... Done !!!
[C7x_1 ]     13.808244 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]     13.808702 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.825446 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]     13.877347 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 

root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# ./run_app_tidl.sh
APP: Init ... !!!
MEM: Init ... !!!
MEM: Initialized DMA HEAP (fd=4) !!!
MEM: Init ... Done !!!
IPC: Init ... !!!
IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
    96.437040 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
    96.447275 s:  VX_ZONE_INIT:Enabled
    96.447302 s:  VX_ZONE_ERROR:Enabled
    96.447308 s:  VX_ZONE_WARNING:Enabled
    96.448144 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    96.448281 s:  VX_ZONE_INIT:[tivxHostInitLocal:93] Initialization Done for HOST !!!
network file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin
config  file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin
Iteration 0 of 1000000 ... 


 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 



 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: p


Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD =   1.79 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_0: TOTAL LOAD =  11. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_1: TOTAL LOAD =  10. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c6x_1: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c6x_2: TOTAL LOAD =   1. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c7x_1: TOTAL LOAD =   1. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )


HWA performance statistics,
===========================



DDR performance statistics,
===========================

DDR: READ  BW: AVG =    213 MB/s, PEAK =   5329 MB/s
DDR: WRITE BW: AVG =     19 MB/s, PEAK =   2897 MB/s
DDR: TOTAL BW: AVG =    232 MB/s, PEAK =   8226 MB/s


Detailed CPU performance/memory statistics,
===========================================

DDR_SHARED_MEM: Alloc's: 31 alloc's of 35809324 bytes 
DDR_SHARED_MEM: Free's : 18 free's  of 9711523 bytes 
DDR_SHARED_MEM: Open's : 13 allocs  of 26097801 bytes 
DDR_SHARED_MEM: Total size: 536870912 bytes 

CPU: mcu2_0: TASK:           IPC_RX:   0. 0 %
CPU: mcu2_0: TASK:       REMOTE_SRV:   0. 0 %
CPU: mcu2_0: TASK:        LOAD_TEST:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CPU_0:   0. 0 %
CPU: mcu2_0: TASK:        TIVX_V1NF:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_V1LDC1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_V1SC1:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_V1MSC2:   0. 0 %
CPU: mcu2_0: TASK:       TIVXVVISS1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT2:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_DISP1:   0.43 %
CPU: mcu2_0: TASK:       TIVX_DISP2:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CSITX:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT3:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT4:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT5:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT6:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT7:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT8:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M1:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M2:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M3:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M4:   0. 0 %

CPU: mcu2_0: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   10620672 B ( 63 % unused)
CPU: mcu2_0: HEAP:           L3_MEM: size =     262144 B, free =     261888 B ( 99 % unused)

CPU: mcu2_1: TASK:           IPC_RX:   0. 0 %
CPU: mcu2_1: TASK:       REMOTE_SRV:   0. 0 %
CPU: mcu2_1: TASK:        LOAD_TEST:   0. 0 %
CPU: mcu2_1: TASK:       TIVX_CPU_1:   0. 0 %
CPU: mcu2_1: TASK:         TIVX_SDE:   0. 0 %
CPU: mcu2_1: TASK:         TIVX_DOF:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU: mcu2_1: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU: mcu2_1: HEAP:           L3_MEM: size =     262144 B, free =     262144 B (100 % unused)

CPU:  c6x_1: TASK:           IPC_RX:   0. 0 %
CPU:  c6x_1: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c6x_1: TASK:        LOAD_TEST:   0. 0 %
CPU:  c6x_1: TASK:         TIVX_CPU:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c6x_1: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU:  c6x_1: HEAP:           L2_MEM: size =     229376 B, free =     229376 B (100 % unused)
CPU:  c6x_1: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B (100 % unused)

CPU:  c6x_2: TASK:           IPC_RX:   0. 0 %
CPU:  c6x_2: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c6x_2: TASK:        LOAD_TEST:   0. 0 %
CPU:  c6x_2: TASK:         TIVX_CPU:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c6x_2: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU:  c6x_2: HEAP:           L2_MEM: size =     229376 B, free =     229376 B (100 % unused)
CPU:  c6x_2: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B (100 % unused)

CPU:  c7x_1: TASK:           IPC_RX:   0. 0 %
CPU:  c7x_1: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c7x_1: TASK:        LOAD_TEST:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P1:   0.16 %
CPU:  c7x_1: TASK:      TIVX_C71_P2:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P3:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P4:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P5:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P6:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P7:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P8:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c7x_1: HEAP:    DDR_LOCAL_MEM: size =  268435456 B, free =  248440320 B ( 92 % unused)
CPU:  c7x_1: HEAP:           L3_MEM: size =    8159232 B, free =          0 B (  0 % unused)
CPU:  c7x_1: HEAP:           L2_MEM: size =     458752 B, free =     458752 B (100 % unused)
CPU:  c7x_1: HEAP:           L1_MEM: size =      16384 B, free =          0 B (  0 % unused)
CPU:  c7x_1: HEAP:  DDR_SCRATCH_MEM: size =  385875968 B, free =  385344256 B ( 99 % unused)


GRAPH:   app_tidl_graph (#nodes =   1, #executions =      8)
 NODE:       DSP_C7-1:                 TIDLNode: avg =   1536 usecs, min/max =   1365 /   2698 usecs, #executions =          8

GRAPH:          Display (#nodes =   1, #executions =      8)
 NODE:       DISPLAY1:              DisplayNode: avg =  57247 usecs, min/max =  52817 /  61971 usecs, #executions =          8

 PERF:           FILEIO: avg =  34457 usecs, min/max =  19808 /  54277 usecs, #executions =          8
 PERF:             DRAW: avg =  14368 usecs, min/max =  12235 /  26351 usecs, #executions =          8
 PERF:            TOTAL: avg = 109280 usecs, min/max =  95256 / 129253 usecs, #executions =          8

 PERF:            TOTAL:    9.15 FPS



 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 


 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 

Regards,

Barry

Hi Brigesh，

Can you have an update here? Please support me.

Regards,

Barry

Hi Brigesh，

Our LCD only supports RGB565 and RGB666. We are executing run_app_tidl.sh, and the output mode is DSI.

How does TDA4 need to be modified to match the LCD color format output display? Can you help us reply? Thanks

we look forward to your reply.

Regards,

Barry

Hi TI Experts，

Can you update it for us?

Regards,

Hi Barry,

Sorry i was out of office for sometime.

When you say LCD supports only RGB565 and RGB666, where is this format limitation? Is it at the input of LCD? Does it mean DSI output format must be one of these formats?

I think by default we use RGB888 output format, as given in below comment in packages\ti\drv\dss\src\drv\dctrl\dss_dctrlDsi.c file. We have not really validated any other output format from DSI.

/* TODO: Only RGB24 input and output supported as of now,
multipled by 3 for RGB24 */
#define DSITX_VID_DATA_TYPE (DSITX_VID_DATA_TYPE_RGB_24)
#define DSITX_VID_PIX_MODE (DSITX_VID_PIXEL_MODE_RGB_24)
#define BPP (3u)  

Regards,

Brijesh

Hi Brigesh,

thanks for your reply.

As you said, this limitation comes from the LCD screen. The LCD screen can only support RGB565/RGB666 input, so I need TDA4 DSI to output the RGB565 format to display correctly.

Can you help us confirm the specific modification points for TDA4 to output DSI signals in RGB565 format? The output demo file I executed is run_app_tidl.sh;

Looking forward for your reply, thank you

Regards,

Barry

Hi Barry,

Can you try changing to

#define DSITX_VID_DATA_TYPE  (DSITX_VID_DATA_TYPE_RGB_16)

#define DSITX_VID_PIX_MODE  (DSITX_VID_PIXEL_MODE_RGB_16)

#define BPP (2u)

Regards,

Brijesh

Hi Brigesh,

thank you for your response.

We also noticed and modified this; but the output display was disordered stripes when we executed run_app_tidl.sh; because the output demo we executed was run_app_tidl.sh, the configuration in this TIDL demo was still in RGB888 format;

So can you tell us how to modify the output RGB565 format in TDA4 TIDL demo? (vision_apps/apps/dl_demos/app_tidl/main.c)

Looking forward to your reply, thank you.

Regards,

Barry

Hi Barry,

RGB565 output from DSI is not validated in the SDK.. This is new request and requires to be validated first on EVM.

Can you please raise this to your local TI support team? 

Regards,

Brijesh

Hi Brigesh,

thank you for your reply.

Can you tell me how to change the TIDL demo to output in RGB565 format?

I'm looking forward to your reply to this question, thank you

Regards,

Barry

Hi,

Again, i did not get it. Are you looking for RGB565 output from TIDL application or looking for RGB565 output from DSI? DSI output is currently fixed to RGB888 and as of now, no plan to support RGB565 format. This is why i had asked you to contact your local TI support to help you. 

Regards,

Brijesh

Hi Brigesh,

We want to change the TIDL demo application to output in RGB565 format.

thank you

Regards,

Barry

ok, can you please refer to the file ti-processor-sdk-rtos-j721e-evm-09_00_00_02\vision_apps\apps\dl_demos\app_tidl\main.c and change the format? 

Regards,

Brijesh

Hi Brigesh,

Can you give me the specific modification points of the code? In the file vision_apps\apps\dl_demos\app_tidl\main.c.thank you

Regards,

Barry

Hi Barry,

Please check the image which is sent to the Display node and change the format of this image to RGB565. 

Regards,

Brijesh

Hi Brijesh,

Sorry, maybe I didn’t make it clear. We are not changing the pictures in test_data/app_tidl.

We want to change the tidl_demo output format to RGB565 in vision_apps\apps\dl_demos\app_tidl\main.c. Can you send us the verified patch? Thanks

Regards,

Barry

Hi Barry,

I understand your requirement, but please refer to my above answer. I had pointed you to the application, where you have to make the changes and also suggested where to make changes. Could you please check after updating this application?  

Regards,

Brijesh