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AM5728: Not Loading AM5728 U-Boot through Code omposer Studio?

Ramachandra Parlapalli
Expert 1800 points

Part Number: AM5728

Hi Sir,

I am using AM5728 board and AM5728 SDK using. my booting option is 1.QSPI then 2. SD card. Actually I want erase the qspi then only boots from SD card(Not written any code in QSPI default junk?).

I used Working U-boot code loading through Code Composer Studio below commands.

I am using Below steps through CCSv8

1)Launch Selected configuration from am5728.ccxml and Load and test configuration of Device Name: GPEVM_AM572X

2) CPU Reset then PC=0x00030000

3)Tools--> Load Memory ->u-boot-spl.bin (0x40300000) -->Type Size(32-bits)-->Finish

4)Run -->Load Symbols --> u-boot-spl(not giving any address) --> OK

5)checking Disassembler and Memory Browser data present or not.

6)Change Program Counter to 0x40300000

7)Run the code.

In beagle board it will stop (##ERROR ## Please Reset the board ###)

but in our custom board nothing it's displaying, it will go and stop in 0x0000000c PRUSS1_GP register.

  • 0
    TI__Guru 50723 points

    Hello Ramachandra,

    We are not sure which documentation you are are referring for the above steps of using CCS to load U-boot. Can you provide us this info? Also which PSDK Linux release you are using for the u-boot binaries? 

    Also, can you review https://software-dl.ti.com/processor-sdk-linux/esd/AM57X/08_02_01_00/exports/docs/linux/Foundational_Components/Tools/Code_Composer_Studio.html documentation.

    Thanks

  • 0 in reply to Praveen Rao
    Expert 1800 points

    Hi Praveen,

    I used this method https://www.ti.com/video/3874225955001 to load u-boot through ccs and some gel files i loaded those output also i am attaching.

    Presently 3-boards dss output files attached.

    I used below link for gel files.

    https://git.ti.com/cgit/sitara-dss-files/am57xx-dss-files/tree/am57xx-boot.dss

    Output:

    /*****************************************Board 6 AM5728:*****************************************/
CTRL_CORE_BOOTSTRAP = 0x00008127
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * QSPI_4 -> SD -> USB

Current tracing vector, word 1 = 0x0000807f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  5: [Peripheral boot] Peripheral booting started
  * Bit  6: [Boot] Booting loop reached last device
  * Bit 15: [Peripheral boot] Peripheral booting failed

Current tracing vector, word 2 = 0x0000f010
  * Bit  4: [USB] USB connected
  * Bit 12: [Memory boot] Memory booting trial (first block)
  * Bit 13: [Memory boot] Memory booting trial (second block)
  * Bit 14: [Memory boot] Memory booting trial (third block)
  * Bit 15: [Memory boot] Memory booting trial (fourth block)

Current tracing vector, word 3 = 0x00200820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4
  * Bit 21: [Peripheral boot] Peripheral booting device USB

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003dde4

/*****************************************Board 5 AM5728:*****************************************/
CTRL_CORE_BOOTSTRAP = 0x00008127
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * QSPI_4 -> SD -> USB

Current tracing vector, word 1 = 0x0000009f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  7: [Boot] GP header found

Current tracing vector, word 2 = 0x00001000
  * Bit 12: [Memory boot] Memory booting trial (first block)

Current tracing vector, word 3 = 0x00000800
  * Bit 11: [Memory boot] Memory booting device QSPI_4

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003808c
  -> Data abort exception default handler
  -> DFAR = ffefeeee
  -> DFSR = 00000801

/*****************************************Board 2 AM5728:*****************************************/

CTRL_CORE_BOOTSTRAP = 0x00008127
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * QSPI_4 -> SD -> USB

Current tracing vector, word 1 = 0x0000807f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  5: [Peripheral boot] Peripheral booting started
  * Bit  6: [Boot] Booting loop reached last device
  * Bit 15: [Peripheral boot] Peripheral booting failed

Current tracing vector, word 2 = 0x0000f010
  * Bit  4: [USB] USB connected
  * Bit 12: [Memory boot] Memory booting trial (first block)
  * Bit 13: [Memory boot] Memory booting trial (second block)
  * Bit 14: [Memory boot] Memory booting trial (third block)
  * Bit 15: [Memory boot] Memory booting trial (fourth block)

Current tracing vector, word 3 = 0x00200820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4
  * Bit 21: [Peripheral boot] Peripheral booting device USB

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x00041760

  • 0 in reply to Ramachandra Parlapalli
    TI__Guru 50723 points

    Hello Ramachandra,

    Thanks for the references. We'll our domain expert look at and will get back on this.

    Regards.

  • 0 in reply to Praveen Rao
    TI__Mastermind 39626 points

    Hello Ramachandra,

    One thing I can see that might  be happening is that you are using an EVM target configuration and not an SoC one.
    The EVM  target configurations have .GEL files that initialize the board and would be conflicting with u-boot.

    Try using an SoC level configuration:

    Not the GPEVM or IDK options.

    -Josue

  • 0 in reply to Josue Zamitiz-Ayala
    Expert 1800 points

    Hi Josue, 

    I am using am5728 in only  target configuration i am attaching the snapshot.

    I am not using gel file for loading u-boot through ccs directly i am loading u-boot-spl & u-boot using below procedure.

     https://www.ti.com/video/3874225955001

    In 6 boards only 2 boards working reaming same issue i attached the not working boards output of DSS file on above

    Thanking you,


    Regards,

    Ramachandra.

  • 0 in reply to Ramachandra Parlapalli
    TI__Mastermind 39626 points

    Ramachandra,

    If I understand you correctly, you see a booting error in 4 out of 6 boards, meaning that 2 boards boot successfully by loading u-boot via CCS.

    Is this correct?

    And this DSS script is used to debug what is happening with the failing boards?
    From the output of this script, it seems like the error is not consistent..

    Does this u-boot image work on the AM572x EVM from the SD card?

    -Josue

  • 0 in reply to Josue Zamitiz-Ayala
    Expert 1800 points

    Hi Josue,

    If I understand you correctly, you see a booting error in 4 out of 6 boards, meaning that 2 boards boot successfully by loading u-boot via CCS.

    Is this correct?

    Yes 2 boards booting from JTAG through CCS & through sd card also booting in the same 2 boards.

    1.DSS files i am attaching now presently we change booting option from SD card only not from QSPI those DSS files i am attaching. Except one board all boards are same condition comparing with working board.

    2.In am57xx-ddr.dss Some register values are changes. EMIF_EXT_PHY_STATUS_17-24 some are different with working board.

    All DSS files i am taken from this Link:

    https://git.ti.com/cgit/sitara-dss-files/am57xx-dss-files/tree/

    boot.dss output:

    /**************************Working Board-3****************************/
CTRL_CORE_BOOTSTRAP = 0x00008107
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * SD -> QSPI_4

Current tracing vector, word 1 = 0x0000005f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  6: [Boot] Booting loop reached last device

Current tracing vector, word 2 = 0x0000f000
  * Bit 12: [Memory boot] Memory booting trial (first block)
  * Bit 13: [Memory boot] Memory booting trial (second block)
  * Bit 14: [Memory boot] Memory booting trial (third block)
  * Bit 15: [Memory boot] Memory booting trial (fourth block)

Current tracing vector, word 3 = 0x00000820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003a7ee
/**************************Not Booting Board-2****************************/
CTRL_CORE_BOOTSTRAP = 0x00008107
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * SD -> QSPI_4

Current tracing vector, word 1 = 0x0000005f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  6: [Boot] Booting loop reached last device

Current tracing vector, word 2 = 0x0000f000
  * Bit 12: [Memory boot] Memory booting trial (first block)
  * Bit 13: [Memory boot] Memory booting trial (second block)
  * Bit 14: [Memory boot] Memory booting trial (third block)
  * Bit 15: [Memory boot] Memory booting trial (fourth block)

Current tracing vector, word 3 = 0x00000820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003a7cc
/**************************Not Booting Board-6****************************/
CTRL_CORE_BOOTSTRAP = 0x00008107
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * SD -> QSPI_4

Current tracing vector, word 1 = 0x0000005f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  6: [Boot] Booting loop reached last device

Current tracing vector, word 2 = 0x0000f000
  * Bit 12: [Memory boot] Memory booting trial (first block)
  * Bit 13: [Memory boot] Memory booting trial (second block)
  * Bit 14: [Memory boot] Memory booting trial (third block)
  * Bit 15: [Memory boot] Memory booting trial (fourth block)

Current tracing vector, word 3 = 0x00000820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003f7e2

/**************************Not Booting Board-5****************************/
CTRL_CORE_BOOTSTRAP = 0x00008107
  * sysboot15 = 1, internal pulldown permanently disabled (recommended for eMMC boot)
  * XIP/NAND BOOTDEVICESIZE = 8-bit
  * XIP/NAND MUXCS0DEVICE = Non-muxed
  * XIP/NAND BOOTWAITEN, wait pin not monitored
  * SPEEDSELECT = 20 MHz
  * QSPI offset = 64KB
  * SD -> QSPI_4

Current tracing vector, word 1 = 0x0000009f
  * Bit  0: [Boot] Passed the public reset vector
  * Bit  1: [Boot] Entered main function
  * Bit  2: [Boot] Running after the cold reset
  * Bit  3: [Boot] Main booting routine entered
  * Bit  4: [Memory boot] Memory booting started
  * Bit  7: [Boot] GP header found

Current tracing vector, word 2 = 0x00001000
  * Bit 12: [Memory boot] Memory booting trial (first block)

Current tracing vector, word 3 = 0x00000820
  * Bit  5: [Memory boot] Memory booting device SD
  * Bit 11: [Memory boot] Memory booting device QSPI_4

Current tracing vector, word 4 = 0x00000000

Cold reset tracing vector, word 1 = 0x00000000

Cold reset tracing vector, word 2 = 0x00000000

Cold reset tracing vector, word 3 = 0x00000000

Cold reset tracing vector, word 4 = 0x00000000

Current copy of the PRM_RSTST register (reset reasons) = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

PRM_RSTST = 0x00000001
  * Bit 0 : GLOBAL_COLD_RST

Cortex A15 Program Counter = 0x0003808c
  -> Data abort exception default handler
  -> DFAR = ffefeeee
  -> DFSR = 00000801

     

    ddr.dss output:

    /**************************Working Board-3****************************/
********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00008107
  * SPEEDSELECT = 20 MHz
CM_CLKSEL_DPLL_DDR = 0x00000000
  * DPLL_MULT = 0 (x0)
  * DPLL_DIV = 0 (/1)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)
CM_DIV_H11_DPLL_DDR = 0x00000201
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 20 MHz
 -> F_dpll_ddr = 0 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 0 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 0 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x80710100
  * System Address Mapping = 0x80000000
  * Section Size = 2048 MB
  * Mapped to EMIF1
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x00000000
DMM_LISA_MAP_3 = 0x00000000

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x4a4a4a4a
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ck, ddr1_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x4a4a4a4a
ddr1_d[7:0], ddr1_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x4a4a4a4a
ddr1_d[23:16], ddr1_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x004a4a00
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x0009ce60
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x00010107
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x00001fff
EMIF_EXT_PHY_STATUS_4  = 0x00120000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00004924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x07000700
EMIF_EXT_PHY_STATUS_17 = 0x034503f5
EMIF_EXT_PHY_STATUS_18 = 0x01ca0213
EMIF_EXT_PHY_STATUS_19 = 0x01ca0213
EMIF_EXT_PHY_STATUS_20 = 0x020c010b
EMIF_EXT_PHY_STATUS_21 = 0x017c020f
EMIF_EXT_PHY_STATUS_22 = 0x034503f5
EMIF_EXT_PHY_STATUS_23 = 0x01ca0213
EMIF_EXT_PHY_STATUS_24 = 0x03d301f6
EMIF_EXT_PHY_STATUS_25 = 0x020c010b
EMIF_EXT_PHY_STATUS_26 = 0x017c020f
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000

********************** EMIF2 **********************

CTRL_CORE_CONTROL_DDRCACH2_0 = 0x4a4a4a4a
ddr2_casn, ddr2_rasn, ddr2_rst, ddr2_wen, ddr2_csn[0], ddr2_cke, ddr2_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ba[0], ddr2_ba[1], ddr2_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ck, ddr2_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_0 = 0x4a4a4a4a
ddr2_d[7:0], ddr2_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[0], ddr2_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[15:8], ddr2_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[1], ddr2_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_1 = 0x4a4a4a4a
ddr2_d[23:16], ddr2_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[2], ddr2_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[31:24], ddr2_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[3], ddr2_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_1 = 0x04e73000
ddr2_d[7:0], ddr2_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr2_d[23:16], ddr2_d[31:24]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT = 0x00000107
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x0000000f
EMIF_EXT_PHY_STATUS_4  = 0x00020000
EMIF_EXT_PHY_STATUS_5  = 0x00009999
EMIF_EXT_PHY_STATUS_6  = 0x00000924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x00000000
EMIF_EXT_PHY_STATUS_17 = 0x024203d5
EMIF_EXT_PHY_STATUS_18 = 0x03b800bc
EMIF_EXT_PHY_STATUS_19 = 0x03b800bc
EMIF_EXT_PHY_STATUS_20 = 0x01b70243
EMIF_EXT_PHY_STATUS_21 = 0x00000000
EMIF_EXT_PHY_STATUS_22 = 0x024203d5
EMIF_EXT_PHY_STATUS_23 = 0x03b800bc
EMIF_EXT_PHY_STATUS_24 = 0x038d0197
EMIF_EXT_PHY_STATUS_25 = 0x01b70243
EMIF_EXT_PHY_STATUS_26 = 0x00000000
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000


/**************************Not Booting Board-2****************************/
********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00008107
  * SPEEDSELECT = 20 MHz
CM_CLKSEL_DPLL_DDR = 0x00000000
  * DPLL_MULT = 0 (x0)
  * DPLL_DIV = 0 (/1)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)
CM_DIV_H11_DPLL_DDR = 0x00000201
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 20 MHz
 -> F_dpll_ddr = 0 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 0 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 0 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x80710100
  * System Address Mapping = 0x80000000
  * Section Size = 2048 MB
  * Mapped to EMIF1
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x00000000
DMM_LISA_MAP_3 = 0x00000000

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x4a4a4a4a
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ck, ddr1_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x4a4a4a4a
ddr1_d[7:0], ddr1_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x4a4a4a4a
ddr1_d[23:16], ddr1_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x004a4a00
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x0009ce60
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x00010107
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x00001fff
EMIF_EXT_PHY_STATUS_4  = 0x00120000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00004924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x07000700
EMIF_EXT_PHY_STATUS_17 = 0x02d00333
EMIF_EXT_PHY_STATUS_18 = 0x0366032c
EMIF_EXT_PHY_STATUS_19 = 0x0366032c
EMIF_EXT_PHY_STATUS_20 = 0x03fb02e9
EMIF_EXT_PHY_STATUS_21 = 0x028d0378
EMIF_EXT_PHY_STATUS_22 = 0x02d00333
EMIF_EXT_PHY_STATUS_23 = 0x0366032c
EMIF_EXT_PHY_STATUS_24 = 0x01ef0341
EMIF_EXT_PHY_STATUS_25 = 0x03fb02e9
EMIF_EXT_PHY_STATUS_26 = 0x028d0378
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000

********************** EMIF2 **********************

CTRL_CORE_CONTROL_DDRCACH2_0 = 0x4a4a4a4a
ddr2_casn, ddr2_rasn, ddr2_rst, ddr2_wen, ddr2_csn[0], ddr2_cke, ddr2_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ba[0], ddr2_ba[1], ddr2_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ck, ddr2_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_0 = 0x4a4a4a4a
ddr2_d[7:0], ddr2_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[0], ddr2_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[15:8], ddr2_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[1], ddr2_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_1 = 0x4a4a4a4a
ddr2_d[23:16], ddr2_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[2], ddr2_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[31:24], ddr2_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[3], ddr2_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_1 = 0x04e73000
ddr2_d[7:0], ddr2_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr2_d[23:16], ddr2_d[31:24]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT = 0x00000107
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x0000000f
EMIF_EXT_PHY_STATUS_4  = 0x00020000
EMIF_EXT_PHY_STATUS_5  = 0x00009999
EMIF_EXT_PHY_STATUS_6  = 0x00000924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x00000000
EMIF_EXT_PHY_STATUS_17 = 0x03ab00ef
EMIF_EXT_PHY_STATUS_18 = 0x038400c0
EMIF_EXT_PHY_STATUS_19 = 0x038400c0
EMIF_EXT_PHY_STATUS_20 = 0x01d10077
EMIF_EXT_PHY_STATUS_21 = 0x00000000
EMIF_EXT_PHY_STATUS_22 = 0x03ab00ef
EMIF_EXT_PHY_STATUS_23 = 0x038400c0
EMIF_EXT_PHY_STATUS_24 = 0x023e0097
EMIF_EXT_PHY_STATUS_25 = 0x01d10077
EMIF_EXT_PHY_STATUS_26 = 0x00000000
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000


/**************************Not Booting Board-6****************************/
********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00008107
  * SPEEDSELECT = 20 MHz
CM_CLKSEL_DPLL_DDR = 0x00000000
  * DPLL_MULT = 0 (x0)
  * DPLL_DIV = 0 (/1)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)
CM_DIV_H11_DPLL_DDR = 0x00000201
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 20 MHz
 -> F_dpll_ddr = 0 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 0 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 0 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x80710100
  * System Address Mapping = 0x80000000
  * Section Size = 2048 MB
  * Mapped to EMIF1
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x00000000
DMM_LISA_MAP_3 = 0x00000000

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x4a4a4a4a
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ck, ddr1_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x4a4a4a4a
ddr1_d[7:0], ddr1_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x4a4a4a4a
ddr1_d[23:16], ddr1_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x004a4a00
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x0009ce60
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x00010107
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x00001fff
EMIF_EXT_PHY_STATUS_4  = 0x00120000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00004924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x07000700
EMIF_EXT_PHY_STATUS_17 = 0x035a018f
EMIF_EXT_PHY_STATUS_18 = 0x033801d6
EMIF_EXT_PHY_STATUS_19 = 0x033801d6
EMIF_EXT_PHY_STATUS_20 = 0x039b037d
EMIF_EXT_PHY_STATUS_21 = 0x027e03f1
EMIF_EXT_PHY_STATUS_22 = 0x035a018f
EMIF_EXT_PHY_STATUS_23 = 0x033801d6
EMIF_EXT_PHY_STATUS_24 = 0x00c4029d
EMIF_EXT_PHY_STATUS_25 = 0x039b037d
EMIF_EXT_PHY_STATUS_26 = 0x027e03f1
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000

********************** EMIF2 **********************

CTRL_CORE_CONTROL_DDRCACH2_0 = 0x4a4a4a4a
ddr2_casn, ddr2_rasn, ddr2_rst, ddr2_wen, ddr2_csn[0], ddr2_cke, ddr2_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ba[0], ddr2_ba[1], ddr2_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ck, ddr2_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_0 = 0x4a4a4a4a
ddr2_d[7:0], ddr2_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[0], ddr2_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[15:8], ddr2_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[1], ddr2_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_1 = 0x4a4a4a4a
ddr2_d[23:16], ddr2_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[2], ddr2_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[31:24], ddr2_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[3], ddr2_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_1 = 0x04e73000
ddr2_d[7:0], ddr2_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr2_d[23:16], ddr2_d[31:24]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT = 0x00000107
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x0000000f
EMIF_EXT_PHY_STATUS_4  = 0x00020000
EMIF_EXT_PHY_STATUS_5  = 0x00009999
EMIF_EXT_PHY_STATUS_6  = 0x00000924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x00000000
EMIF_EXT_PHY_STATUS_17 = 0x032903c9
EMIF_EXT_PHY_STATUS_18 = 0x03df02fc
EMIF_EXT_PHY_STATUS_19 = 0x03df02fc
EMIF_EXT_PHY_STATUS_20 = 0x024a0364
EMIF_EXT_PHY_STATUS_21 = 0x00000000
EMIF_EXT_PHY_STATUS_22 = 0x032903c9
EMIF_EXT_PHY_STATUS_23 = 0x03df02fc
EMIF_EXT_PHY_STATUS_24 = 0x01bd03fc
EMIF_EXT_PHY_STATUS_25 = 0x024a0364
EMIF_EXT_PHY_STATUS_26 = 0x00000000
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000


/**************************Not Booting Board-5****************************/
********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00008107
  * SPEEDSELECT = 20 MHz
CM_CLKSEL_DPLL_DDR = 0x00000000
  * DPLL_MULT = 0 (x0)
  * DPLL_DIV = 0 (/1)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)
CM_DIV_H11_DPLL_DDR = 0x00000201
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 20 MHz
 -> F_dpll_ddr = 0 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 0 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 0 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x80710100
  * System Address Mapping = 0x80000000
  * Section Size = 2048 MB
  * Mapped to EMIF1
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x00000000
DMM_LISA_MAP_3 = 0x00000000

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x4a4a4a4a
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_ck, ddr1_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x4a4a4a4a
ddr1_d[7:0], ddr1_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x4a4a4a4a
ddr1_d[23:16], ddr1_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x004a4a00
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x0009ce60
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x00010107
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x00001fff
EMIF_EXT_PHY_STATUS_4  = 0x00120000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00004924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x07000700
EMIF_EXT_PHY_STATUS_17 = 0x02cb02e5
EMIF_EXT_PHY_STATUS_18 = 0x00f7033a
EMIF_EXT_PHY_STATUS_19 = 0x00f7033a
EMIF_EXT_PHY_STATUS_20 = 0x003803db
EMIF_EXT_PHY_STATUS_21 = 0x037e02e7
EMIF_EXT_PHY_STATUS_22 = 0x02cb02e5
EMIF_EXT_PHY_STATUS_23 = 0x00f7033a
EMIF_EXT_PHY_STATUS_24 = 0x028900ae
EMIF_EXT_PHY_STATUS_25 = 0x003803db
EMIF_EXT_PHY_STATUS_26 = 0x037e02e7
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000

********************** EMIF2 **********************

CTRL_CORE_CONTROL_DDRCACH2_0 = 0x4a4a4a4a
ddr2_casn, ddr2_rasn, ddr2_rst, ddr2_wen, ddr2_csn[0], ddr2_cke, ddr2_odt[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_a[15:0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ba[0], ddr2_ba[1], ddr2_ba[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_ck, ddr2_nck
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_0 = 0x4a4a4a4a
ddr2_d[7:0], ddr2_dqm[0]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[0], ddr2_dqsn[0]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[15:8], ddr2_dqm[1]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[1], ddr2_dqsn[1]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH2_1 = 0x4a4a4a4a
ddr2_d[23:16], ddr2_dqm[2]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[2], ddr2_dqsn[2]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_d[31:24], ddr2_dqm[3]
  * Pull-down selected
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr2_dqs[3], ddr2_dqsn[3]
  * Pull-down selected for padp, pull-up selected for padn
  * Slew rate is 2, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_1 = 0x04e73000
ddr2_d[7:0], ddr2_d[15:8]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability
ddr2_d[23:16], ddr2_d[31:24]
  * Internal VREF enabled
  * Capacitor between Vbias and ground
  * 8-uA VREF output drive capability

CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT = 0x00000107
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x60812031
EMIF_SDRAM_CONFIG_2 = 0x00000010
EMIF_SDRAM_REFRESH_CONTROL = 0x8000061b
EMIF_SDRAM_TIMING_1 = 0x1c000000
EMIF_SDRAM_TIMING_2 = 0x00000000
EMIF_SDRAM_TIMING_3 = 0x000f8120
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0000081e
  * Bits 4:0 READ_LATENCY = 30
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 2
  * Bit 18 PHY_INVERT_CLKOUT = 0
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 0
  * Bit 25 WRLVL_MASK = 0
  * Bit 26 RDLVLGATE_MASK = 0
  * Bit 27 RDLVL_MASK = 0

EMIF_EXT_PHY_CONTROL_1  = 0x04020080
EMIF_EXT_PHY_CONTROL_2  = 0x00000000
EMIF_EXT_PHY_CONTROL_3  = 0x00000000
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x00000000
EMIF_EXT_PHY_CONTROL_6  = 0x00000000
EMIF_EXT_PHY_CONTROL_7  = 0x00400040
EMIF_EXT_PHY_CONTROL_8  = 0x00400040
EMIF_EXT_PHY_CONTROL_9  = 0x00400040
EMIF_EXT_PHY_CONTROL_10 = 0x00400040
EMIF_EXT_PHY_CONTROL_11 = 0x00400040
EMIF_EXT_PHY_CONTROL_12 = 0x00400040
EMIF_EXT_PHY_CONTROL_13 = 0x00400040
EMIF_EXT_PHY_CONTROL_14 = 0x00400040
EMIF_EXT_PHY_CONTROL_15 = 0x00400040
EMIF_EXT_PHY_CONTROL_16 = 0x00400040
EMIF_EXT_PHY_CONTROL_17 = 0x00000000
EMIF_EXT_PHY_CONTROL_18 = 0x00000000
EMIF_EXT_PHY_CONTROL_19 = 0x00000000
EMIF_EXT_PHY_CONTROL_20 = 0x00000000
EMIF_EXT_PHY_CONTROL_21 = 0x00000000
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x00010080
EMIF_EXT_PHY_CONTROL_25 = 0x00000000
EMIF_EXT_PHY_CONTROL_26 = 0x01500150
EMIF_EXT_PHY_CONTROL_27 = 0x01500150
EMIF_EXT_PHY_CONTROL_28 = 0x01500150
EMIF_EXT_PHY_CONTROL_29 = 0x01500150
EMIF_EXT_PHY_CONTROL_30 = 0x01500150
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001ff1f3
EMIF_EXT_PHY_STATUS_2  = 0xffffffff
EMIF_EXT_PHY_STATUS_3  = 0x0000000f
EMIF_EXT_PHY_STATUS_4  = 0x00020000
EMIF_EXT_PHY_STATUS_5  = 0x00009999
EMIF_EXT_PHY_STATUS_6  = 0x00000924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x07000700
EMIF_EXT_PHY_STATUS_13 = 0x07000700
EMIF_EXT_PHY_STATUS_14 = 0x07000700
EMIF_EXT_PHY_STATUS_15 = 0x07000700
EMIF_EXT_PHY_STATUS_16 = 0x00000000
EMIF_EXT_PHY_STATUS_17 = 0x0197007a
EMIF_EXT_PHY_STATUS_18 = 0x0213035e
EMIF_EXT_PHY_STATUS_19 = 0x0213035e
EMIF_EXT_PHY_STATUS_20 = 0x030a00f3
EMIF_EXT_PHY_STATUS_21 = 0x00000000
EMIF_EXT_PHY_STATUS_22 = 0x0197007a
EMIF_EXT_PHY_STATUS_23 = 0x0213035e
EMIF_EXT_PHY_STATUS_24 = 0x025601d6
EMIF_EXT_PHY_STATUS_25 = 0x030a00f3
EMIF_EXT_PHY_STATUS_26 = 0x00000000
EMIF_EXT_PHY_STATUS_27 = 0x00000000
EMIF_EXT_PHY_STATUS_28 = 0x00000000

    Not booting from SD-Card and JTAG through CCS also  it will go and stop in 0x0000000c PRUSS1_GP register.

    How to check AM5728 Properly solder or not?(But device is connected i loaded the code into ram using Jtag) thanking you,

    Regards,

    Ramachandra.

  • 0 in reply to Ramachandra Parlapalli
    TI__Mastermind 39626 points

    Ramachandra,

    Do all boards pass the boundary scan test?

    Having two boards functioning fine with the software is a good sign and perhaps the issue with the other boards is HW related.

    Just to make sure,

    Josue Zamitiz-Ayala said:
    Does this u-boot image work on the AM572x EVM from the SD card?

    this is confirmed as well right?

    -Josue