TDA4VM: YOLOv5s6 compilation using tidl repo

Ramaseshan Subramanian

Part Number: TDA4VM

I am trying to compile yolov5s6 ti lite model using tidl repo. I got this error while compiling this custom retrained model.

mugundan@mugundan-virtual-machine:~/edgeai-tidl-tools/examples/osrt_python/ort$ python3 onnxrt_ep.py -c
Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']

Running 1 Models - ['last']


Running_Model :  last  

last ot found in availbale list of model configs - dict_keys(['cl-ort-resnet18-v1', 'cl-ort-resnet18-v1_4batch', 'ss-ort-deeplabv3lite_mobilenetv2', 'od-ort-ssd-lite_mobilenetv2_fpn', 'cl-tfl-mobilenet_v1_1.0_224', 'cl-tfl-mobilenetv2_4batch', 'od-tfl-ssd_mobilenet_v2_300_float', 'od-tfl-ssdlite_mobiledet_dsp_320x320_coco', 'ss-tfl-deeplabv3_mnv2_ade20k_float', 'cl-dlr-tflite_inceptionnetv3', 'cl-dlr-onnx_mobilenetv2', 'cl-dlr-timm_mobilenetv3_large_100', 'cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite', 'cl-6360_onnxrt_imagenet1k_fbr-pycls_regnetx-200mf_onnx', 'cl-3090_tvmdlr_imagenet1k_torchvision_mobilenet_v2_tv_onnx', 'od-2020_tflitert_coco_tf1-models_ssdlite_mobiledet_dsp_320x320_coco_20200519_tflite', 'od-8020_onnxrt_coco_edgeai-mmdet_ssd_mobilenetv2_lite_512x512_20201214_model_onnx', 'od-8200_onnxrt_coco_edgeai-mmdet_yolox_nano_lite_416x416_20220214_model_onnx', 'od-8220_onnxrt_coco_edgeai-mmdet_yolox_s_lite_640x640_20220221_model_onnx', 'od-8420_onnxrt_widerface_edgeai-mmdet_yolox_s_lite_640x640_20220307_model_onnx', 'ss-2580_tflitert_ade20k32_mlperf_deeplabv3_mnv2_ade20k32_float_tflite', 'ss-8610_onnxrt_ade20k32_edgeai-tv_deeplabv3plus_mobilenetv2_edgeailite_512x512_20210308_outby4_onnx', 'cl-ort-caffe_mobilenet_v1', 'cl-ort-caffe_mobilenet_v2', 'cl-ort-caffe_squeezenet_v1_1', 'cl-ort-caffe_resnet10', 'cl-ort-caffe_mobilenetv1_ssd', 'cl-ort-caffe_pelee_ssd', 'cl-ort-caffe_erfnet'])
Process Process-1:
Traceback (most recent call last):
  File "/usr/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap
    self.run()
  File "/usr/lib/python3.10/multiprocessing/process.py", line 108, in run
    self._target(*self._args, **self._kwargs)
  File "/home/mugundan/edgeai-tidl-tools/examples/osrt_python/ort/onnxrt_ep.py", line 132, in run_model
    config = models_configs[model]
KeyError: 'last'

over 1 year ago

+1 Pratik Kedar over 1 year ago

TI__Mastermind 24041 points

Can you elaborate all the changes you did (with file names) for custom model training ?

0 Ramaseshan Subramanian over 1 year ago in reply to Pratik Kedar

Intellectual 490 points

yeah sure

1) In onnxrt_ep.py,

#models = models_configs.keys()
if len(args.models) > 0:
    models = args.models
else :
    models = ['last'] #change here
    if(SOC == "am69a"):
        models.append('cl-ort-resnet18-v1_4batch')

if ( args.run_model_zoo ):
    models = [
             'od-8020_onnxrt_coco_edgeai-mmdet_ssd_mobilenetv2_lite_512x512_20201214_model_onnx',
             'od-8200_onnxrt_coco_edgeai-mmdet_yolox_nano_lite_416x416_20220214_model_onnx',
            #  'od-8420_onnxrt_widerface_edgeai-mmdet_yolox_s_lite_640x640_20220307_model_onnx',# not working - 
             'ss-8610_onnxrt_ade20k32_edgeai-tv_deeplabv3plus_mobilenetv2_edgeailite_512x512_20210308_outby4_onnx',
             'od-8220_onnxrt_coco_edgeai-mmdet_yolox_s_lite_640x640_20220221_model_onnx',
             'cl-6360_onnxrt_imagenet1k_fbr-pycls_regnetx-200mf_onnx'
            ]
log = f'\nRunning {len(models)} Models - {models}\n'
print(log)

2)In common_utils.py i haved added model configs

    dict_file.append( {'last' : {
        'model_path' : os.path.join('/home/mugu/edgeai-tidl-tools/models/public/last.onnx'),
        'mean': [0, 0, 0],
        'std' : [0.003921568627,0.003921568627,0.003921568627],
        'num_images' : numImages,
        'num_classes': 9,
        'model_type': 'od',
        'od_type' : 'YoloV5',
        'framework' : '',
        'meta_layers_names_list' : os.path.join('/home/mugu/edgeai-tidl-tools/models/public/last.prototxt'),
        'session_name' : 'onnxrt' ,
        'meta_arch_type' : 6
    }})

Is there anything i have to change or add any other things, kindly help me out to solve this issue

0 Ramaseshan Subramanian over 1 year ago in reply to Pratik Kedar

Intellectual 490 points

I had no issues while training yolov5s6_ti_lite, I faced issues while compiling the model.

0 Pratik Kedar over 1 year ago in reply to Ramaseshan Subramanian

TI__Mastermind 24041 points

Firstly can you help me few details.

1) Are the std example supported are running fine ? this will cross out the env set related possibility.

2) Can you set debug_level = 2 flag and share the logs ?

+1 Ramaseshan Subramanian over 1 year ago in reply to Pratik Kedar

Intellectual 490 points

I tried by adding model configs in model_config.py, I could see the compilation works. The detailed log is mentioned below:

mugundan@mugundan-virtual-machine:~/edgeai-tidl-tools/examples/osrt_python/ort$ python3 onnxrt_ep.py -c
Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']

Running 1 Models - ['last']


Running_Model :  last  


Running shape inference on model ../../../models/public/last.onnx 

tidl_tools_path                                 = /home/mugundan/edgeai-tidl-tools/tidl_tools 
artifacts_folder                                = ../../../model-artifacts//last/ 
tidl_tensor_bits                                = 8 
debug_level                                     = 2 
num_tidl_subgraphs                              = 16 
tidl_denylist                                   = 
tidl_denylist_layer_name                        = 
tidl_denylist_layer_type                         = 
tidl_allowlist_layer_name                        = 
model_type                                      =  
tidl_calibration_accuracy_level                 = 7 
tidl_calibration_options:num_frames_calibration = 2 
tidl_calibration_options:bias_calibration_iterations = 5 
mixed_precision_factor = -1.000000 
model_group_id = 0 
power_of_2_quantization                         = 2 
enable_high_resolution_optimization             = 0 
pre_batchnorm_fold                              = 1 
add_data_convert_ops                          = 3 
output_feature_16bit_names_list                 =  
m_params_16bit_names_list                       =  
reserved_compile_constraints_flag               = 1601 
ti_internal_reserved_1                          = 
yolo_v3 is meta arch name 
yolo_v3
Number of OD backbone nodes = 192 
Size of odBackboneNodeIds = 192 
Supported TIDL layer type ---            Conv -- Conv_0 
Supported TIDL layer type ---            Relu -- Relu_1 
Supported TIDL layer type ---            Conv -- Conv_2 
Supported TIDL layer type ---            Relu -- Relu_3 
Supported TIDL layer type ---            Conv -- Conv_4 
Supported TIDL layer type ---            Relu -- Relu_5 
Supported TIDL layer type ---            Conv -- Conv_6 
Supported TIDL layer type ---            Relu -- Relu_7 
Supported TIDL layer type ---            Conv -- Conv_8 
Supported TIDL layer type ---            Relu -- Relu_9 
Supported TIDL layer type ---            Conv -- Conv_10 
Supported TIDL layer type ---            Relu -- Relu_11 
Supported TIDL layer type ---             Add -- Add_12 
Supported TIDL layer type ---            Conv -- Conv_13 
Supported TIDL layer type ---            Relu -- Relu_14 
Supported TIDL layer type ---          Concat -- Concat_15 
Supported TIDL layer type ---            Conv -- Conv_16 
Supported TIDL layer type ---            Relu -- Relu_17 
Supported TIDL layer type ---            Conv -- Conv_18 
Supported TIDL layer type ---            Relu -- Relu_19 
Supported TIDL layer type ---            Conv -- Conv_20 
Supported TIDL layer type ---            Relu -- Relu_21 
Supported TIDL layer type ---            Conv -- Conv_22 
Supported TIDL layer type ---            Relu -- Relu_23 
Supported TIDL layer type ---            Conv -- Conv_24 
Supported TIDL layer type ---            Relu -- Relu_25 
Supported TIDL layer type ---             Add -- Add_26 
Supported TIDL layer type ---            Conv -- Conv_27 
Supported TIDL layer type ---            Relu -- Relu_28 
Supported TIDL layer type ---            Conv -- Conv_29 
Supported TIDL layer type ---            Relu -- Relu_30 
Supported TIDL layer type ---             Add -- Add_31 
Supported TIDL layer type ---            Conv -- Conv_32 
Supported TIDL layer type ---            Relu -- Relu_33 
Supported TIDL layer type ---            Conv -- Conv_34 
Supported TIDL layer type ---            Relu -- Relu_35 
Supported TIDL layer type ---             Add -- Add_36 
Supported TIDL layer type ---            Conv -- Conv_37 
Supported TIDL layer type ---            Relu -- Relu_38 
Supported TIDL layer type ---          Concat -- Concat_39 
Supported TIDL layer type ---            Conv -- Conv_40 
Supported TIDL layer type ---            Relu -- Relu_41 
Supported TIDL layer type ---            Conv -- Conv_42 
Supported TIDL layer type ---            Relu -- Relu_43 
Supported TIDL layer type ---            Conv -- Conv_44 
Supported TIDL layer type ---            Relu -- Relu_45 
Supported TIDL layer type ---            Conv -- Conv_46 
Supported TIDL layer type ---            Relu -- Relu_47 
Supported TIDL layer type ---            Conv -- Conv_48 
Supported TIDL layer type ---            Relu -- Relu_49 
Supported TIDL layer type ---             Add -- Add_50 
Supported TIDL layer type ---            Conv -- Conv_51 
Supported TIDL layer type ---            Relu -- Relu_52 
Supported TIDL layer type ---            Conv -- Conv_53 
Supported TIDL layer type ---            Relu -- Relu_54 
Supported TIDL layer type ---             Add -- Add_55 
Supported TIDL layer type ---            Conv -- Conv_56 
Supported TIDL layer type ---            Relu -- Relu_57 
Supported TIDL layer type ---            Conv -- Conv_58 
Supported TIDL layer type ---            Relu -- Relu_59 
Supported TIDL layer type ---             Add -- Add_60 
Supported TIDL layer type ---            Conv -- Conv_61 
Supported TIDL layer type ---            Relu -- Relu_62 
Supported TIDL layer type ---          Concat -- Concat_63 
Supported TIDL layer type ---            Conv -- Conv_64 
Supported TIDL layer type ---            Relu -- Relu_65 
Supported TIDL layer type ---            Conv -- Conv_66 
Supported TIDL layer type ---            Relu -- Relu_67 
Supported TIDL layer type ---            Conv -- Conv_68 
Supported TIDL layer type ---            Relu -- Relu_69 
Supported TIDL layer type ---            Conv -- Conv_70 
Supported TIDL layer type ---            Relu -- Relu_71 
Supported TIDL layer type ---            Conv -- Conv_72 
Supported TIDL layer type ---            Relu -- Relu_73 
Supported TIDL layer type ---             Add -- Add_74 
Supported TIDL layer type ---            Conv -- Conv_75 
Supported TIDL layer type ---            Relu -- Relu_76 
Supported TIDL layer type ---          Concat -- Concat_77 
Supported TIDL layer type ---            Conv -- Conv_78 
Supported TIDL layer type ---            Relu -- Relu_79 
Supported TIDL layer type ---            Conv -- Conv_80 
Supported TIDL layer type ---            Relu -- Relu_81 
Supported TIDL layer type ---            Conv -- Conv_82 
Supported TIDL layer type ---            Relu -- Relu_83 
Supported TIDL layer type ---         MaxPool -- MaxPool_84 
Supported TIDL layer type ---         MaxPool -- MaxPool_86 
Supported TIDL layer type ---         MaxPool -- MaxPool_89 
Supported TIDL layer type ---          Concat -- Concat_90 
Supported TIDL layer type ---            Conv -- Conv_91 
Supported TIDL layer type ---            Relu -- Relu_92 
Supported TIDL layer type ---            Conv -- Conv_93 
Supported TIDL layer type ---            Relu -- Relu_94 
Supported TIDL layer type ---            Conv -- Conv_95 
Supported TIDL layer type ---            Relu -- Relu_96 
Supported TIDL layer type ---            Conv -- Conv_97 
Supported TIDL layer type ---            Relu -- Relu_98 
Supported TIDL layer type ---            Conv -- Conv_99 
Supported TIDL layer type ---            Relu -- Relu_100 
Supported TIDL layer type ---          Concat -- Concat_101 
Supported TIDL layer type ---            Conv -- Conv_102 
Supported TIDL layer type ---            Relu -- Relu_103 
Supported TIDL layer type ---            Conv -- Conv_104 
Supported TIDL layer type ---            Relu -- Relu_105 
Supported TIDL layer type ---          Resize -- Resize_107 
Supported TIDL layer type ---          Concat -- Concat_108 
Supported TIDL layer type ---            Conv -- Conv_109 
Supported TIDL layer type ---            Relu -- Relu_110 
Supported TIDL layer type ---            Conv -- Conv_111 
Supported TIDL layer type ---            Relu -- Relu_112 
Supported TIDL layer type ---            Conv -- Conv_113 
Supported TIDL layer type ---            Relu -- Relu_114 
Supported TIDL layer type ---            Conv -- Conv_115 
Supported TIDL layer type ---            Relu -- Relu_116 
Supported TIDL layer type ---          Concat -- Concat_117 
Supported TIDL layer type ---            Conv -- Conv_118 
Supported TIDL layer type ---            Relu -- Relu_119 
Supported TIDL layer type ---            Conv -- Conv_120 
Supported TIDL layer type ---            Relu -- Relu_121 
Supported TIDL layer type ---          Resize -- Resize_123 
Supported TIDL layer type ---          Concat -- Concat_124 
Supported TIDL layer type ---            Conv -- Conv_125 
Supported TIDL layer type ---            Relu -- Relu_126 
Supported TIDL layer type ---            Conv -- Conv_127 
Supported TIDL layer type ---            Relu -- Relu_128 
Supported TIDL layer type ---            Conv -- Conv_129 
Supported TIDL layer type ---            Relu -- Relu_130 
Supported TIDL layer type ---            Conv -- Conv_131 
Supported TIDL layer type ---            Relu -- Relu_132 
Supported TIDL layer type ---          Concat -- Concat_133 
Supported TIDL layer type ---            Conv -- Conv_134 
Supported TIDL layer type ---            Relu -- Relu_135 
Supported TIDL layer type ---            Conv -- Conv_136 
Supported TIDL layer type ---            Relu -- Relu_137 
Supported TIDL layer type ---          Resize -- Resize_139 
Supported TIDL layer type ---          Concat -- Concat_140 
Supported TIDL layer type ---            Conv -- Conv_141 
Supported TIDL layer type ---            Relu -- Relu_142 
Supported TIDL layer type ---            Conv -- Conv_143 
Supported TIDL layer type ---            Relu -- Relu_144 
Supported TIDL layer type ---            Conv -- Conv_145 
Supported TIDL layer type ---            Relu -- Relu_146 
Supported TIDL layer type ---            Conv -- Conv_147 
Supported TIDL layer type ---            Relu -- Relu_148 
Supported TIDL layer type ---          Concat -- Concat_149 
Supported TIDL layer type ---            Conv -- Conv_150 
Supported TIDL layer type ---            Relu -- Relu_151 
Supported TIDL layer type ---            Conv -- Conv_152 
Supported TIDL layer type ---            Relu -- Relu_153 
Supported TIDL layer type ---          Concat -- Concat_154 
Supported TIDL layer type ---            Conv -- Conv_155 
Supported TIDL layer type ---            Relu -- Relu_156 
Supported TIDL layer type ---            Conv -- Conv_157 
Supported TIDL layer type ---            Relu -- Relu_158 
Supported TIDL layer type ---            Conv -- Conv_159 
Supported TIDL layer type ---            Relu -- Relu_160 
Supported TIDL layer type ---            Conv -- Conv_161 
Supported TIDL layer type ---            Relu -- Relu_162 
Supported TIDL layer type ---          Concat -- Concat_163 
Supported TIDL layer type ---            Conv -- Conv_164 
Supported TIDL layer type ---            Relu -- Relu_165 
Supported TIDL layer type ---            Conv -- Conv_166 
Supported TIDL layer type ---            Relu -- Relu_167 
Supported TIDL layer type ---          Concat -- Concat_168 
Supported TIDL layer type ---            Conv -- Conv_169 
Supported TIDL layer type ---            Relu -- Relu_170 
Supported TIDL layer type ---            Conv -- Conv_171 
Supported TIDL layer type ---            Relu -- Relu_172 
Supported TIDL layer type ---            Conv -- Conv_173 
Supported TIDL layer type ---            Relu -- Relu_174 
Supported TIDL layer type ---            Conv -- Conv_175 
Supported TIDL layer type ---            Relu -- Relu_176 
Supported TIDL layer type ---          Concat -- Concat_177 
Supported TIDL layer type ---            Conv -- Conv_178 
Supported TIDL layer type ---            Relu -- Relu_179 
Supported TIDL layer type ---            Conv -- Conv_180 
Supported TIDL layer type ---            Relu -- Relu_181 
Supported TIDL layer type ---          Concat -- Concat_182 
Supported TIDL layer type ---            Conv -- Conv_183 
Supported TIDL layer type ---            Relu -- Relu_184 
Supported TIDL layer type ---            Conv -- Conv_185 
Supported TIDL layer type ---            Relu -- Relu_186 
Supported TIDL layer type ---            Conv -- Conv_187 
Supported TIDL layer type ---            Relu -- Relu_188 
Supported TIDL layer type ---            Conv -- Conv_189 
Supported TIDL layer type ---            Relu -- Relu_190 
Supported TIDL layer type ---          Concat -- Concat_191 
Supported TIDL layer type ---            Conv -- Conv_192 
Supported TIDL layer type ---            Relu -- Relu_193 
Supported TIDL layer type ---            Conv -- Conv_194 
Supported TIDL layer type ---            Conv -- Conv_242 
Supported TIDL layer type ---            Conv -- Conv_290 
Supported TIDL layer type ---            Conv -- Conv_338 

Preliminary subgraphs created = 1 
Final number of subgraphs created are : 1, - Offloaded Nodes - 293, Total Nodes - 293 
INFORMATION -- [TIDL_ResizeLayer]  Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.  
INFORMATION -- [TIDL_ResizeLayer]  Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.  
INFORMATION -- [TIDL_ResizeLayer]  Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.  
Running runtimes graphviz - /home/mugundan/edgeai-tidl-tools/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//last//allowedNode.txt ../../../model-artifacts//last//tempDir/graphvizInfo.txt ../../../model-artifacts//last//tempDir/runtimes_visualization.svg 
*** In TIDL_createStateImportFunc *** 
Compute on node : TIDLExecutionProvider_TIDL_0_0
  0,            Conv, 3, 1, images, 167
  1,            Relu, 1, 1, 167, 168
  2,            Conv, 3, 1, 168, 169
  3,            Relu, 1, 1, 169, 170
  4,            Conv, 3, 1, 170, 171
  5,            Relu, 1, 1, 171, 172
  6,            Conv, 3, 1, 172, 180
  7,            Relu, 1, 1, 180, 181
  8,            Conv, 3, 1, 172, 173
  9,            Relu, 1, 1, 173, 174
 10,            Conv, 3, 1, 174, 175
 11,            Relu, 1, 1, 175, 176
 12,            Conv, 3, 1, 176, 177
 13,            Relu, 1, 1, 177, 178
 14,             Add, 2, 1, 174, 179
 15,          Concat, 2, 1, 179, 182
 16,            Conv, 3, 1, 182, 183
 17,            Relu, 1, 1, 183, 184
 18,            Conv, 3, 1, 184, 185
 19,            Relu, 1, 1, 185, 186
 20,            Conv, 3, 1, 186, 204
 21,            Relu, 1, 1, 204, 205
 22,            Conv, 3, 1, 186, 187
 23,            Relu, 1, 1, 187, 188
 24,            Conv, 3, 1, 188, 189
 25,            Relu, 1, 1, 189, 190
 26,            Conv, 3, 1, 190, 191
 27,            Relu, 1, 1, 191, 192
 28,             Add, 2, 1, 188, 193
 29,            Conv, 3, 1, 193, 194
 30,            Relu, 1, 1, 194, 195
 31,            Conv, 3, 1, 195, 196
 32,            Relu, 1, 1, 196, 197
 33,             Add, 2, 1, 193, 198
 34,            Conv, 3, 1, 198, 199
 35,            Relu, 1, 1, 199, 200
 36,            Conv, 3, 1, 200, 201
 37,            Relu, 1, 1, 201, 202
 38,             Add, 2, 1, 198, 203
 39,          Concat, 2, 1, 203, 206
 40,            Conv, 3, 1, 206, 207
 41,            Relu, 1, 1, 207, 208
 42,            Conv, 3, 1, 208, 209
 43,            Relu, 1, 1, 209, 210
 44,            Conv, 3, 1, 210, 228
 45,            Relu, 1, 1, 228, 229
 46,            Conv, 3, 1, 210, 211
 47,            Relu, 1, 1, 211, 212
 48,            Conv, 3, 1, 212, 213
 49,            Relu, 1, 1, 213, 214
 50,            Conv, 3, 1, 214, 215
 51,            Relu, 1, 1, 215, 216
 52,             Add, 2, 1, 212, 217
 53,            Conv, 3, 1, 217, 218
 54,            Relu, 1, 1, 218, 219
 55,            Conv, 3, 1, 219, 220
 56,            Relu, 1, 1, 220, 221
 57,             Add, 2, 1, 217, 222
 58,            Conv, 3, 1, 222, 223
 59,            Relu, 1, 1, 223, 224
 60,            Conv, 3, 1, 224, 225
 61,            Relu, 1, 1, 225, 226
 62,             Add, 2, 1, 222, 227
 63,          Concat, 2, 1, 227, 230
 64,            Conv, 3, 1, 230, 231
 65,            Relu, 1, 1, 231, 232
 66,            Conv, 3, 1, 232, 233
 67,            Relu, 1, 1, 233, 234
 68,            Conv, 3, 1, 234, 242
 69,            Relu, 1, 1, 242, 243
 70,            Conv, 3, 1, 234, 235
 71,            Relu, 1, 1, 235, 236
 72,            Conv, 3, 1, 236, 237
 73,            Relu, 1, 1, 237, 238
 74,            Conv, 3, 1, 238, 239
 75,            Relu, 1, 1, 239, 240
 76,             Add, 2, 1, 236, 241
 77,          Concat, 2, 1, 241, 244
 78,            Conv, 3, 1, 244, 245
 79,            Relu, 1, 1, 245, 246
 80,            Conv, 3, 1, 246, 247
 81,            Relu, 1, 1, 247, 248
 82,            Conv, 3, 1, 248, 249
 83,            Relu, 1, 1, 249, 250
 84,         MaxPool, 1, 1, 250, 251
 85,         MaxPool, 1, 1, 251, 253
 86,         MaxPool, 1, 1, 253, 256
 87,          Concat, 4, 1, 250, 257
 88,            Conv, 3, 1, 257, 258
 89,            Relu, 1, 1, 258, 259
 90,            Conv, 3, 1, 259, 266
 91,            Relu, 1, 1, 266, 267
 92,            Conv, 3, 1, 259, 260
 93,            Relu, 1, 1, 260, 261
 94,            Conv, 3, 1, 261, 262
 95,            Relu, 1, 1, 262, 263
 96,            Conv, 3, 1, 263, 264
 97,            Relu, 1, 1, 264, 265
 98,          Concat, 2, 1, 265, 268
 99,            Conv, 3, 1, 268, 269
100,            Relu, 1, 1, 269, 270
101,            Conv, 3, 1, 270, 271
102,            Relu, 1, 1, 271, 272
103,          Resize, 3, 1, 272, 277
104,          Concat, 2, 1, 277, 278
105,            Conv, 3, 1, 278, 285
106,            Relu, 1, 1, 285, 286
107,            Conv, 3, 1, 278, 279
108,            Relu, 1, 1, 279, 280
109,            Conv, 3, 1, 280, 281
110,            Relu, 1, 1, 281, 282
111,            Conv, 3, 1, 282, 283
112,            Relu, 1, 1, 283, 284
113,          Concat, 2, 1, 284, 287
114,            Conv, 3, 1, 287, 288
115,            Relu, 1, 1, 288, 289
116,            Conv, 3, 1, 289, 290
117,            Relu, 1, 1, 290, 291
118,          Resize, 3, 1, 291, 296
119,          Concat, 2, 1, 296, 297
120,            Conv, 3, 1, 297, 304
121,            Relu, 1, 1, 304, 305
122,            Conv, 3, 1, 297, 298
123,            Relu, 1, 1, 298, 299
124,            Conv, 3, 1, 299, 300
125,            Relu, 1, 1, 300, 301
126,            Conv, 3, 1, 301, 302
127,            Relu, 1, 1, 302, 303
128,          Concat, 2, 1, 303, 306
129,            Conv, 3, 1, 306, 307
130,            Relu, 1, 1, 307, 308
131,            Conv, 3, 1, 308, 309
132,            Relu, 1, 1, 309, 310
133,          Resize, 3, 1, 310, 315
134,          Concat, 2, 1, 315, 316
135,            Conv, 3, 1, 316, 323
136,            Relu, 1, 1, 323, 324
137,            Conv, 3, 1, 316, 317
138,            Relu, 1, 1, 317, 318
139,            Conv, 3, 1, 318, 319
140,            Relu, 1, 1, 319, 320
141,            Conv, 3, 1, 320, 321
142,            Relu, 1, 1, 321, 322
143,          Concat, 2, 1, 322, 325
144,            Conv, 3, 1, 325, 326
145,            Relu, 1, 1, 326, 327
146,            Conv, 3, 1, 327, 328
147,            Relu, 1, 1, 328, 329
148,          Concat, 2, 1, 329, 330
149,            Conv, 3, 1, 330, 337
150,            Relu, 1, 1, 337, 338
151,            Conv, 3, 1, 330, 331
152,            Relu, 1, 1, 331, 332
153,            Conv, 3, 1, 332, 333
154,            Relu, 1, 1, 333, 334
155,            Conv, 3, 1, 334, 335
156,            Relu, 1, 1, 335, 336
157,          Concat, 2, 1, 336, 339
158,            Conv, 3, 1, 339, 340
159,            Relu, 1, 1, 340, 341
160,            Conv, 3, 1, 341, 342
161,            Relu, 1, 1, 342, 343
162,          Concat, 2, 1, 343, 344
163,            Conv, 3, 1, 344, 351
164,            Relu, 1, 1, 351, 352
165,            Conv, 3, 1, 344, 345
166,            Relu, 1, 1, 345, 346
167,            Conv, 3, 1, 346, 347
168,            Relu, 1, 1, 347, 348
169,            Conv, 3, 1, 348, 349
170,            Relu, 1, 1, 349, 350
171,          Concat, 2, 1, 350, 353
172,            Conv, 3, 1, 353, 354
173,            Relu, 1, 1, 354, 355
174,            Conv, 3, 1, 355, 356
175,            Relu, 1, 1, 356, 357
176,          Concat, 2, 1, 357, 358
177,            Conv, 3, 1, 358, 365
178,            Relu, 1, 1, 365, 366
179,            Conv, 3, 1, 358, 359
180,            Relu, 1, 1, 359, 360
181,            Conv, 3, 1, 360, 361
182,            Relu, 1, 1, 361, 362
183,            Conv, 3, 1, 362, 363
184,            Relu, 1, 1, 363, 364
185,          Concat, 2, 1, 364, 367
186,            Conv, 3, 1, 367, 368
187,            Relu, 1, 1, 368, 369
188,            Conv, 3, 1, 369, 556
189,         Reshape, 2, 1, 556, 574
190,       Transpose, 1, 1, 574, 575
191,         Sigmoid, 1, 1, 575, 576
192,           Slice, 5, 1, 576, 609
193,           Slice, 5, 1, 576, 594
194,             Mul, 2, 1, 594, 596
195,             Pow, 2, 1, 596, 599
196,             Mul, 2, 1, 599, 604
197,           Slice, 5, 1, 576, 581
198,             Mul, 2, 1, 581, 583
199,             Sub, 2, 1, 583, 585
200,             Add, 2, 1, 585, 587
201,             Mul, 2, 1, 587, 589
202,          Concat, 3, 1, 589, 610
203,         Reshape, 2, 1, 610, 617
204,            Conv, 3, 1, 355, 494
205,         Reshape, 2, 1, 494, 512
206,       Transpose, 1, 1, 512, 513
207,         Sigmoid, 1, 1, 513, 514
208,           Slice, 5, 1, 514, 547
209,           Slice, 5, 1, 514, 532
210,             Mul, 2, 1, 532, 534
211,             Pow, 2, 1, 534, 537
212,             Mul, 2, 1, 537, 542
213,           Slice, 5, 1, 514, 519
214,             Mul, 2, 1, 519, 521
215,             Sub, 2, 1, 521, 523
216,             Add, 2, 1, 523, 525
217,             Mul, 2, 1, 525, 527
218,          Concat, 3, 1, 527, 548
219,         Reshape, 2, 1, 548, 555
220,            Conv, 3, 1, 341, 432
221,         Reshape, 2, 1, 432, 450
222,       Transpose, 1, 1, 450, 451
223,         Sigmoid, 1, 1, 451, 452
224,           Slice, 5, 1, 452, 485
225,           Slice, 5, 1, 452, 470
226,             Mul, 2, 1, 470, 472
227,             Pow, 2, 1, 472, 475
228,             Mul, 2, 1, 475, 480
229,           Slice, 5, 1, 452, 457
230,             Mul, 2, 1, 457, 459
231,             Sub, 2, 1, 459, 461
232,             Add, 2, 1, 461, 463
233,             Mul, 2, 1, 463, 465
234,          Concat, 3, 1, 465, 486
235,         Reshape, 2, 1, 486, 493
236,            Conv, 3, 1, 327, 370
237,         Reshape, 2, 1, 370, 388
238,       Transpose, 1, 1, 388, 389
239,         Sigmoid, 1, 1, 389, 390
240,           Slice, 5, 1, 390, 423
241,           Slice, 5, 1, 390, 408
242,             Mul, 2, 1, 408, 410
243,             Pow, 2, 1, 410, 413
244,             Mul, 2, 1, 413, 418
245,           Slice, 5, 1, 390, 395
246,             Mul, 2, 1, 395, 397
247,             Sub, 2, 1, 397, 399
248,             Add, 2, 1, 399, 401
249,             Mul, 2, 1, 401, 403
250,          Concat, 3, 1, 403, 424
251,         Reshape, 2, 1, 424, 431
252,          Concat, 4, 1, 431, 618
253,          Gather, 2, 1, 618, 620
254,         Greater, 2, 1, 620, 622
255,          Gather, 2, 1, 622, 626
256,         NonZero, 1, 1, 626, 628
257,       Transpose, 1, 1, 628, 629
258,         Squeeze, 1, 1, 618, 624
259,        GatherND, 2, 1, 624, 630
260,           Slice, 5, 1, 630, 660
261,           Slice, 5, 1, 630, 655
262,             Mul, 2, 1, 655, 661
263,       ReduceMax, 1, 1, 661, 673
264,         Reshape, 2, 1, 673, 678
265,         Greater, 2, 1, 678, 680
266,         NonZero, 1, 1, 680, 682
267,       Transpose, 1, 1, 682, 683
268,          ArgMax, 1, 1, 661, 674
269,            Cast, 1, 1, 674, 675
270,           Slice, 5, 1, 630, 650
271,             Div, 2, 1, 650, 667
272,           Slice, 5, 1, 630, 640
273,             Add, 2, 1, 640, 671
274,           Slice, 5, 1, 630, 645
275,             Div, 2, 1, 645, 664
276,           Slice, 5, 1, 630, 635
277,             Add, 2, 1, 635, 670
278,             Sub, 2, 1, 640, 669
279,             Sub, 2, 1, 635, 668
280,          Concat, 6, 1, 668, 676
281,        GatherND, 2, 1, 676, 684
282,          Gather, 2, 1, 684, 699
283,       Unsqueeze, 1, 1, 699, 702
284,           Slice, 5, 1, 684, 696
285,           Slice, 5, 1, 684, 689
286,             Mul, 2, 1, 689, 691
287,             Add, 2, 1, 696, 697
288,       Unsqueeze, 1, 1, 697, 700
289, NonMaxSuppression, 4, 1, 700, 705
290,          Gather, 2, 1, 705, 707
291,         Squeeze, 1, 1, 707, 708
292,          Gather, 2, 1, 684, detections

Input tensor name -  images 
Output tensor name - detections 
In TIDL_onnxRtImportInit subgraph_name=detections
Layer 0, subgraph id detections, name=370
Layer 1, subgraph id detections, name=432
Layer 2, subgraph id detections, name=494
Layer 3, subgraph id detections, name=556
Layer 4, subgraph id detections, name=images
TIDL Meta PipeLine (Proto) File  : ../../../models/public/last.prototxt  
yolo_v3
yolo_v3
In TIDL_runtimesOptimizeNet: LayerIndex = 197, dataIndex = 193 
Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal

 ************** Frame index 1 : Running float import ************* 
In TIDL_runtimesPostProcessNet 
In TIDL_runtimesPostProcessNet 1
In TIDL_runtimesPostProcessNet 2
In TIDL_runtimesPostProcessNet 3
INFORMATION: [TIDL_ResizeLayer] Resize_107 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Resize_123 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Resize_139 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
****************************************************
**          3 WARNINGS          0 ERRORS          **
****************************************************
In TIDL_runtimesPostProcessNet 4
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 2048
The hard limit is 2048
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.50s:  VX_ZONE_ERROR:Enabled
 0.84s:  VX_ZONE_WARNING:Enabled
 0.9011s:  VX_ZONE_INIT:[tivxInit:185] Initialization Done !!!

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space       , Attribute   , Size(KBytes) 
0           , DDR Cacheable, Persistent  , 15.18    
1           , DDR Cacheable, Persistent  , 0.63     
2           , DDR Cacheable, Scratch     , 16.00    
3           , DDR Cacheable, Scratch     , 4.00     
4           , DDR Cacheable, Scratch     , 56.00    
5           , DDR Cacheable, Persistent  , 409.66   
6           , DDR Cacheable, Scratch     , 102746.27 
7           , DDR Cacheable, Scratch     , 0.12     
8           , DDR Cacheable, Scratch     , 25600.12 
9           , DDR Cacheable, Scratch     , 25923.75 
10          , DDR Cacheable, Persistent  , 1269.23  
11          , DDR Cacheable, Scratch     , 12816.62 
12          , DDR Cacheable, Persistent  , 0.12     
13          , DDR Cacheable, Persistent  , 51465.78 
14          , DDR Cacheable, Persistent  , 0.12     
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 220323.62
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
TIDL init call from ivision API 
Alg Init for Layer # -    1
Alg Init for Layer # -    2
Alg Init for Layer # -    3
Alg Init for Layer # -    4
Alg Init for Layer # -    5
Alg Init for Layer # -    6
Alg Init for Layer # -    7
Alg Init for Layer # -    8
Alg Init for Layer # -    9
Alg Init for Layer # -   10
Alg Init for Layer # -   11
Alg Init for Layer # -   12
Alg Init for Layer # -   13
Alg Init for Layer # -   14
Alg Init for Layer # -   15
Alg Init for Layer # -   16
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Alg Init for Layer # -   20
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Alg Init for Layer # -   27
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Alg Init for Layer # -   31
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Alg Init for Layer # -   33
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Alg Init for Layer # -   35
Alg Init for Layer # -   36
Alg Init for Layer # -   37
Alg Init for Layer # -   38
Alg Init for Layer # -   39
Alg Init for Layer # -   40
Alg Init for Layer # -   41
Alg Init for Layer # -   42
Alg Init for Layer # -   43
Alg Init for Layer # -   44
Alg Init for Layer # -   45
Alg Init for Layer # -   46
Alg Init for Layer # -   47
Alg Init for Layer # -   48
Alg Init for Layer # -   49
Alg Init for Layer # -   50
Alg Init for Layer # -   51
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Alg Init for Layer # -   53
Alg Init for Layer # -   54
Alg Init for Layer # -   55
Alg Init for Layer # -   56
Alg Init for Layer # -   57
Alg Init for Layer # -   58
Alg Init for Layer # -   59
Alg Init for Layer # -   60
Alg Init for Layer # -   61
Alg Init for Layer # -   62
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Alg Init for Layer # -   64
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Alg Init for Layer # -   66
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Alg Init for Layer # -   79
Alg Init for Layer # -   80
Alg Init for Layer # -   81
Alg Init for Layer # -   82
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Alg Init for Layer # -   84
Alg Init for Layer # -   85
Alg Init for Layer # -   86
Alg Init for Layer # -   87
Alg Init for Layer # -   88
Alg Init for Layer # -   89
Alg Init for Layer # -   90
Alg Init for Layer # -   91
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Alg Init for Layer # -   95
Alg Init for Layer # -   96
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Alg Init for Layer # -  102
Alg Init for Layer # -  103
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Alg Init for Layer # -  105
Alg Init for Layer # -  106
Alg Init for Layer # -  107
Alg Init for Layer # -  108
Alg Init for Layer # -  109
Alg Init for Layer # -  110
Alg Init for Layer # -  111
Alg Init for Layer # -  112
Alg Init for Layer # -  113
Alg Init for Layer # -  114
Alg Init for Layer # -  115
Alg Init for Layer # -  116
Alg Init for Layer # -  117
PREEMPTION: Adding a new priority object for targetPriority = 2, handle = 0x7ffb79cbe000
PREEMPTION: Now total number of priority objects = 1 at priorityId = 2,    with new memRec of base = 0x7ffb7c036000 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x7ffb79cbe000, return Addr = 0x7ffb6b0c0db8
************ TIDL_subgraphRtCreate done ************ 
 *******   In TIDL_subgraphRtInvoke  ******** 
TIDL_activate is called with handle : 79cbe000 
Alg Process for Layer # -    0
Alg Process for Layer # -    1
Processing Layer # -    1
End of Layer # -    1 with outPtrs[0] = 0x7ffb2e966000
Alg Process for Layer # -    2
Processing Layer # -    2
End of Layer # -    2 with outPtrs[0] = 0x7ffb2ee1d900
Alg Process for Layer # -    3
Processing Layer # -    3
End of Layer # -    3 with outPtrs[0] = 0x7ffb2f2dca80
Alg Process for Layer # -    4
Processing Layer # -    4
End of Layer # -    4 with outPtrs[0] = 0x7ffb2ff84c80
Alg Process for Layer # -    5
Processing Layer # -    5
End of Layer # -    5 with outPtrs[0] = 0x7ffb305c4d00
Alg Process for Layer # -    6
Processing Layer # -    6
End of Layer # -    6 with outPtrs[0] = 0x7ffb308e4d80
Alg Process for Layer # -    7
Processing Layer # -    7
End of Layer # -    7 with outPtrs[0] = 0x7ffb30c04e00
Alg Process for Layer # -    8
Processing Layer # -    8
End of Layer # -    8 with outPtrs[0] = 0x7ffb2ff84c80
Alg Process for Layer # -    9
Processing Layer # -    9
End of Layer # -    9 with outPtrs[0] = 0x7ffb30f39080
Alg Process for Layer # -   10
Processing Layer # -   10
End of Layer # -   10 with outPtrs[0] = 0x7ffb31259100
Alg Process for Layer # -   11
Processing Layer # -   11
End of Layer # -   11 with outPtrs[0] = 0x7ffb31899180
Alg Process for Layer # -   12
Processing Layer # -   12

but after the 12 layer the compilation stucks, what can be the issue

0 Ramaseshan Subramanian over 1 year ago in reply to Pratik Kedar

Intellectual 490 points

The issue is the memory allocation is too low, I solved tried out the compilation works.

+1 Pratik Kedar over 1 year ago in reply to Ramaseshan Subramanian

TI__Mastermind 24041 points

Great to hear that compilation works for you.

Can we close this issue now ?

0 Ramaseshan Subramanian over 1 year ago in reply to Pratik Kedar

Intellectual 490 points

yes thank you Mr. Pratik for the help

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TDA4VM: YOLOv5s6 compilation using tidl repo