Hi everybody
I have a problem communicating with AT24C1024 ( I2C EEPROM) and CC430F6137
It seems there is a problem with SCL (Serial clock) .
Atmel Product Page:
http://www.atmel.com/dyn/products/product_card.asp?part_id=2488
Datasheet:
http://www.atmel.org/dyn/resources/prod_documents/doc1471.pdf
Here is My code:
SMCLK is 8Mhz
void I2C_Init(void)
{
//..........
// ACLK = REFO = 32kHz, MCLK = SMCLK = 8MHz//
/* Initialize Ports */
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP0 = PM_ACLK; // Map ACLK output to P2.0
P2MAP2 = PM_MCLK; // Map MCLK output to P2.2
P2MAP4 = PM_SMCLK; // Map SMCLK output to P2.4
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT0 + BIT2 + BIT4; // ACLK, MCLK, SMCLK set out to pins
P2SEL |= BIT0 + BIT2 + BIT4; // P2.0,2,4 for debugging purposes
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 + 249; // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (249 + 1) * 32768 = 8MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);
//............................
PMAPPWD = 0x02D52;
P1MAP3 = PM_UCB0SDA;
P1MAP2 = PM_UCB0SCL;
PMAPPWD = 0;
P1SEL |= (BIT2+BIT3);
//............................
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC ; // I2C Master, synchronous mode
UCB0CTL1 = 0xC0 + UCTR + UCSWRST ; // Use ACLK, keep SW reset
UCB0BR0 = 12;
UCB0BR1 = 0x00;
UCB0I2CSA = 0xA0; // E2Prom Address
// UCB0I2COA=0x01a5; // ----> Master Own Address
UCB0CTL1 &= ~UCSWRST;