TDA4VM: ospi clock problem

Hi,

Couple of questions:

• Is this on the EVM or custom board?
• If custom board what is the OSPI part being used?

- Keerthy

Hi

We are based on the EVM board，

It is the SDK8.6 original ospi nor flash, we use the test results of mtd speedtest

thanks

Can you point me to a specific location in the manual or documentation。

Also, I would like to know why ospi has baud rate divisor, which causes reading and writing not as fast as it should be

Hi,

I checked internally if the phy is not active then /8 divider is active so the effective clock is 166/8 which corresponds to approximately 20M

Best Regards,

Keerthy 

thanks

Where is the PHY-enabled switch? Is it in the path below? 

drivers\spi\spi-cadence-quadspi.c

Please specify how to modify it

This is the function in which I investigated the code for the frequency division

Hi,

Have you flashed the phy calibration pattern which will enable phy.

software-dl.ti.com/.../UG-QSPI.html

Best Regards,
Keerthy

yes, I have flash phy.

At SDK8.6, rtos sbl already enable phy , but But I don't see any PHy-related configuration on linux side.

Currently we are testing ospi nor flash on the linux side

Hi,

Make sure the calibration pattern is flashed at the right address.

In driver probe based on calibration pattern availability there is a phy calibration function during probe if calibration passes then PHY will be enabled during all reads.

- Keerthy

I checked internally if the phy is not active then /8 divider is active so the effective clock is 166/8 which corresponds to approximately 20M

-->

Can you tell me the specific path of this frequency division code?

Hi,

ji bocheng said:

Can you tell me the specific path of this frequency division code?

In U-Boot: drivers/spi/cadence_qspi_apb.c

Function: cadence_qspi_apb_config_baudrate_div

/*
         * The baud_div field in the config reg is 4 bits, and the ref clock is
         * divided by 2 * (baud_div + 1). Round up the divider to ensure the
         * SPI clock rate is less than or equal to the requested clock rate.
         */
        div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;

This divisor is used when Phy calibration is not there.

- Keerthy

May I ask if this is hardware controlled, as I did not see any relevant judgment criteria in the code. I checked the code and found that this part will definitely be executed, which means there will definitely be frequency division.

Similar to enabling a register, although frequency division is set, it does not take effect

Hi,

So the issue is that you are seeing lesser Frequency even with phy being used?

You always see 20M even with phy calibration?

Regards,

Keerthy