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AM62A3: I/O drive strength for SDIO and LVCMOS

Gunter Schmer
Genius 14222 points
Part Number: AM62A3

Hi all,

we had a couple questions on the I/O drive strength configurations

[1] For SDIO buffers the drive strength is controlled by SDIOx_CTRL_DRV_STR, however the bit field description only allows the reset default configuration.

What is the default drive strength here and does it match 50 Ohm?

Can the drive strength be controlled, and if so what values can be used?

[2] LVCMOS I/O buffers control the drive strength via DRV_STR. The customer cares most about the higher speed RGMII interface, but also slower speed SPI

Again what is the default drive strength and is it matched to 50Ohm impedence control?

If not are there values that can be used to control the drive strength?

Thanks!

--Gunter