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TDA4VE-Q1: Generate uboot DTSI for specific DDR4 chip

Li Niu
Prodigy 91 points
Part Number: TDA4VE-Q1

We are using TDA4VE for a custom design with a new DDR4 chip (MT53E512M32D1ZW-046 AAT:B).

We tried the "Jacinto7 DDRSS Regsiter Configuration tool", but it has way too many parameters to change ( Hundreds? and many of which are hard to find the on the DRAM datasheet)

The reference design used MT53E2G32D4DT-046 AAT:A, similar DDR just x4 times larger.

We tried by simply changing the size parameters in the tool and compile the file, unfortunately it didn't work.

Can someone point us to the right direction?

Thanks!

Li

  • +1
    TI__Mastermind 38420 points

    Hi Li,

    From what I can tell, the new device you have selected just has a single rank and also has half the channel density (per rank). In addition to updating those two parameters from the "Config" worksheet in the register configuration tool, you would need to update the u-boot global data variables defined in the dram_init_banksize function. (assuming you are using u-boot)

    https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/board/ti/j721s2/evm.c?h=08.06.00.007#n60 

    As a side note, refresh timing (tRFC) is impacted by density, but that should only cause functional failures if not updated when moving from a smaller density to a larger density.

    Li Niu said:
    We tried by simply changing the size parameters in the tool and compile the file, unfortunately it didn't work.

    Can you provide a log illustrating the error?

    What SDK are you using?

    Can you provide the filled-in XLS used to generate the new settings?

    Regards,
    Kevin