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TDA4VH-Q1: How do I configure the compileConstraintsFlag parameter in TIDL?

cheng han
Prodigy 90 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi  TI：

      The board I'm currently using is the 9.0 SDK for TDA4VH.

      I want to export the model via the TIDL PC Importer tool to get the board-side inference time for the PC simulation, so I use the compileConstraintsFlag parameter.

      I found a description of the compileConstraintsFlag parameter in the documentation released by TI.

    

     So, how do I configure the compileConstraintsFlag parameter when exporting the model?

Thank you

  • 0
    TI__Mastermind 24041 points

    Hi,

    As I understand you want to get benchmark of the model.

    You can set debugTraceLevel = 2 and do inference run on host emulation to get the benchmark data.

    However we highly suggest to use EVM to get actual benchmark data, as emulators might not simulate all the hardware latencies.

    For EVM benchmark same flag will produce the data.

  • 0 in reply to Pratik Kedar
    Prodigy 90 points

    Hi,

    So, I see what you mean.

    Can you teach me how to use the compileConstraintsFlag parameter? I would like to know how to configure it.

    Thanks

  • 0 in reply to cheng han
    TI__Mastermind 24041 points

    May I understand what you want to achieve ? What is use use case tied to this flag ?

  • 0 in reply to Pratik Kedar
    Prodigy 90 points

    Hi,

    The board I'm currently using is the 9.0 SDK for TDA4VH.

    I want to export the model via the TIDL PC Importer tool to get the board-side inference time for the PC simulation, so I use the compileConstraintsFlag parameter.

    In PC emulation mode, I configured the parameter compileConstraintsFlag=83886080 and used the TIDL Importer Tool to export the model. After I successfully exported, I was able to find a .csv file about the DSP in the output document, which recorded the time spent for model inference. However, the network time of this .csv file deviates greatly from the actual deployment time of the model.

    So, how do I configure the compileConstraintsFlag parameter to reduce the bias?

    (PC emulation total Network times(us) = 59330.40    Board deploy total natwork times(us) = 235321.60)

    Thanks

  • 0 in reply to cheng han
    TI__Mastermind 24041 points

    The host emulation benchmarks are prone to mem latency / register latency reads/write delays, this number can be taken as reference but not actual reading.

    We recommend our customers to perform benchmarking of models on EVM for final benchmark.