• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 291 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

c6748 GPIO when loading from emulator

Fred Skalka
Intellectual 260 points

We are using the LogicPD SOM.  The C6748 requires the receive UPP port to be activated before the transmitter (at least during emulation). If this is not done, the ethernet port does not respond. I am using the GP0[13] and GP0[14] lines to control the UPP port.  When the emulator is loading (long before any code is run), these GPIO lines are high. LogicPD SOM does not have any pullups on these lines.

Is there a way to defeat this?  Is this normal behavior when running out of ROM?  I would like them to both be low.

  • 0
    TI__Guru*** 125430 points

    Those pins have internal pullups that are active by default after a power-on reset.  You can look in the "Terminal Functions" section of the data sheet to see those pins are in group 0 (CP[0]).  This can be changed at run-time by modifying the PUPD_SEL register (bit 0) as documented in the System Reference Guide.  However, you will not be able to change the fact that after a power-on reset those pins will always be pulled high.  If it's not sufficient to write to this register at run-time then your only option is to add external pull-downs to over-drive the internal pullups at reset.

  • 0 in reply to Brad Griffis
    Intellectual 260 points

    Thank for pointing me to the right part of the data sheet.  Actually, according to note 2 on page, these should be pulled down (weekly) during reset.

  • 0 in reply to Fred Skalka
    TI__Guru*** 125430 points

    Fred Skalka said:
    Actually, according to note 2 on page, these should be pulled down (weekly) during reset.

    That foot note distinguishes behavior at 2 separate times:

    1. While reset is asserted, the pins are weakly pulled low.
    2. After reset is released, the pins are driven according to the default values of the PUPD_SEL register (i.e. high in this case).