TDA4VM: Switching U-Boot console to MCU_UART0 not working

Hi Felix,

I have tried SD Boot with changed console and I have not tried the DFU. Can you first make sure it works with SD boot mode?

- Keerthy

Hi Keerthy, 

I get the same error when trying SD Boot. These are the changes I made to the U-Boot source code:

felix@felix-virtual-machine:~/ti-processor-sdk-linux-j7-evm-08_05_00_08/board-support/u-boot-2021.01+gitAUTOINC+7996ed51f1-g7996ed51f1$ git diff
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 194f587b38..e1ffe73662 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -7,7 +7,7 @@
 
 / {
        chosen {
-               stdout-path = "serial2:115200n8";
+               stdout-path = "serial1:115200n8";
                tick-timer = &timer1;
        };
 
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 5d141445b8..444cfc6ad9 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -13,8 +13,8 @@
 
 / {
        chosen {
-               stdout-path = "serial2:115200n8";
-               bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+               stdout-path = "serial1:115200n8";
+               bootargs = "console=ttyS1,115200n8 earlycon=ns16550a,mmio32,0x40a00000";
        };
 
        gpio_keys: gpio-keys {
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 6cd14390ad..02007aa1b8 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -12,6 +12,7 @@
 
 #ifdef CONFIG_SOC_K3_J721E
 #include "j721e_hardware.h"
+#include "j721e_qos_params.h"
 #endif
 
 #ifdef CONFIG_SOC_K3_J721S2
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 4e23164f92..770aee0214 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -189,6 +189,278 @@ void do_dt_magic(void)
 }
 #endif
 
+void setup_navss_nb(void)
+{
+        /* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
+        writel(2, NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+        writel(2, NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
+void setup_vpac_qos(void)
+{
+       unsigned int channel, group;
+
+       /* vpac data master 0  */
+       for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_DATA0_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA0_CBASS_MAP(channel));
+       }
+
+       /* vpac data master 1  */
+       for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_DATA1_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA1_CBASS_MAP(channel));
+       }
+
+       /* vpac ldc0  */
+       for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4), (uintptr_t)QOS_VPAC0_LDC0_CBASS_MAP(channel));
+       }
+
+}
+
+void setup_dmpac_qos(void)
+{
+       unsigned int channel;
+
+       /* dmpac data  */
+       for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel) {
+
+               writel((QOS_DMPAC0_DATA_ATYPE << 28), (uintptr_t)QOS_DMPAC0_DATA_CBASS_MAP(channel));
+       }
+}
+
+void setup_dss_qos(void)
+{
+       unsigned int channel, group;
+
+       /* two master ports: dma and fbdc */
+       /* two groups: SRAM and DDR */
+       /* 10 channels: (pipe << 1) | is_second_buffer */
+
+       /* master port 1 (dma) */
+       for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4), (uintptr_t)QOS_DSS0_DMA_CBASS_MAP(channel));
+       }
+
+       /* master port 2 (fbdc) */
+       for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel) {
+
+               writel((QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4), (uintptr_t)QOS_DSS0_FBDC_CBASS_MAP(channel));
+       }
+}
+
+void setup_gpu_qos(void)
+{
+       unsigned int channel, group;
+
+       /* gpu m0 rd */
+       for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel) {
+
+               if(channel == 0)
+               {
+                       writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+               }
+               else
+               {
+                       writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+               }
+       }
+
+       /* gpu m0 wr */
+       for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_WR_CBASS_MAP(channel));
+       }
+
+       /* gpu m1 rd */
+       for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel) {
+
+               if(channel == 0)
+               {
+                       writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+               }
+               else
+               {
+                       writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+               }
+       }
+
+       /* gpu m1 wr */
+       for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_encoder_qos(void)
+{
+       unsigned int channel, group;
+
+       /* encoder rd */
+       for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_RD_CBASS_MAP(channel));
+       }
+
+       /* encoder wr */
+       for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_decoder_qos(void)
+{
+       unsigned int channel, group;
+
+       /* decoder rd */
+       for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_RD_CBASS_MAP(channel));
+       }
+
+       /* decoder wr */
+       for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_c66_qos(void)
+{
+       unsigned int channel, group;
+
+       /* c66_0 mdma */
+       for (group = 0; group < QOS_C66SS0_MDMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_C66SS0_MDMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_C66SS0_MDMA_ATYPE << 28) | (QOS_C66SS0_MDMA_PRIORITY << 12) | (QOS_C66SS0_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS0_MDMA_CBASS_MAP(channel));
+       }
+
+       /* c66_1 mdma */
+       for (group = 0; group < QOS_C66SS1_MDMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_C66SS1_MDMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_C66SS1_MDMA_ATYPE << 28) | (QOS_C66SS1_MDMA_PRIORITY << 12) | (QOS_C66SS1_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS1_MDMA_CBASS_MAP(channel));
+       }
+}
+
+void setup_main_r5f_qos(void)
+{
+       unsigned int channel, group;
+
+       /* R5FSS0 core0 - read */
+       for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core0 - write */
+       for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core1 - read */
+       for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core1 - write */
+       for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel));
+       }
+
+}
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
@@ -324,6 +596,18 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
+
+       if (soc_is_j721e()) {
+               setup_navss_nb();
+               setup_c66_qos();
+               setup_main_r5f_qos();
+               setup_vpac_qos();
+               setup_dmpac_qos();
+               setup_dss_qos();
+               setup_gpu_qos();
+               setup_encoder_qos();
+       }
+
        spl_enable_dcache();
 }
 
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index e71a862a6f..003fa4f372 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_GPIO_HOG=y
 # CONFIG_PSCI_RESET is not set
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 17683bbe73..f0bb5e9c2d 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -719,6 +719,23 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
        writel(val, base + DDRSS_ECC_CTRL_REG);
 }
 
+#ifdef CONFIG_K3_J721E_DDRSS
+#define DDRSS_V2A_LPT_DEF_PRI_MAP_REG (0x02980030u)
+#define DDRSS_V2A_HPT_DEF_PRI_MAP_REG (0x0298004Cu)
+#define DDRSS_V2A_LPT_HPT_PRI_MAP_VAL (0x77777777u)
+
+void j721e_lpddr4_priority_map(void)
+{
+       /* Override defaults with a flattened priority */
+       /* This makes VBUSM.C priority take effect */
+    /* LPT */
+    writel(DDRSS_V2A_LPT_HPT_PRI_MAP_VAL, (uintptr_t)DDRSS_V2A_LPT_DEF_PRI_MAP_REG);
+
+    /* HPT */
+    writel(DDRSS_V2A_LPT_HPT_PRI_MAP_VAL, (uintptr_t)DDRSS_V2A_HPT_DEF_PRI_MAP_REG);
+}
+#endif
+
 #define AM64_DDRSS_SS_BASE  0x0F300000
 static int k3_ddrss_probe(struct udevice *dev)
 {
@@ -751,6 +768,10 @@ static int k3_ddrss_probe(struct udevice *dev)
        if (ret)
                return ret;
 
+#ifdef CONFIG_K3_J721E_DDRSS
+    j721e_lpddr4_priority_map();
+#endif
+
        k3_lpddr4_start(ddrss);
 
        if (ddrss->ti_ecc_enabled) {
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 50b018b6ed..874f7bc48c 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -86,9 +86,9 @@
                        "setenv name_fdt k3-j721e-sk.dtb; fi;"  \
                "setenv fdtfile ${name_fdt}\0"                          \
        "name_kern=Image\0"                                             \
-       "console=ttyS2,115200n8\0"                                      \
+       "console=ttyS1,115200n8\0"                                      \
        "args_all=setenv optargs ${optargs} "                           \
-               "earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}\0"     \
+               "earlycon=ns16550a,mmio32,0x40a00000 ${mtdparts}\0"     \
        "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
 
 #define PARTS_DEFAULT \
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index a598607ead..f7d79247d6 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -12,7 +12,7 @@
 #include <linux/stringify.h>
 
 #ifndef CONSOLEDEV
-#define CONSOLEDEV "ttyS2"
+#define CONSOLEDEV "ttyS1"
 #endif
 
 #ifndef PARTS_DEFAULT

There were some uncommited changes already present in this directory, which I did not modify. 

The changes to ATF repository are:

felix@felix-virtual-machine:~/ti-processor-sdk-linux-j7-evm-08_05_00_08/board-support/trusted-firmware-a-2.6$ git diff
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index 81a383a72..3bc8b671b 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -95,14 +95,14 @@
 
 /* Platform default console definitions */
 #ifndef K3_USART_BASE
-#define K3_USART_BASE                  (0x02800000 + 0x10000 * K3_USART)
+#define K3_USART_BASE                  0x40a00000
 #endif
 
 /* USART has a default size for address space */
 #define K3_USART_SIZE 0x1000
 
 #ifndef K3_USART_CLK_SPEED
-#define K3_USART_CLK_SPEED 48000000
+#define K3_USART_CLK_SPEED 96000000
 #endif
 
 /* Crash console defaults */
felix@felix-virtual-machine:~/ti-processor-sdk-linux-j7-evm-08_05_00_08/board-support/trusted-firmware-a-2.6$ 

ATF was built via:

make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed

Afterwards, I copied bl31.bin to the prebuilt directory. U-Boot was built via:

make u-boot

Thanks for your help and best regards,

Felix

Update: Doing the same changes on vanilla PSDK Linux v07.03 works fine with SD Boot and USB Boot (Board boots without errors). Is it possible to update the FAQ for newer versions of PSDK Linux? Prefereably v09.01? 

Thanks for your help and best regards,

Felix

Felix,

felix_123 said:

Update: Doing the same changes on vanilla PSDK Linux v07.03 works fine with SD Boot and USB Boot (Board boots without errors). Is it possible to update the FAQ for newer versions of PSDK Linux? Prefereably v09.01? 

Thanks for the updates! There might be an issue on 9.01 SDK with the MCU_UART clocking. We will need time to check with the internal team on the issue.

Can you share the failure logs from SD boot?

- Keerthy