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About the uPP internal DMA write timing to the memory

RY9983
Guru 10570 points
Other Parts Discussed in Thread: OMAPL138

Hello.

I have a question about the write timing of uPP internal DMA to the memory.
The uPP Users guide(SPRUgj5b) describes that the internal DMA controller always writes data in bursts of 64bytes.
For example, when it receive the 100bytes, I think that the burst write perform just once.
In other words, only 64bytes of data is written to the memory.

Could you let me know?
 - Is it correct that my considering?
 - When the rest of 36bytes write to the memory?

=============
SPRUgj5b (P15)
The internal DMA controller always writes data in bursts of 64 bytes.
=============

Best regards,
RY

  • 0
    Guru 10570 points

    Hello.

    Sorry, the device is OMAPL138.
    Please help.

    Best regards,
    RY

     

  • 0 in reply to RY9983
    TI__Expert 8890 points

    RY,

    The uPP peripheral will actually write the "remainder" bytes even if the overall transfer size is not divisible by the DMA burst size.  When the end of window (EOW) event fires, the final DMA burst has already fired.  This means that the entire data buffer should already be filled (in receive mode) or consumed (in transmit mode).

    There may be some slight latency between the EOW event and the final DMA burst completion.  You can monitor the UPxS2.ACT register field(s) to determine whether or not the final DMA burst has actually completed.

    Hope this helps.