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TDA4VH-Q1: Enable DDR ECC in SPL on MCU1-0 Failed

Kevin Peng
Expert 4208 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi TI Experts,

Customer is working on TDA4VH SDK9.0.

They are referring the below link to implement inline ddr ecc.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/09_01_00_06/exports/docs/psdk_rtos/docs/user_guide/developer_notes_ddr_inline_ecc.html

They want to implement it on MCU1_0.

Also they configured the MCU1_0 to run in MSMC or OCMC to avoid using DDR shown below.

However, after enabling the ddr ecc code, the linux run will die shown below.

May I know in the current SDK (SDK9.0 or the newly released SDK9.1), do we support enable inline ecc check in SPL on MCU1_0?

Thanks a lot!

Kevin

  • 0
    TI__Expert 4208 points

    Hi TI Experts,

    I provide some more details below, thanks!

    Customer also tried to use rtos-sdk to enable ddr ecc on mcu1_0 in SPL. 

    And they want the safety code independence, so they include demo csl_ecc_test_app to enable ddr ecc in mcu1-0.

    As we know csl_ecc_test_app is working good in CCS, but when they integrate to MCU1_0 in SPL, it will cause Linux to die mentioned above.

    So this post is to discuss the feasibility to use rtos-sdk to enable ddr ecc on MCU1_0 in SPL in our current SDK release.

    If we have to use linux-sdk to achieve this goal, would there be anything needed based on the current SDK?

    Thanks a lot!

    Kevin

  • +1 in reply to Kevin Peng
    TI__Guru**** 166360 points

    Hi Kevin,

    We have the reference code on top of 9.0 SDK as the SDK does not have it by default. We do not have RTOS based code.
    So customer can try to refer the SPL based code and port it over.

    - Keerthy