Hi,
The July2011 C6678 data sheet says the following about the PASS PLL:
7.8 PASS PLL
The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select the input source of PASS PLL as either the output of Main PLL mux or the PASSCLK clock reference sources.
The text in bold is not the same as the diagram (Fig7-29). The diagram shows the PACLKSEL selecting between the CORECLK(P/N) package pins and the PASSCLK(P/N) package pins i.e. it is not coming from the Main PLL mux.
I am assuming the diagram is correct and the text is a hangover from the C6670 device. Am I correct?
Cheers
Richard
