Hi,
I would like to know if the AM623 supports in its QSPI interface non-sequential accesses to a QSPI type SRAM memory (e.g. IS66WVQ2M4DALL or similar).
Regards.
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Hi,
I would like to know if the AM623 supports in its QSPI interface non-sequential accesses to a QSPI type SRAM memory (e.g. IS66WVQ2M4DALL or similar).
Regards.
Hello Amílcar Barca
I assume you are checking if the QSPI support IS66WVQ2M4D memory.
The QSPI is mostly designed / interfaced for flash memory.
Could you check with the SRAM provider to confirm the functioning as i check internally.
Regards,
Sreenivasa
Regards,
Hello Amílcar Barca
I checked internally with the design.
This is not something that has been tested or being considered for testing for now.
The answer is -> this is not currently supported.
Regards,
Sreenivasa
Hi,
Thanks. In this case, what alternative can they use ? They need to write data in a non-volatile memory at up to 20Mbytes and the number of times we access the memory is way higher than what can a flash can withstand.
The GPMC bus is already used.
Is there an alternative ? Can we use the PRU to interface with the SRAM ?
Regards
Geoffrey
Geoffrey
We do not have any recommendations/examples to show PRU interfacing with SRAMs etc. Such implementations are potentially feasible, but will require customer to do all the relevant testing across their use-case conditions.
I do not really recommend going the PRU route.
What is GPMC being used for in the system?
Hi Mukul,
GPMC is used for FPGA communication (we exchanged about it by emails).
Might use the PRU instead of the GPMC for the FPGA communication and the GPMC to interface with the SRAM instead but it does not change the fact that PRU will need to be programmed.
Any other alternative ?
Regards
Geoffrey
Hello Geoffrey
I do not see any quick alternative to suggest given the data rate expectation.
I will have to check if the flash experts have any thought.
The experts are on vacation till the 8th of January 2024.
Regards,
Sreenivasa