SK-AM62B: AM62B EVM JTAG testing is mul-function?

Hi Rio,

On HS devices, it is not possible to connect to the TIFS core. So, there is no way for the CCS to connect to the TIFS core & run the TIFS core GEL script meant to initialize the PLLs or clocks for the peripherals including DDR. This eventually leads the failure in trying to run the DDR initialization GEL script from any core.

The only option to perform the DDR initialization via GEL scripts, assuming this is a strict requirement, is to boot SBL/SPL with DDR initialization disabled. The SBL/SPL once boots results in the TIFS running with the TIFS firmware. So, the SBL/SPL can enable the clocks for the DDR after which the debugger can be connected to the R5F core & the DDR initialization GEL script can be run.

Please find the procedure below for the same with SBL NULL from the AM62x MCU+ SDK v9.

Preparing the SBL NULL

1) Disable the DDR module in the sysconfig of the SBL NULL.

2) Apply the following patch in the main.c file of the SBL NULL. This patch enables the clocks for the DDR & also traps the control into an infinite loop just after so as to ensure the SBL NULL does not interfere with the debug activities.

diff --git a/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
index 02569427..b5df45ca 100644
--- a/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
+++ b/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
@@ -89,6 +89,30 @@ int32_t App_loadSelfcoreImage(Bootloader_Handle bootHandle, Bootloader_BootImage
     return status;
 }
 
+int32_t DDR_enableClock()
+{
+    #define SOC_MODULES_END     (0xFFFFFFFFu)
+
+    uint32_t gSocModules[] = {
+        TISCI_DEV_EMIF_DATA_ISO_VD,
+        TISCI_DEV_DDR16SS0,
+
+        SOC_MODULES_END,
+    };
+
+    int32_t status;
+    uint32_t i = 0;
+
+    while(gSocModules[i]!=SOC_MODULES_END)
+    {
+        status = SOC_moduleClockEnable(gSocModules[i], 1);
+        DebugP_assertNoLog(status == SystemP_SUCCESS);
+        i++;
+    }
+
+    return status;
+}
+
 int main()
 {
     int32_t status;
@@ -107,6 +131,9 @@ int main()
     DebugP_log("\r\n");
     DebugP_log("Starting NULL Bootloader ... \r\n");
 
+    DDR_enableClock();
+    loop_forever();
+
     status = Board_driversOpen();
     DebugP_assert(status == SystemP_SUCCESS);
     Bootloader_profileAddProfilePoint("Board_driversOpen");

3) Due to a bug which restricts the debug read/writes into certain regions which happens to cover the region required by the GEL script to perform the DDR initialization, replace the TIFS firmware & its certificate (source\drivers\sciclient\soc\am62x\sysfw-hs-fs*.bin) with the respective firmwares taken from the following commit

https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/commit/?h=ti-linux-firmware&id=8e1defd09d400588470c6de49705dd32f0c17937

4) Rebuild the SBL NULL.

Attaching the SBL NULL image with all the above changes just in case you happen to use TI board

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6758.sbl_5F00_null.release.hs_5F00_fs.tiimage

Boot the SBL NULL

There are many ways to boot the SBL NULL image (*.hs_fs.tiimage).

1) The SBL NULL can be booted directly in UART boot mode with the help of Teraterm: File -> Transfer -> XMODEM -> Send... -> SBL NULL image. This method will be slow so not really useful in case frequent PORs are done & so SBL NULL needs to be booted again & again.

2) Use DFU boot mode. This will be much faster compared to UART boot.

dfu-util -a bootloader -D examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/ti-arm-clang/sbl_null.release.hs_fs.tiimage

3) Flash the SBL NULL using UART Uniflash in UART boot mode. Switch the boot mode to the flashed boot media.

In all cases, the expected output on the UART console is

Starting NULL Bootloader ...

After dumping this log, the control gets stuck into an infinite loop so no more logs.

DDR initialization GEL script

1) Once it is confirmed the SBL NULL is booted, connect to the R5F core & run the DDR initialization GEL script as usual.

I have also attached a screen recording showing the procedure running successfully just in case it helps.

Regards,

Prashant

Hi jing,

Yes, the procedure with necessary changes will work for AM62A as well. The GEL scripts will be available on choosing AM62A_SK_EVM in the Target Configuration file as shown below

Attaching the SBL NULL patch

diff --git a/examples/drivers/boot/sbl_null/am62ax-sk/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_null/am62ax-sk/r5fss0-0_nortos/main.c
index 2455058..9af5bf7 100644
--- a/examples/drivers/boot/sbl_null/am62ax-sk/r5fss0-0_nortos/main.c
+++ b/examples/drivers/boot/sbl_null/am62ax-sk/r5fss0-0_nortos/main.c
@@ -90,6 +90,30 @@ int32_t App_loadSelfcoreImage(Bootloader_Handle bootHandle, Bootloader_BootImage
     return status;
 }
 
+int32_t DDR_enableClock()
+{
+    #define SOC_MODULES_END     (0xFFFFFFFFu)
+
+    uint32_t gSocModules[] = {
+        TISCI_DEV_DDR32SS0,
+        TISCI_DEV_EMIF_DATA_ISO_VD,
+
+        SOC_MODULES_END,
+    };
+
+    int32_t status;
+    uint32_t i = 0;
+
+    while(gSocModules[i]!=SOC_MODULES_END)
+    {
+        status = SOC_moduleClockEnable(gSocModules[i], 1);
+        DebugP_assertNoLog(status == SystemP_SUCCESS);
+        i++;
+    }
+
+    return status;
+}
+
 int main()
 {
     int32_t status;
@@ -111,6 +135,9 @@ int main()
     DebugP_log("\r\n");
     DebugP_log("Starting NULL Bootloader ... \r\n");
 
+    DDR_enableClock();
+    loop_forever();
+
     status = Board_driversOpen();
     DebugP_assert(status == SystemP_SUCCESS);
     Bootloader_profileAddProfilePoint("Board_driversOpen");

Attaching the SBL NULL HSFS image which should work as it is on custom board as well

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6470.sbl_5F00_null.release.hs_5F00_fs.tiimage

Regards,

Prashant

Hi Jing,

If you are using UART boot mode, I would recommend to use the Teraterm to send the SBL NULL image

Regards,

Prashant

Hi Rio,

I already shared the SBL NULL image for AM62X HSFS as well in my very first response. That image should have worked for custom board as well. Anyways, I have reattached the image with other modifications to totally remove any board dependency & so should definitely work as it is on custom board.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6428.sbl_5F00_null.release.hs_5F00_fs.tiimage

Regards,

Prashant

Hi Rio,

I see the issue. This happens because the R5F core is a 32-bit cpu & you are trying access an address of more than 32 bits. If this is necessary, this access has to be done from the A53 cores which will require changes in the SBL NULL to enable the A53 clocks & reset it.

Attached is the patch with necessary modifications.

diff --git a/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
index 02569427..3ca7fc8d 100644
--- a/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
+++ b/examples/drivers/boot/sbl_null/am62x-sk/r5fss0-0_nortos/main.c
@@ -89,6 +89,42 @@ int32_t App_loadSelfcoreImage(Bootloader_Handle bootHandle, Bootloader_BootImage
     return status;
 }
 
+int32_t DDR_enableClock()
+{
+    #define SOC_MODULES_END     (0xFFFFFFFFu)
+
+    uint32_t gSocModules[] = {
+        TISCI_DEV_EMIF_DATA_ISO_VD,
+        TISCI_DEV_DDR16SS0,
+
+        SOC_MODULES_END,
+    };
+
+    int32_t status;
+    uint32_t i = 0;
+
+    while(gSocModules[i]!=SOC_MODULES_END)
+    {
+        status = SOC_moduleClockEnable(gSocModules[i], 1);
+        DebugP_assertNoLog(status == SystemP_SUCCESS);
+        i++;
+    }
+
+    return status;
+}
+
+void A53_enableClock()
+{
+    uint32_t cpuId = CSL_CORE_ID_A53SS0_0;
+    uint32_t clkHz = Bootloader_socCpuGetClkDefault(cpuId);
+
+    Bootloader_socCpuRequest(cpuId);
+    Bootloader_socCpuSetClock(cpuId, clkHz);
+    Bootloader_socCpuPowerOnReset(cpuId, NULL);
+    Bootloader_socCpuResetRelease(cpuId, 0);
+    Bootloader_socCpuRelease(cpuId);
+}
+
 int main()
 {
     int32_t status;
@@ -107,6 +143,10 @@ int main()
     DebugP_log("\r\n");
     DebugP_log("Starting NULL Bootloader ... \r\n");
 
+    DDR_enableClock();
+    A53_enableClock();
+    loop_forever();
+
     status = Board_driversOpen();
     DebugP_assert(status == SystemP_SUCCESS);
     Bootloader_profileAddProfilePoint("Board_driversOpen");
@@ -114,6 +154,7 @@ int main()
     status = Sciclient_getVersionCheck(1);
     Bootloader_profileAddProfilePoint("Sciclient Get Version");
 
+    #if 0
     if(SystemP_SUCCESS == status)
     {
         Bootloader_BootImageInfo bootImageInfo;
@@ -178,6 +219,7 @@ int main()
 
         Bootloader_close(bootHandle);
     }
+    #endif
 
     if(status != SystemP_SUCCESS )
     {

Attached is the SBL NULL image

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/7367.sbl_5F00_null.release.hs_5F00_fs.tiimage

Regards,

Prashant