Hi,
We are having a problem with EDMA3/McBSP/McASP configuration in the OMAP-L138. We are using the McBSP for proprietary network communication and the McASP for audio in- and out of our system. The EDMA CH0/1, 4/5 is used to transfer data to/from L2 RAM internal memory.
The problem is seen as data missing (one word) in the buffer for the received network data and it occurs shortly after start up of our board. The ARM is running Linux and booting the DSP through dsplink. There does not seem to be any EDMA indication of errors when the problem occurs.
We have configured our internal devices like this:
McBSP RX: Word length = 16 bits. CLKR clk external and running at 41 MHz. FSR is external. No FIFO.
McBSP TX: Word length = 16 bits. CLKX external and running at 8.192 MHz. FSX is generated by sample rate generator. No FIFO.
McASP RX: FIFO used, eight 32 bit words/event. CLK external and running at 2.048 MHz. External frame sync.
McASP TX: FIFO used, four times 8 32-bit words/event. CLK external and running at 2.048 MHz. External frame sync.
The EDMA channels are configured like this:
EDMA CH0 (audio in):
//Transfer options (AB-sync). Enable transfer complete interrupt, IPR0 Enable, Normal completion
edma30cc_0_Regs->PARAMSET[0].OPT=0x00100004u;
//edma30cc_0_Regs->PARAMSET[0].OPT=0x00000004u; //Transfer options (AB-sync)
edma30cc_0_Regs->PARAMSET[0].SRC=0x01D02010; //Channel source address
edma30cc_0_Regs->PARAMSET[0].A_B_CNT=0x00080004u; //8 samples of 4 bytes
edma30cc_0_Regs->PARAMSET[0].DST=(Uint32)(&LineInBuf)+AUDIO_IN_OFFSET*8; //Channel destination address
edma30cc_0_Regs->PARAMSET[0].SRC_DST_BIDX=0x00040000u; //Dest.: Increase with the size of an array, Source: No increment.
//Link to PaRAM 34 - offset address
edma30cc_0_Regs->PARAMSET[0].LINK_BCNTRLD=(Uint32)&(edma30cc_0_Regs->PARAMSET[34])&0x0000FFE0;
edma30cc_0_Regs->PARAMSET[0].CCNT=0x00000010u; //16 frame - 8 samples (4 lineA - 4 lineB)
edma30cc_0_Regs->PARAMSET[0].SRC_DST_CIDX=0x00200000u; //Destination C index - 4 bytes*8 addr. offset
EDMA CH1 (audio out):
The audio transmit channel is configured as this:
//Transfer options (AB-sync)
edma30cc_0_Regs->PARAMSET[1].OPT=0x00000004u;
//Channel source address = outgoing bus data buffer
edma30cc_0_Regs->PARAMSET[1].SRC=(Uint32)(&ZoneAudioOutBuf)+AUDIO_OUT_OFFSET*8;
//4 samples of 4 bytes
edma30cc_0_Regs->PARAMSET[1].A_B_CNT=0x00200004u;
//Channel destination address = McASP1 > DMA port transmit address.
edma30cc_0_Regs->PARAMSET[1].DST=0x01D02000;
//Source: Increase with the size of an array (1. dimension), Dest.: No increment.
edma30cc_0_Regs->PARAMSET[1].SRC_DST_BIDX=0x00000004u;
//Link to PaRAM 38 - "link-to-self"
edma30cc_0_Regs->PARAMSET[1].LINK_BCNTRLD=(Uint32)&(edma30cc_0_Regs->PARAMSET[38])&0x0000FFE0;
//Restart after all zone buffers have been transferred (EDMA transfers only 4 samples pr. event)
edma30cc_0_Regs->PARAMSET[1].CCNT=0x00000010u;
//Add 4 bytes*4 zones to start address after transfer of a frame (4 zones).
edma30cc_0_Regs->PARAMSET[1].SRC_DST_CIDX=0x00000080u;
//Use event que 0 for EDMA channel 0 => EDMA TC0 is used.
CSL_FINS(edma30cc_0_Regs->DMAQNUM[0], EDMA3CC_DMAQNUM_E0, 0);
//Use event que 0 for EDMA channel 1 => EDMA TC0 is used.
CSL_FINS(edma30cc_0_Regs->DMAQNUM[0], EDMA3CC_DMAQNUM_E1, 0);
EDMA CH4 (Network in):
//Transfer options
edma30cc_0_Regs->PARAMSET[4].OPT=0x00000000u;
//Channel source address
edma30cc_0_Regs->PARAMSET[4].SRC=(Uint32)&(mcbsp1Regs->DRR);
//1. and 2. dimension: 8192 samples of 2 bytes
edma30cc_0_Regs->PARAMSET[4].A_B_CNT=0x20000002u;
//Channel destination address
edma30cc_0_Regs->PARAMSET[4].DST=(Uint32)(&IngoingDataBuf[0]);
//Source: No increment, Destination: increase with 2 bytes, link to PaRAM 64 - offset address
edma30cc_0_Regs->PARAMSET[4].SRC_DST_BIDX=0x00020000u;
edma30cc_0_Regs->PARAMSET[4].LINK_BCNTRLD=(Uint32)&(edma30cc_0_Regs->PARAMSET[64])&0x0000FFE0;
//One frame
edma30cc_0_Regs->PARAMSET[4].CCNT=0x00000001u;
//Distance between frames - unused
edma30cc_0_Regs->PARAMSET[4].SRC_DST_CIDX=0x00000000u;
EDMA CH5 (Network out):
//Enable transfer complete interrupt, IPR5 Enable, Early completion
edma30cc_0_Regs->PARAMSET[5].OPT=0x00105800u;
//Channel source address = outgoing bus data buffer
edma30cc_0_Regs->PARAMSET[5].SRC=(Uint32)(&OutgoingDataBuffers[0][0]);
//960 arrays of 2 byte.
edma30cc_0_Regs->PARAMSET[5].A_B_CNT=0x03C00002u;
//Channel destination address = McBSP1 TX reg
edma30cc_0_Regs->PARAMSET[5].DST=(Uint32)&(mcbsp1Regs->DXR);
edma30cc_0_Regs->PARAMSET[5].SRC_DST_BIDX=0x00000002u;
//Source: Increase with 2 bytes, Destination: No increment, link to PaRAM 65 - "link-to-self"
edma30cc_0_Regs->PARAMSET[5].CCNT=0x00000001u;
//Distance between frames - unused
edma30cc_0_Regs->PARAMSET[5].SRC_DST_CIDX=0x00000000u;
//Use event que 0 for EDMA channel 4 (inbus) => EDMA TC0 is used.
CSL_FINS(edma30cc_0_Regs->DMAQNUM[0], EDMA3CC_DMAQNUM_E4, 0);
//Use event que 0 for EDMA channel 5 (outbus) => EDMA TC0 is used.
CSL_FINS(edma30cc_0_Regs->DMAQNUM[0], EDMA3CC_DMAQNUM_E5, 0);
The priority of EDMATC0 is set to 0 in MSTPRI reg, and all other priorities are set to 1 or lower.The OMAP is running at 456 MHz.
Can anybody help me solve this problem?